CN107798203B - A kind of combinational logic circuit equivalence detection method - Google Patents
A kind of combinational logic circuit equivalence detection method Download PDFInfo
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Abstract
The invention discloses a kind of combinational logic circuit equivalence detection methods, by extending complementary minor concept, Logic coverage equivalence test problems are divided into and resolve into circuit comprising detecting subproblem, one of circuit expressions formula is sought one by one to the complementary minor of another each product term of circuit expressions formula, then judge on the basis of establishing the Shannon structure chart of each product term complementary minor its whether tautology, finally according to tautology differentiate result determine two circuits between whether cover equivalent relation；Advantage is that product term complementary minor decompose to logical function and depression of order is handled by seeking, to accelerate covering equivalence verifying speed, operability and detection efficiency are higher, it and is not in memory explosion issues, experimental configuration shows that method of the invention is stablized effectively, and the test result of circuit obtained by three kinds of algorithms to EXPRESSO Integrated Simulation shows, compared with two kinds of detection algorithms based on truth table and BDD, there is apparent speed advantage.
Description
Technical field
The present invention relates to a kind of detection methods, more particularly, to a kind of combinational logic circuit equivalence detection method.
Background technique
Logic equivalence detects for the purpose of 2 different combinational circuit Non-inferiority tests of logical layer expression formula, according to giving
The logical expression of 2 fixed combinational circuits, detects whether they realize identical logic function.Combinational logic circuit etc. at present
Effect property detection method mainly has algebraic approach, truth table criterion and functional method.
Algebraic approach is a kind of direct-vision method for examining combinational logic circuit equivalence, and this method is basic using logic algebra
The logical expression of 2 combinational circuits of formula manipulation, if can obtain it is identical as a result, if 2 combinational circuits logical expression
It is logically equivalent.But since the fundamental formular quantity of logic algebra is more, in this method, if fundamental formular selects, is selected
The links such as the application order of dry fundamental formular and the selected selection of each fundamental formular process object there are it is a variety of can
Scheme is selected, the selection of concrete scheme and circuit structure have direct relation, still available without unified feasible guideline.Therefore,
Detection tool is carried out to combinational logic circuit equivalence using algebraic approach to bear the character of much blindness, this method poor operability, and count
Calculation amount and calculating time, detection efficiency was very low also with circuit scale sharp increase, seldom individually used in practice.
Truth table criterion using truth table by determining the logical expression of 2 combinational circuits with the presence or absence of logic etc.
Effect relationship.In this method, all possible combinations of the input variable value of 2 combinational circuits are substituted into 2 combinational circuits one by one
Logical expression, then according to whether all identical you can get it the conclusion of result.Although this method can be operated relative to algebraic approach
Property it is higher, however, it will be apparent that when circuit scale increase when, the input variable value of combinational circuit will also sharply increase, this method
Time overhead will sharply increase, detection efficiency is still lower.
Functional method is currently used combinational logic circuit equivalence detection method, and this method is by 2 combinational circuits
It is expressed as a kind of canonical form, such as binary decision figure (BDD), they are equivalent if the canonical form isomorphism of 2 combinational circuits.
The problem of operability is also not present in this method, although increasing relative to truth table criterion detection efficiency, still not
It is able to satisfy the demand of current ultra-large circuit, and this method can face asking for memory explosion under certain input variable sequences
Topic.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of operability and detection efficiency are higher, and be not in
The combinational logic circuit equivalence detection method of memory explosion issues.
The technical scheme of the invention to solve the technical problem is: a kind of combinational logic circuit equivalence detection side
Method, comprising the following steps:
(1) two combinational circuits to be detected are denoted as a and b, wherein the logical expression of a are as follows:
The logical expression of b are as follows:
Wherein, n is the variable number of combinational circuit a and b, and ∑ is summation operation symbol, and p is the product term of combinational circuit a
Quantity, q are the quantity of the product term of combinational circuit b, aiFor i-th of product term of combinational circuit a, ai=x 'i1x′i2…x′ik…
x′in, k is the integer more than or equal to 1 and less than or equal to n, x 'ikFor product term aiThe text variable of kth position indicates that corresponding input becomes
Measure xkIn product term aiThe appearance form of kth position, x 'ik∈ 0,1 ,-, as x 'ikWhen=0, xkWith its contravariantForm occur
In product term aiKth position, as x 'ikWhen=1, xkWith its former variable xkForm appear in product term aiKth position, as x 'ik=-when,
Indicate xkValue perseverance be 1, xkIt is not present in product term aiIn kth position；bjFor j-th of product term of combinational circuit b, bj=y 'j1y′j2…y′jh…y′jn, h is the integer more than or equal to 1 and less than or equal to n, y 'jhFor product term bjH text variables, table
Show corresponding input variable yhIn product term bjH appearance forms, y 'jh∈ 0,1 ,-, as y 'jhWhen=0, yhWith its contravariant
AmountForm appear in product term bjH, as y 'jhWhen=1, yhWith its former variable yhForm appear in product term bjH
Position, as y 'jh=-when, indicate yhValue perseverance be 1, yhIt is not present in product term bjH；
(2) judge whether combinational circuit a includes combinational circuit b, detailed process are as follows:
A. variable f is set, initializing variable f enables variable f=1；
B. variable u is set, initializing variable u enables u=1；Variable t is set, initializing variable t enables variable t=1；
C. by combinational circuit a to f-th of product term b of combinational circuit bfMinor function representation be af(x1,x2,…,xn),
By t-th of product term a of combinational circuit atTo f-th of product term b of combinational circuit bfComplementary minor be denoted as
D. it enablesForThe text variable of kth position indicates corresponding input variable xk?The
K appearance forms, x "tk∈ 0,1 ,-, NULL }, as x "tkWhen=0, xkWith its contravariantForm appear inKth position,
As x "tkWhen=1, xkWith its x of former variablekForm appear inKth position, as x "tk=-when, indicate xkValue perseverance be 1, xkDo not go out
NowKth position, as x "tkWhen=NULL, x is indicatedkValue perseverance be 0；
It is successively right according to following ruleU text variable x "tuCarry out assignment:
If x 'tu=y 'fu, then x " is enabledtu=-；
If x 'tu≠y′fu, and x 'tu=-, y 'fu=0, then enable x "tu=-；
If x 'tu≠y′fu, and x 'tu=-, y 'fu=1, then enable x "tu=-；
If x 'tu≠y′fu, and x 'tu=0, y 'fu=1, then enable x "tu=NULL；
If x 'tu≠y′fu, and x 'tu=1, y 'fu=0, then enable x "tu=NULL；
If x 'tu≠y′fu, and x 'tu=0, y 'fu=-, then enables x "tu=0；
If x 'tu≠y′fu, and x 'tu=1, y 'fu=-, then enables x "tu=1；
E. judge x "tuValue whether be NULL, if x "tuValue be NULL, then directly orderObtain combinational circuit
T-th of product term a of atTo f-th of product term b of combinational circuit bfComplementary minorExpression formula, subsequently into step F；It is no
Then, judge whether the current value of u is equal to n, if the current value of u is equal to n, showThe 1st~n-th text variable it is complete
Portion's assignment is completed, and the 1st~n-th text variable whole assignment is completedExpression formulaMake
For t-th of product term a of combinational circuit atTo f-th of product term b of combinational circuit bfComplementary minorExpression formula, then into
Enter step F, if the current value of u be not equal to n, using u current value add 1 after value go update u, then repeatedly step D and
Step E；
F. judgeThe 1st text variable~the n-th text variable value whether all for-, if so, showingValue
Perseverance is 1, then directly enables af(x1,x2,…,xk,…,xn)=1 obtains combinational circuit a to f-th of product term b of combinational circuit bf
Minor function af(x1,x2,…,xn) expression formula, subsequently into step G, if it is not, then judging whether the current value of t is equal to
P is enabled if be equal toCombinational circuit a is obtained to the f of combinational circuit b
A product term bfMinor function af(x1,x2,…,xn) expression formula, subsequently into step G, if be not equal to p, using t
Value after current value adds 1 goes to update t, and repeats step D~step F；
G. determine combinational circuit a to f-th of product term b of combinational circuit bfMinor function af(x1,x2,…,xn) table
It whether is tautology, detailed process up to formula are as follows:
G-1. minor function a is first determined whetherf(x1,x2,…,xn) the value of expression formula whether be 0, if minor function af
(x1,x2,…,xn) the value of expression formula be 0, then minor function af(x1,x2,…,xn) expression formula be not tautology, combination electricity
It is not logically equivalent relationship that road a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；If minor function
af(x1,x2,…,xn) the value of expression formula be not 0, then G-2 is entered step, to minor function af(x1,x2,…,xn) expression formula
Value whether be 1 to be judged；
G-2. if minor function af(x1,x2,…,xn) the value of expression formula be 1, then minor function af(x1,x2,…,xn)
Expression formula be tautology, G-6 is entered step, if minor function af(x1,x2,…,xn) the value of expression formula be not 1, then into
Enter step G-3；
G-3. from complementary minorIn randomly select a unselected mistake be not equal to 0 complementary minor, be denoted asV be integer and 1≤v≤p, fromExpression formula in randomly select one not equal to-text variable, be denoted as x "vs,
S is the integer more than or equal to 1 and less than or equal to n, by x "vsCorresponding variable xsAs variable is split, according to shannon's expansion theorem
Calculate minor function af(x1,x2,…,xn) expression formula to xsFormer variable xsComplementary minor, obtained complementary minor is denoted as
Minor function a is calculated according to shannon's expansion theoremf(x1,x2,…,xn) expression formula to xsContravariantComplementary minor, will
To complementary minor be denoted asSubsequently into step G-4, judgementIt whether is tautology；
G-4. judgeIt whether is tautology, specifically: ifValue be 0, thenIt is not tautology, combinational circuit a
Not comprising combinational circuit b, combinational circuit a and combinational circuit b are not logically equivalent relationships, and detection is completed；IfValue be not
0, then continue to judgeValue whether be 1, ifValue be not 1, then repeatedly step G-3 and step G-4；IfValue
It is 1, thenIt is tautology, enters step G-5；
G-5. using judgementIt whether is the method for tautology to judgeIt whether is tautology, ifIt is not tautology,
It is not logically equivalent relationship that then combinational circuit a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；If
It is tautology, then shows af(x1,x2,…,xn) it is tautology, enter step G-6；
Whether the current value for G-6. judging f is q, the value if current value of f is not q, after adding 1 using the current value of f
It goes to update f, then repeatedly step B~step G of step (2), if the current value of f is q, shows that combinational circuit a includes group
Circuit b is closed, (3) are entered step；
(3) determine whether combinational circuit b wraps using whether judgement combinational circuit a includes the identical method of combinational circuit b
A containing combinational circuit shows combinational circuit a and combinational circuit b is that logically equivalent closes if combinational circuit b includes combinational circuit a
System has been detected if it is not logically equivalent relationship that combinational circuit b, which does not include combinational circuit a, combinational circuit a and combinational circuit b,
At.
Compared with the prior art, the advantages of the present invention are as follows by extension complementary minor concept, Logic coverage equivalence is examined
Survey problem, which is divided into, resolves into circuit comprising detecting subproblem, seeks one of circuit expressions formula one by one to another circuit expressions
The complementary minor of each product term of formula, then judge on the basis of establishing the Shannon structure chart of each product term complementary minor its whether tautology
Formula finally differentiates whether cover equivalent relation between result determines two circuits according to tautology, and method of the invention is by seeking multiplying
Product item complementary minor decompose to logical function and depression of order is handled, to accelerate covering equivalence verifying speed, operability
It is higher with detection efficiency, and be not in memory explosion issues, experimental configuration shows that method of the invention is stablized effectively,
The test result of circuit obtained by three kinds of algorithms to EXPRESSO Integrated Simulation shows, with two kinds of inspections based on truth table and BDD
Method of determining and calculating is compared, and has apparent speed advantage.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
A kind of embodiment: combinational logic circuit equivalence detection method, comprising the following steps:
(1) two combinational circuits to be detected are denoted as a and b, wherein the logical expression of a are as follows:
The logical expression of b are as follows:
Wherein, n is the variable number of combinational circuit a and b, and ∑ is summation operation symbol, and p is the product term of combinational circuit a
Quantity, q are the quantity of the product term of combinational circuit b, aiFor i-th of product term of combinational circuit a, ai=x 'i1x′i2…x′ik…
x′in, k is the integer more than or equal to 1 and less than or equal to n, x 'ikFor product term aiThe text variable of kth position indicates that corresponding input becomes
Measure xkIn product term aiThe appearance form of kth position, x 'ik∈ 0,1 ,-, as x 'ikWhen=0, xkWith its contravariantForm go out
Present product term aiKth position, as x 'ikWhen=1, xkWith its former variable xkForm appear in product term aiKth position, as x 'ik=-
When, indicate xkValue perseverance be 1, xkIt is not present in product term aiIn kth position；bjFor j-th of product term of combinational circuit b, bj=
y′j1y′j2…y′jh…y′jn, h is the integer more than or equal to 1 and less than or equal to n, y 'jhFor product term bjH text variables,
Indicate corresponding input variable yhIn product term bjH appearance forms, y 'jh∈ 0,1 ,-, as y 'jhWhen=0, yhIt is anti-with it
VariableForm appear in product term bjH, as y 'jhWhen=1, yhWith its former variable yhForm appear in product term bj
H, as y 'jh=-when, indicate yhValue perseverance be 1, yhIt is not present in product term bjH；
(2) judge whether combinational circuit a includes combinational circuit b, detailed process are as follows:
A. variable f is set, initializing variable f enables variable f=1；
B. variable u is set, initializing variable u enables u=1；Variable t is set, initializing variable t enables variable t=1；
C. by combinational circuit a to f-th of product term b of combinational circuit bfMinor function representation be af(x1,x2,…,xn),
By t-th of product term a of combinational circuit atTo f-th of product term b of combinational circuit bfComplementary minor be denoted as
D. it enablesx″tkForThe text variable of kth position indicates corresponding input variable xk?The
K appearance forms, x "tk∈ 0,1 ,-, NULL }, as x "tkWhen=0, xkWith its contravariantForm appear inKth position,
As x "tkWhen=1, xkWith its x of former variablekForm appear inKth position, as x "tk=-when, indicate xkValue perseverance be 1, xkNo
It appears inKth position, as x "tkWhen=NULL, x is indicatedkValue perseverance be 0；
It is successively right according to following ruleU text variable x "tuCarry out assignment:
If x 'tu=y 'fu, then x " is enabledtu=-；
If x 'tu≠y′fu, and x 'tu=-, y 'fu=0, then enable x "tu=-；
If x 'tu≠y′fu, and x 'tu=-, y 'fu=1, then enable x "tu=-；
If x 'tu≠y′fu, and x 'tu=0, y 'fu=1, then enable x "tu=NULL；
If x 'tu≠y′fu, and x 'tu=1, y 'fu=0, then enable x "tu=NULL；
If x 'tu≠y′fu, and x 'tu=0, y 'fu=-, then enables x "tu=0；
If x 'tu≠y′fu, and x 'tu=1, y 'fu=-, then enables x "tu=1；
E. judge x "tuValue whether be NULL, if x "tuValue be NULL, then directly orderObtain combinational circuit
T-th of product term a of atTo f-th of product term b of combinational circuit bfComplementary minorExpression formula, subsequently into step F；It is no
Then, judge whether the current value of u is equal to n, if the current value of u is equal to n, showThe 1st~n-th text variable it is complete
Portion's assignment is completed, and the 1st~n-th text variable whole assignment is completedExpression formulaMake
For t-th of product term a of combinational circuit atTo f-th of product term b of combinational circuit bfComplementary minorExpression formula, then into
Enter step F, if the current value of u be not equal to n, using u current value add 1 after value go update u, then repeatedly step D and
Step E；
F. judgeThe 1st text variable~the n-th text variable value whether all for-, if so, showingValue
Perseverance is 1, then directly enables af(x1,x2,…,xk,…,xn)=1 obtains combinational circuit a to f-th of product term b of combinational circuit bf
Minor function af(x1,x2,…,xn) expression formula, subsequently into step G, if it is not, then judging whether the current value of t is equal to
P is enabled if be equal toCombinational circuit a is obtained to the f of combinational circuit b
A product term bfMinor function af(x1,x2,…,xn) expression formula, subsequently into step G, if be not equal to p, using t
Value after current value adds 1 goes to update t, and repeats step D~step F；
G. determine combinational circuit a to f-th of product term b of combinational circuit bfMinor function af(x1,x2,…,xn) table
It whether is tautology, detailed process up to formula are as follows:
G-1. minor function a is first determined whetherf(x1,x2,…,xn) the value of expression formula whether be 0, if minor function af
(x1,x2,…,xn) the value of expression formula be 0, then minor function af(x1,x2,…,xn) expression formula be not tautology, combination electricity
It is not logically equivalent relationship that road a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；If minor function
af(x1,x2,…,xn) the value of expression formula be not 0, then G-2 is entered step, to minor function af(x1,x2,…,xn) expression formula
Value whether be 1 to be judged；
G-2. if minor function af(x1,x2,…,xn) the value of expression formula be 1, then minor function af(x1,x2,…,xn)
Expression formula be tautology, G-6 is entered step, if minor function af(x1,x2,…,xn) the value of expression formula be not 1, then into
Enter step G-3；
G-3. from complementary minorIn randomly select a unselected mistake be not equal to 0 complementary minor, be denoted asV be integer and 1≤v≤p, fromExpression formula in randomly select one not equal to-text variable, be denoted as x "vs,
S is the integer more than or equal to 1 and less than or equal to n, by x "vsCorresponding variable xsAs variable is split, according to shannon's expansion theorem
Calculate minor function af(x1,x2,…,xn) expression formula to xsFormer variable xsComplementary minor, obtained complementary minor is denoted as
Minor function a is calculated according to shannon's expansion theoremf(x1,x2,…,xn) expression formula to xsContravariantComplementary minor, will
To complementary minor be denoted asSubsequently into step G-4, judgementIt whether is tautology；
G-4. judgeIt whether is tautology, specifically: ifValue be 0, thenIt is not tautology, combinational circuit a
Not comprising combinational circuit b, combinational circuit a and combinational circuit b are not logically equivalent relationships, and detection is completed；IfValue be not
0, then continue to judgeValue whether be 1, ifValue be not 1, then repeatedly step G-3 and step G-4；IfValue
It is 1, thenIt is tautology, enters step G-5；
G-5. using judgementIt whether is the method for tautology to judgeIt whether is tautology, ifIt is not tautology,
It is not logically equivalent relationship that then combinational circuit a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；If
It is tautology, then shows af(x1,x2,…,xn) it is tautology, enter step G-6；
Whether the current value for G-6. judging f is q, the value if current value of f is not q, after adding 1 using the current value of f
It goes to update f, then repeatedly step B~step G of step (2), if the current value of f is q, shows that combinational circuit a includes group
Circuit b is closed, (3) are entered step；
(3) determine whether combinational circuit b wraps using whether judgement combinational circuit a includes the identical method of combinational circuit b
A containing combinational circuit shows combinational circuit a and combinational circuit b is that logically equivalent closes if combinational circuit b includes combinational circuit a
System has been detected if it is not logically equivalent relationship that combinational circuit b, which does not include combinational circuit a, combinational circuit a and combinational circuit b,
At.
Method of the invention is at IV 1.60GHz of Pentium, the Windows XP environment of 1.00GB memory, using C language
Speech programming is realized, and is compiled and is debugged by VC6.0.Test includes validity test and efficiency test: 1) using input
Multiple single output circuit testing algorithm validity of the variable number no more than 4, optimize primary circuit expression formula using Karnaugh map, will optimize
The expression formula of front and back is write as test circuit pair of the BLIF file as algorithm of standard；Test result shows: each pair of test electricity
Road is that covering is equivalent；2) test circuit is modified by one or more of mode before test: changes several products at random
Several bit variable values, deletion or addition several row ONSET or outliers, test result be consistent with expected results
It closes；3) using the MCNC of the method for the invention of ESPRESSO Integrated Simulation and existing two kinds of optimization algorithms optimization different scales
Benchmark circuit forms test circuit pair by primary circuit with circuit obtained by Different Optimization algorithm respectively, continues the test present invention
Validity, while observing the efficiency of algorithm.Table 1 show the brief informations of 12 test circuits, including circuit name, defeated
Enter/product term the quantity of the number of output, ifq circuit product term quantity and three kinds of algorithm optimization result circuits；Esp1 is represented most
Optimization algorithm optimum results circuit, Esp2 represent ESPRESSO algorithm optimization result circuit, and Esp3 represents quick ESPRESSO and calculates
Method optimum results circuit.
The product item number of 1 ESPRESSO of table optimization front and back, 12 MCNC Benchmark circuits
For the validity and efficiency convenient for method and existing method more of the invention；Using the above test circuit to point
It Ce Shi not the equivalence detection algorithm (abbreviation truth table method) based on the truth table, (abbreviation of the equivalence detection algorithm based on BDD
BDD method) and method of the invention.Wherein, truth table method is programmed under identical environment using C language, is based on truth table realizing
Tautology decision algorithm on the basis of further realize；BDD method uses document (Somenzi F.CUDD:CU decision
Diagram package release 3.0.0 [OL] [2015-12-31] .http: //vlsi.colorado.edu/~
Fabio/CUDD/cudd.pdf the combinational circuit equivalence checking algorithm in CUDD disclosed in), the algorithm will test circuit to point
The OBDD under optimal input variable sequence is not constructed, and then the equivalent node of each output is compared one by one.When all output
When node all confirms equivalent, discriminating test circuit is to equivalent.Three kinds of equivalence detection algorithm results show: testing circuit above
Equivalent relation is covered to all meeting.The consistency conclusion also shows the validity of method of the invention simultaneously.Table 2 is shown accordingly
The runing time and comparable situation of detection process, be the average value of 5 runing times wherein；tTr、tBDDAnd tOurIt is respectively true
It is worth table method, BDD method and the method for the present invention test corresponding circuits to the time used；S1The time of truth table method is compared for the present invention
Save percentage,S2Percentage is saved compared to the time of BDD method for the present invention.
The time required to carrying out equivalence test with 3 kinds of algorithms before and after 2 12 MCNC Benchmark circuit optimizations of table
As can be seen from Table 2: 1) it is obviously, significant the time required to truth table method to increase as input variable quantity increases, this
Inventive method and BDD method runing time and input variable quantity do not have apparent relationship；2) product term quantity is to the method for the present invention
It is influenced obviously with truth table method speed, it is relatively small on the influence of BDD method, such as circuit cordic and duke2 input variable number is only
Difference 1, the former product item number is 10 times of the latter or more, and truth table method is the latter to the runing time of the former different tests pair
10 times or more, the method for the present invention is to 50 times or more that the testing time of cordic circuit pair is then duke2, and BDD method pair
The testing time of cordic circuit is reduced to nearly 1/10th of duke2 instead, in addition seq, cordic and alu4 circuit multiplies
Product item number is relatively most, and the method for the present invention is more compared to other circuits to the testing time of this 3 circuits, also illustrates product item number
It is the significant effects factor of this paper efficiency of algorithm；3) circuit output quantity influences maximum to the BDD method testing time, to truth table
Method and the method for the present invention influence are relatively small, this conclusion is easy by comparing cps, the testing time of the circuits such as seq, duke2
It obtains；4) for the overall operation efficiency of three kinds of method, truth table method efficiency is minimum, but works as input variable and product item number
Still there is relatively high operational efficiency, when circuit has few output quantity, input quantity and more product term, such as when measuring less
Seq and cordic circuit, BDD method is fastest, product term quantity relatively small number of circuit more for the amount of outputting and inputting,
It is suitble to carry out test using the method for the present invention for involved test circuit, the method for the present invention average efficiency highest, compared to true
The time of value table method and BDD method, averagely saving rate was more than 60%.
Claims (1)
1. a kind of combinational logic circuit equivalence detection method, it is characterised in that the following steps are included:
(1) two combinational circuits to be detected are denoted as a and b, wherein the logical expression of combinational circuit a are as follows:
The logical expression of b are as follows:
Wherein, n is the variable number of combinational circuit a and combinational circuit b, and ∑ is summation operation symbol, and p is the product of combinational circuit a
The quantity of item, q are the quantity of the product term of combinational circuit b, aiFor i-th of product term of combinational circuit a, ai=x 'i1x′i2…
x′ik…x′in, k is the integer more than or equal to 1 and less than or equal to n, x 'ikFor product term aiThe text variable of kth position indicates to correspond to
Input variable xkIn product term aiThe appearance form of kth position, x 'ik∈ 0,1 ,-, as x 'ikWhen=0, xkWith its contravariant's
Form appears in product term aiKth position, as x 'ikWhen=1, xkWith its former variable xkForm appear in product term aiKth position, when
x′ik=-when, indicate xkValue perseverance be 1, xkIt is not present in product term aiIn kth position；bjFor j-th of product term of combinational circuit b,
bj=y'j1y'j2…y'jh…y'jn, h is the integer more than or equal to 1 and less than or equal to n, y'jhFor product term bjH texts
Variable indicates corresponding input variable yhIn product term bjH appearance forms, y'jh∈ 0,1 ,-, work as y'jhWhen=0, yhWith
Its contravariantForm appear in product term bjH, work as y'jhWhen=1, yhWith its former variable yhForm appear in product
Item bjH, work as y'jh=-when, indicate yhValue perseverance be 1, yhIt is not present in product term bjH；
(2) judge whether combinational circuit a includes combinational circuit b, detailed process are as follows:
A. variable f is set, initializing variable f enables variable f=1；
B. variable u is set, initializing variable u enables u=1；Variable t is set, initializing variable t enables variable t=1；
C. by combinational circuit a to f-th of product term b of combinational circuit bfMinor function representation be af(x1,x2,…,xn), by group
Close t-th of product term a of circuit atTo f-th of product term b of combinational circuit bfComplementary minor be denoted as
D. it enablesx″tkForThe text variable of kth position indicates corresponding input variable xk?Kth position
Appearance form, x "tk∈ 0,1 ,-, NULL }, as x "tkWhen=0, xkWith its contravariantForm appear inKth position, when
x″tkWhen=1, xkWith its x of former variablekForm appear inKth position, as x "tk=-when, indicate xkValue perseverance be 1, xkDo not go out
NowKth position, as x "tkWhen=NULL, x is indicatedkValue perseverance be 0；
It is successively right according to following ruleU text variable x "tuCarry out assignment:
If x 'tu=y'fu, then x " is enabledtu=-；
If x 'tu≠y'fu, and x 'tu=-, y'fu=0, then enable x "tu=-；
If x 'tu≠y'fu, and x 'tu=-, y'fu=1, then enable x "tu=-；
If x 'tu≠y'fu, and x 'tu=0, y'fu=1, then enable x "tu=NULL；
If x 'tu≠y'fu, and x 'tu=1, y'fu=0, then enable x "tu=NULL；
If x 'tu≠y'fu, and x 'tu=0, y'fu=-, then enables x "tu=0；
If x 'tu≠y'fu, and x 'tu=1, y'fu=-, then enables x "tu=1；
E. judge x "tuValue whether be NULL, if x "tuValue be NULL, then directly orderObtain combinational circuit a's
T-th of product term atTo f-th of product term b of combinational circuit bfComplementary minorExpression formula, subsequently into step F；Otherwise,
Judge whether the current value of u is equal to n, if the current value of u is equal to n, showsThe 1st~n-th text variable it is whole
Assignment is completed, and the 1st~n-th text variable whole assignment is completedExpression formulaAs
T-th of product term a of combinational circuit atTo f-th of product term b of combinational circuit bfComplementary minorExpression formula, subsequently into
Step F, if the current value of u is not equal to n, the value after adding 1 using the current value of u goes to update u, then repeatedly step D and step
Rapid E；
F. judgeThe 1st text variable~the n-th text variable value whether all for-, if so, showingValue perseverance be
1, then directly enable af(x1,x2,…,xk,…,xn)=1 obtains combinational circuit a to f-th of product term b of combinational circuit bfIt is remaining
Subfunction af(x1,x2,…,xn) expression formula, subsequently into step G, if it is not, then judging whether the current value of t is equal to p, such as
Fruit is equal to, then enablesCombinational circuit a is obtained to multiply f-th of combinational circuit b
Product item bfMinor function af(x1,x2,…,xn) expression formula, it is current using t if being not equal to p subsequently into step G
Value after value plus 1 goes to update t, and repeats step D~step F；
G. determine combinational circuit a to f-th of product term b of combinational circuit bfMinor function af(x1,x2,…,xn) expression formula
It whether is tautology, detailed process are as follows:
G-1. minor function a is first determined whetherf(x1,x2,…,xn) the value of expression formula whether be 0, if minor function af(x1,
x2,…,xn) the value of expression formula be 0, then minor function af(x1,x2,…,xn) expression formula be not tautology, combinational circuit a
Not comprising combinational circuit b, combinational circuit a and combinational circuit b are not logically equivalent relationships, and detection is completed；If minor function af
(x1,x2,…,xn) the value of expression formula be not 0, then G-2 is entered step, to minor function af(x1,x2,…,xn) expression formula
Value whether be 1 to be judged；
G-2. if minor function af(x1,x2,…,xn) the value of expression formula be 1, then minor function af(x1,x2,…,xn) table
It is tautology up to formula, enters step G-6, if minor function af(x1,x2,…,xn) the value of expression formula be not 1, then enter step
Rapid G-3；
G-3. from complementary minorIn randomly select a unselected mistake be not equal to 0 complementary minor, be denoted asv
For integer and 1≤v≤p, fromExpression formula in randomly select one not equal to-text variable, be denoted as x "vs, s is
Integer more than or equal to 1 and less than or equal to n, by x "vsCorresponding variable xsAs variable is split, calculated according to shannon's expansion theorem
Minor function af(x1,x2,…,xn) expression formula to xsFormer variable xsComplementary minor, obtained complementary minor is denoted asAccording to
Shannon's expansion theorem calculates minor function af(x1,x2,…,xn) expression formula to xsContravariantComplementary minor, by what is obtained
Complementary minor is denoted asSubsequently into step G-4, judgementIt whether is tautology；
G-4. judgeIt whether is tautology, specifically: ifValue be 0, thenIt is not tautology, combinational circuit a is not wrapped
B containing combinational circuit, combinational circuit a and combinational circuit b are not logically equivalent relationships, and detection is completed；IfValue be not 0, then
Continue to judgeValue whether be 1, ifValue be not 1, then repeatedly step G-3 and step G-4；IfValue be 1,
ThenIt is tautology, enters step G-5；
G-5. using judgementIt whether is the method for tautology to judgeIt whether is tautology, ifIt is not tautology, then group
Closing circuit a not including combinational circuit b, combinational circuit a and combinational circuit b is not logically equivalent relationship, and detection is completed；IfIt is weight
Speech formula, then show af(x1,x2,…,xn) it is tautology, enter step G-6；
Whether the current value for G-6. judging f is q, if the current value of f is not q, the value after adding 1 using the current value of f is gone more
New f, then repeatedly step B~step G of step (2) shows that combinational circuit a includes combination electricity if the current value of f is q
Road b enters step (3)；
(3) determine whether combinational circuit b includes group using whether judgement combinational circuit a includes the identical method of combinational circuit b
Circuit a is closed, if combinational circuit b includes combinational circuit a, shows combinational circuit a and combinational circuit b is logically equivalent relationship,
If it is not logically equivalent relationship that combinational circuit b, which does not include combinational circuit a, combinational circuit a and combinational circuit b, detection is completed.
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