CN107798203A - A kind of combinational logic circuit equivalence detection method - Google Patents
A kind of combinational logic circuit equivalence detection method Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Abstract
The invention discloses a kind of combinational logic circuit equivalence detection method, by extending complementary minor concept, Logic coverage equivalence test problems are divided into resolve into circuit include detection subproblem, complementary minor of one of circuit expressions formula to another each product term of circuit expressions formula is asked for one by one, then judge on the basis of the Shannon structure chart of each product term complementary minor is established its whether tautology, finally according to tautology differentiate result determine whether cover equivalent relation between two circuits；Advantage is logical function to be decomposed by asking for product term complementary minor and depression of order is handled, so as to accelerate covering equivalence verifying speed, operability and detection efficiency are higher, and be not in internal memory explosion issues, experimental configuration shows, method of the invention is stablized effective, and the test result of circuit obtained by three kinds of algorithms of EXPRESSO Integrated Simulations is shown, compared with two kinds of detection algorithms based on truth table and BDD, there is obvious speed advantage.
Description
Technical field
The present invention relates to a kind of detection method, more particularly, to a kind of combinational logic circuit equivalence detection method.
Background technology
Logic equivalence detect for the purpose of 2 different combinational circuit Non-inferiority tests of logical layer expression formula, according to
The logical expression of 2 fixed combinational circuits, detects whether they realize identical logic function.Combinational logic circuit at present
Equivalence detection method mainly has algebraic approach, truth table criterion and functional method.
Algebraic approach is a kind of direct-vision method for examining combinational logic circuit equivalence, and this method is basic using logic algebra
The logical expression of 2 combinational circuits of formula manipulation, if identical result can be obtained, the logical expression of 2 combinational circuits
Formula is logically equivalent.But because the fundamental formular quantity of logic algebra is more, in this method, fundamental formular selection, institute
The links such as the selection of application order and selected each fundamental formular process object of several fundamental formulars are selected to exist more
Kind alternative, selection and the circuit structure of concrete scheme have direct relation, still can use without unified feasible guideline.
Therefore, detection tool is carried out to combinational logic circuit equivalence using algebraic approach to bear the character of much blindness, this method operability
Difference, and amount of calculation and calculating time, also with circuit scale sharp increase, detection efficiency is very low, seldom individually uses in practice.
Truth table criterion judges the logical expression of 2 combinational circuits with the presence or absence of logic etc. by using truth table
Effect relation.In this method, the combination that is possible to of the input variable value of 2 combinational circuits is substituted into 2 combination electricity one by one
The logical expression on road, then according to result whether all it is identical i.e. it could be assumed that.Although this method relative to algebraic approach, can
Operability is higher, however, it will be apparent that when circuit scale increases, the input variable value of combinational circuit will also sharply increase, should
The time overhead of method will sharply increase, and detection efficiency is still relatively low.
Functional method is currently used combinational logic circuit equivalence detection method, and this method is by 2 combinational circuits
It is expressed as a kind of canonical form, such as binary decision figure (BDD), they etc. if the canonical form isomorphism of 2 combinational circuits
Effect.The problem of operability is also not present in this method, although being increased relative to truth table criterion detection efficiency,
Can not still meet the needs of current ultra-large circuit, and to face internal memory under some input variable orders quick-fried for this method
The problem of fried.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of operability and detection efficiency is higher, and are not in
The combinational logic circuit equivalence detection method of internal memory explosion issues.
Technical scheme is used by the present invention solves above-mentioned technical problem：A kind of combinational logic circuit equivalence detection side
Method, comprise the following steps：
(1) two combinational circuits to be detected are designated as a and b, wherein, a logical expression is：
B logical expression is：
Wherein, n is combinational circuit a and b variable number, and ∑ is summation operation symbol, and p is combinational circuit a product term
Quantity, q be combinational circuit b product term quantity, aiFor combinational circuit a i-th of product term, ai=xi'1xi'2…xi'k…
xi'n, k be more than or equal to 1 and less than or equal to n integer, xi'kFor product term aiThe word variable of kth position, represent corresponding input
Variable xkIn product term aiThe appearance form of kth position, xi'k∈ 0,1 ,-, work as xi'kWhen=0, xkWith its contravariantForm
Appear in product term aiKth position, works as xi'kWhen=1, xkWith its former variable xkForm appear in product term aiKth position, works as xi'k
=-when, represent xkValue it is permanent be 1, xkIt is not present in product term aiIn kth position；bjFor combinational circuit b j-th of product term, bj
=y'j1y'j2…y'jh…y'jn, h be more than or equal to 1 and less than or equal to n integer, y'jhFor product term bjThe word of h positions becomes
Amount, represent corresponding input variable yhIn product term bjThe appearance form of h positions, y'jh∈ 0,1 ,-, work as y'jhWhen=0, yhWith it
Contravariant yhForm appear in product term bjH positions, work as y'jhWhen=1, yhWith its former variable yhForm appear in product term
bjH positions, work as y'jh=-when, represent yhValue it is permanent be 1, yhIt is not present in product term bjH positions；
(2) judge whether combinational circuit a includes combinational circuit b, detailed process is：
A. variable f is set, initializing variable f, makes variable f=1；
B. variable u is set, initializing variable u, makes u=1；Variable t is set, initializing variable t, makes variable t=1；
C. f-th of product term b by combinational circuit a to combinational circuit bfMinor function representation be af(x1,x2,…,xn),
By combinational circuit a t-th of product term atTo combinational circuit b f-th of product term bfComplementary minor be designated as
D. makext”kForThe word variable of kth position, represent corresponding input variable xk The
The appearance form of k positions, xt”k∈ 0,1 ,-, NULL }, work as xt”kWhen=0, xkWith its contravariantForm appear inKth
Position, works as xt”kWhen=1, xkWith its x of former variablekForm appear inKth position, works as xt”k=-when, represent xkValue it is permanent be 1,
xkIt is not present inKth position, works as xt”kDuring=NULL, x is representedkValue it is permanent be 0；
It is right successively according to following ruleU positions word variable xt”uCarry out assignment：
If xt'u=y'fu, then x is madet”u=-；
If xt'u≠y'fu, and xt'u=-, y'fu=0, then make xt”u=-；
If xt'u≠y'fu, and xt'u=-, y'fu=1, then make xt”u=-；
If xt'u≠y'fu, and xt'u=0, y'fu=1, then make xt”u=NULL；
If xt'u≠y'fu, and xt'u=1, y'fu=0, then make xt”u=NULL；
If xt'u≠y'fu, and xt'u=0, y'fu=-, then makes xt”u=0；
If xt'u≠y'fu, and xt'u=1, y'fu=-, then makes xt”u=1；
E. x is judgedt”uValue whether be NULL, if xt”uValue be NULL, then directly makeObtain combination electricity
Road a t-th of product term atTo combinational circuit b f-th of product term bfComplementary minorExpression formula, subsequently into step
F；Otherwise, judge whether u currency is equal to n, if u currency is equal to n, showThe 1st~n-th word
Variable whole assignment is completed, and the 1st~n-th word variable whole assignment is completedExpression formulaT-th of product term a as combinational circuit atTo combinational circuit b f-th of product term bfMinor
FormulaExpression formula, subsequently into step F, if u currency is not equal to n, add the value after 1 to go more using u currency
New u, then repeat step D and step E；
F. judgeThe 1st word variable~the n-th word variable value whether all for-, if it is, showingValue
Perseverance is 1, then directly makes af(x1,x2,…,xk,…,xn)=1, obtain f-th product term bs of the combinational circuit a to combinational circuit bf
Minor function af(x1,x2,…,xn) expression formula, subsequently into step G, if it is not, then judge t currency whether etc.
In p, if equal to, then makeCombinational circuit a is obtained to the of combinational circuit b
F product term bfMinor function af(x1,x2,…,xn) expression formula, subsequently into step G, if being not equal to p, using t
Currency add the value after 1 to go to update t, and repeat step D~step F；
G. f-th of product term b of the combinational circuit a to combinational circuit b is judgedfMinor function af(x1,x2,…,xn) table
Whether it is tautology up to formula, detailed process is：
G-1. minor function a is first determined whetherf(x1,x2,…,xn) the value of expression formula whether be 0, if minor function af
(x1,x2,…,xn) the value of expression formula be 0, then minor function af(x1,x2,…,xn) expression formula be not tautology, combination
It is not logically equivalent relation that circuit a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；If minor
Function af(x1,x2,…,xn) expression formula value not be 0, then into step G-2, to minor function af(x1,x2,…,xn)
Whether the value of expression formula is 1 to be judged；
G-2. if minor function af(x1,x2,…,xn) the value of expression formula be 1, then minor function af(x1,x2,…,xn)
Expression formula be tautology, into step G-6, if minor function af(x1,x2,…,xn) the value of expression formula be not 1, then
Into step G-3；
G-3. from complementary minorIn randomly select the complementary minor for being not equal to 0 of unselected mistake, be designated asV is integer and 1≤v≤p, fromExpression formula in randomly select one not equal to-word variable, be designated as x
'v's, s is the integer more than or equal to 1 and less than or equal to n, by x'v'sCorresponding variable xsAs variable is split, according to Shannon exhibition
Open theorem and calculate minor function af(x1,x2,…,xn) expression formula to xsFormer variable xsComplementary minor, the complementary minor that will be obtained
It is designated asMinor function a is calculated according to shannon's expansion theoremf(x1,x2,…,xn) expression formula to xsContravariantMinor
Formula, obtained complementary minor is designated asSubsequently into step G-4, judgeWhether it is tautology；
G-4. judgeWhether it is tautology, is specially：IfValue be 0, thenIt is not tautology, combinational circuit a
Not comprising combinational circuit b, combinational circuit a and combinational circuit b are not logically equivalent relations, and detection is completed；IfValue be not
0, then continue to judgeValue whether be 1, ifValue be not 1, then repeat step G-3 and step G-4；IfValue
It is 1, thenIt is tautology, into step G-5；
G-5. using judgementWhether it is that the method for tautology judgesWhether it is tautology, ifIt is not tautology,
It is not logically equivalent relation that then combinational circuit a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；IfIt is tautology, then shows af(x1,x2,…,xn) it is tautology, into step G-6；
Whether the currency for G-6. judging f is q, if f currency is not q, the value after 1 is added using f currency
Renewal f, then repeat step (2) step B~step G is removed, if f currency is q, shows that combinational circuit a includes group
Circuit b is closed, into step (3)；
(3) whether combinational circuit b identicals method is included to judge whether combinational circuit b wraps using judgement combinational circuit a
A containing combinational circuit, if combinational circuit b includes combinational circuit a, show that combinational circuit a and combinational circuit b are logically equivalents
Relation, if it is not logically equivalent relation that combinational circuit b, which does not include combinational circuit a, combinational circuit a and combinational circuit b, inspection
Survey and complete.
Compared with prior art, the advantage of the invention is that by extending complementary minor concept, Logic coverage equivalence is examined
Survey problem, which is divided into, resolves into circuit comprising subproblem is detected, and asks for one of circuit expressions formula one by one to another circuit table
Up to the complementary minor of each product term of formula, then judge whether it weighs on the basis of the Shannon structure chart of each product term complementary minor is established
Speech formula, finally differentiate that result determines whether cover equivalent relation between two circuits according to tautology, method of the invention is by asking
Take product term complementary minor logical function is decomposed and depression of order processing, so as to accelerate covering equivalence verifying speed, can grasp
The property made and detection efficiency are higher, and are not in internal memory explosion issues, and experimental configuration shows, method of the invention stably has
Effect, the test result of circuit obtained by three kinds of algorithms of EXPRESSO Integrated Simulations is shown, and based on truth table and BDD
Two kinds of detection algorithms are compared, and have obvious speed advantage.
Embodiment
The present invention is described in further detail with reference to embodiments.
Embodiment：A kind of combinational logic circuit equivalence detection method, comprises the following steps：
(1) two combinational circuits to be detected are designated as a and b, wherein, a logical expression is：
B logical expression is：
Wherein, n is combinational circuit a and b variable number, and ∑ is summation operation symbol, and p is combinational circuit a product term
Quantity, q be combinational circuit b product term quantity, aiFor combinational circuit a i-th of product term, ai=xi'1xi'2…xi'k…
xi'n, k be more than or equal to 1 and less than or equal to n integer, xi'kFor product term aiThe word variable of kth position, represent corresponding input
Variable xkIn product term aiThe appearance form of kth position, xi'k∈ 0,1 ,-, work as xi'kWhen=0, xkWith its contravariantForm
Appear in product term aiKth position, works as xi'kWhen=1, xkWith its former variable xkForm appear in product term aiKth position, works as xi'k
=-when, represent xkValue it is permanent be 1, xkIt is not present in product term aiIn kth position；bjFor combinational circuit b j-th of product term, bj
=y'j1y'j2…y'jh…y'jn, h be more than or equal to 1 and less than or equal to n integer, y'jhFor product term bjThe word of h positions becomes
Amount, represent corresponding input variable yhIn product term bjThe appearance form of h positions, y'jh∈ 0,1 ,-, work as y'jhWhen=0, yhWith it
ContravariantForm appear in product term bjH positions, work as y'jhWhen=1, yhWith its former variable yhForm appear in product term
bjH positions, work as y'jh=-when, represent yhValue it is permanent be 1, yhIt is not present in product term bjH positions；
(2) judge whether combinational circuit a includes combinational circuit b, detailed process is：
A. variable f is set, initializing variable f, makes variable f=1；
B. variable u is set, initializing variable u, makes u=1；Variable t is set, initializing variable t, makes variable t=1；
C. f-th of product term b by combinational circuit a to combinational circuit bfMinor function representation be af(x1,x2,…,xn),
By combinational circuit a t-th of product term atTo combinational circuit b f-th of product term bfComplementary minor be designated as
D. makext”kForThe word variable of kth position, represent corresponding input variable xk The
The appearance form of k positions, xt”k∈ 0,1 ,-, NULL }, work as xt”kWhen=0, xkWith its contravariantForm appear inKth
Position, works as xt”kWhen=1, xkWith its x of former variablekForm appear inKth position, works as xt”k=-when, represent xkValue it is permanent be 1,
xkIt is not present inKth position, works as xt”kDuring=NULL, x is representedkValue it is permanent be 0；
It is right successively according to following ruleU positions word variable xt”uCarry out assignment：
If xt'u=y'fu, then x is madet”u=-；
If xt'u≠y'fu, and xt'u=-, y'fu=0, then make xt”u=-；
If xt'u≠y'fu, and xt'u=-, y'fu=1, then make xt”u=-；
If xt'u≠y'fu, and xt'u=0, y'fu=1, then make xt”u=NULL；
If xt'u≠y'fu, and xt'u=1, y'fu=0, then make xt”u=NULL；
If xt'u≠y'fu, and xt'u=0, y'fu=-, then makes xt”u=0；
If xt'u≠y'fu, and xt'u=1, y'fu=-, then makes xt”u=1；
E. x is judgedt”uValue whether be NULL, if xt”uValue be NULL, then directly makeObtain combination electricity
Road a t-th of product term atTo combinational circuit b f-th of product term bfComplementary minorExpression formula, subsequently into step F；
Otherwise, judge whether u currency is equal to n, if u currency is equal to n, showThe 1st~n-th word become
Measure whole assignment to complete, the 1st~n-th word variable whole assignment is completedExpression formulaT-th of product term a as combinational circuit atTo combinational circuit b f-th of product term bfMinor
FormulaExpression formula, subsequently into step F, if u currency is not equal to n, add the value after 1 to go more using u currency
New u, then repeat step D and step E；
F. judgeThe 1st word variable~the n-th word variable value whether all for-, if it is, showingValue
Perseverance is 1, then directly makes af(x1,x2,…,xk,…,xn)=1, obtain f-th product term bs of the combinational circuit a to combinational circuit bf
Minor function af(x1,x2,…,xn) expression formula, subsequently into step G, if it is not, then judge t currency whether etc.
In p, if equal to, then makeCombinational circuit a is obtained to the of combinational circuit b
F product term bfMinor function af(x1,x2,…,xn) expression formula, subsequently into step G, if being not equal to p, using t
Currency add the value after 1 to go to update t, and repeat step D~step F；
G. f-th of product term b of the combinational circuit a to combinational circuit b is judgedfMinor function af(x1,x2,…,xn) table
Whether it is tautology up to formula, detailed process is：
G-1. minor function a is first determined whetherf(x1,x2,…,xn) the value of expression formula whether be 0, if minor function af
(x1,x2,…,xn) the value of expression formula be 0, then minor function af(x1,x2,…,xn) expression formula be not tautology, combination
It is not logically equivalent relation that circuit a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；If minor
Function af(x1,x2,…,xn) expression formula value not be 0, then into step G-2, to minor function af(x1,x2,…,xn)
Whether the value of expression formula is 1 to be judged；
G-2. if minor function af(x1,x2,…,xn) the value of expression formula be 1, then minor function af(x1,x2,…,xn)
Expression formula be tautology, into step G-6, if minor function af(x1,x2,…,xn) the value of expression formula be not 1, then
Into step G-3；
G-3. from complementary minorIn randomly select the complementary minor for being not equal to 0 of unselected mistake, be designated asV is integer and 1≤v≤p, fromExpression formula in randomly select one not equal to-word variable, be designated as x
'v's, s is the integer more than or equal to 1 and less than or equal to n, by x'v'sCorresponding variable xsAs variable is split, according to Shannon exhibition
Open theorem and calculate minor function af(x1,x2,…,xn) expression formula to xsFormer variable xsComplementary minor, the complementary minor that will be obtained
It is designated asMinor function a is calculated according to shannon's expansion theoremf(x1,x2,…,xn) expression formula to xsContravariantMinor
Formula, obtained complementary minor is designated asSubsequently into step G-4, judgeWhether it is tautology；
G-4. judgeWhether it is tautology, is specially：IfValue be 0, thenIt is not tautology, combinational circuit
It is not logically equivalent relation that a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；IfValue be not
0, then continue to judgeValue whether be 1, ifValue be not 1, then repeat step G-3 and step G-4；IfValue
It is 1, thenIt is tautology, into step G-5；
G-5. using judgementWhether it is that the method for tautology judgesWhether it is tautology, ifIt is not tautology,
It is not logically equivalent relation that then combinational circuit a, which does not include combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；IfIt is tautology, then shows af(x1,x2,…,xn) it is tautology, into step G-6；
Whether the currency for G-6. judging f is q, if f currency is not q, the value after 1 is added using f currency
Renewal f, then repeat step (2) step B~step G is removed, if f currency is q, shows that combinational circuit a includes group
Circuit b is closed, into step (3)；
(3) whether combinational circuit b identicals method is included to judge whether combinational circuit b wraps using judgement combinational circuit a
A containing combinational circuit, if combinational circuit b includes combinational circuit a, show that combinational circuit a and combinational circuit b are logically equivalents
Relation, if it is not logically equivalent relation that combinational circuit b, which does not include combinational circuit a, combinational circuit a and combinational circuit b, inspection
Survey and complete.
The method of the present invention is under the Windows XP environment of Pentium IV 1.60GHz, 1.00GB internal memories, using C languages
Programming realization is sayed, and is compiled and debugs by VC6.0.Test includes validity test and efficiency test：1) using input
Variable number is not more than 4 multiple single output circuit testing algorithm validity, optimizes primary circuit expression formula using Karnaugh map, will be excellent
Change front and rear expression formula and write as test circuit pair of the BLIF files of standard as algorithm；Test result shows：Each pair is tested
Circuit is that covering is equivalent；2) test circuit is changed by one or more of mode before test:Change some multiply at random
Some bit variable values, deletion or some row ONSET items of addition or outlier, test result of product item are homogeneous with expected results
Meet；3) different scales are optimized using the method for the invention of ESPRESSO Integrated Simulations and existing two kinds of optimized algorithms
MCNC Benchmark circuits, test circuit pair is formed with Different Optimization algorithm gained circuit respectively by primary circuit, continues to test
Effectiveness of the invention, while observe the efficiency of algorithm.Table 1 show the brief information of 12 test circuits, including circuit name
The product term quantity of title, input/output quantity, ifq circuit product term quantity and three kinds of algorithm optimization result circuits；Esp1
Represent optimization algorithm optimum results circuit, Esp2 represents ESPRESSO algorithm optimization result circuits, Esp3 represents quick
ESPRESSO algorithm optimization result circuits.
Before and after table 1ESPRESSO optimizations
The product item number of 12 MCNC Benchmark circuits
For ease of method more of the invention and the validity and efficiency of existing method；Using above test circuit to dividing
The equivalence detection algorithm (abbreviation truth table method) based on truth table, the equivalence detection algorithm based on BDD are not tested (referred to as
BDD methods) and method of the invention.Wherein, truth table method is programmed under identical environment using C language, and truth table is based on realizing
Tautology decision algorithm on the basis of further realize；BDD methods use document (Somenzi F.CUDD:CU decision
diagram package release 3.0.0[OL].[2015-12-31]. http://vlsi.colorado.edu/~
Fabio/CUDD/cudd.pdf the combinational circuit equivalence checking algorithm in CUDD disclosed in), the algorithm is by test circuit pair
The OBDD under optimal input variable order is built respectively, and then the equivalent node of each output is compared one by one.When all defeated
When egress all confirms equivalent, discriminating test circuit is to equivalent.Three kinds of equivalence detection algorithm results show：Test above
Circuit is to all meeting to cover equivalent relation.The uniformity conclusion also shows the validity of the method for the present invention simultaneously.Shown in table 2
For the run time and comparable situation of corresponding detection process, be the average value of 5 run times wherein；tTr、tBDDAnd tOur
Respectively truth table method, BDD methods and the inventive method test corresponding circuits to the time used；S1True value is compared for the present invention
The time of table method saves percentage, S2For the present invention percentage is saved compared to the time of BDD methods.
2 12 MCNC Benchmark circuit optimizations of table are front and rear to carry out equivalence test required time with 3 kinds of algorithms
As can be seen from Table 2：1) obviously, as input variable quantity increases, significantly increase the time required to truth table method,
The inventive method and BDD methods run time do not have obvious relation with input variable quantity；2) product term quantity is to present invention side
Method and truth table method speed influence substantially, relatively small on the influence of BDD methods, such as circuit cordic and duke2 input variable number
1 is differed only by, the former product item number is more than 10 times of the latter, and truth table method is to the run time of the former different tests pair
More than 10 times of the latter, the inventive method is to more than 50 times that the testing time of cordic circuits pair is then duke2, and BDD methods
Nearly 1/10th of duke2 is reduced on the contrary to the testing time of cordic circuits, in addition seq, cordic and alu4 circuits
Product item number is relatively most, and the inventive method is more compared to other circuits to the testing time of this 3 circuits, also illustrates product
Item number is the significant effects factor of this paper efficiency of algorithm；3) circuit output quantity influences maximum on the BDD method testing times, right
Truth table method and the inventive method influence it is relatively small, during test of this conclusion by comparing the circuits such as cps, seq, duke2
Between be readily obtained；4) for the overall operation efficiency of three kinds of method, truth table method efficiency is minimum, but when input variable and
Still there is of a relatively high operational efficiency during product term negligible amounts, when circuit have few output quantity, input quantity and product term compared with
When more, such as seq and cordic circuits, BDD methods are fastest, and for input and output quantity is more, product term quantity is relatively fewer
Circuit, be adapted to carry out testing involved by for test circuit using the inventive method, the inventive method average efficiency is most
Height, compared to the time of truth table method and BDD methods averagely saving rate more than 60%.
Claims (1)
1. a kind of combinational logic circuit equivalence detection method, it is characterised in that comprise the following steps：
(1) two combinational circuits to be detected are designated as a and b, wherein, combinational circuit a logical expression is：
<mrow>
<mi>a</mi>
<mrow>
<mo>(</mo>
<msub>
<mi>x</mi>
<mn>1</mn>
</msub>
<mo>,</mo>
<msub>
<mi>x</mi>
<mn>2</mn>
</msub>
<mo>,</mo>
<mn>...</mn>
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<mi>x</mi>
<mi>k</mi>
</msub>
<mo>,</mo>
<mn>...</mn>
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<mi>x</mi>
<mi>n</mi>
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</mrow>
<mo>=</mo>
<munderover>
<mo>&Sigma;</mo>
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<mi>i</mi>
<mo>=</mo>
<mn>1</mn>
</mrow>
<mi>p</mi>
</munderover>
<msub>
<mi>a</mi>
<mi>i</mi>
</msub>
<mo>-</mo>
<mo>-</mo>
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<mo>(</mo>
<mn>1</mn>
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</mrow>
</mrow>
B logical expression is：
<mrow>
<mi>b</mi>
<mrow>
<mo>(</mo>
<msub>
<mi>y</mi>
<mn>1</mn>
</msub>
<mo>,</mo>
<msub>
<mi>y</mi>
<mn>2</mn>
</msub>
<mo>,</mo>
<mn>...</mn>
<mo>,</mo>
<msub>
<mi>y</mi>
<mi>h</mi>
</msub>
<mo>,</mo>
<mn>...</mn>
<mo>,</mo>
<msub>
<mi>y</mi>
<mi>n</mi>
</msub>
<mo>)</mo>
</mrow>
<mo>=</mo>
<munderover>
<mo>&Sigma;</mo>
<mrow>
<mi>j</mi>
<mo>=</mo>
<mn>1</mn>
</mrow>
<mi>q</mi>
</munderover>
<msub>
<mi>b</mi>
<mi>j</mi>
</msub>
<mo>-</mo>
<mo>-</mo>
<mo>-</mo>
<mrow>
<mo>(</mo>
<mn>2</mn>
<mo>)</mo>
</mrow>
</mrow>
Wherein, n is combinational circuit a and combinational circuit b variable number, and ∑ is summation operation symbol, and p is combinational circuit a product
Quantity, q be combinational circuit b product term quantity, aiFor combinational circuit a i-th of product term, ai=x 'i1x′i2…
x′ik…x′in, k be more than or equal to 1 and less than or equal to n integer, x 'ikFor product term aiThe word variable of kth position, represent corresponding
Input variable xkIn product term aiThe appearance form of kth position, x 'ik∈ 0,1 ,-, as x 'ikWhen=0, xkWith its contravariant's
Form appears in product term aiKth position, as x 'ikWhen=1, xkWith its former variable xkForm appear in product term aiKth position, when
x′ik=-when, represent xkValue it is permanent be 1, xkIt is not present in product term aiIn kth position；bjFor combinational circuit b j-th of product term,
bj=y'j1y'j2…y'jh…y'jn, h be more than or equal to 1 and less than or equal to n integer, y'jhFor product term bjThe word of h positions
Variable, represent corresponding input variable yhIn product term bjThe appearance form of h positions, y'jh∈ 0,1 ,-, work as y'jhWhen=0, yhWith
Its contravariantForm appear in product term bjH positions, work as y'jhWhen=1, yhWith its former variable yhForm appear in product
Item bjH positions, work as y'jh=-when, represent yhValue it is permanent be 1, yhIt is not present in product term bjH positions；
(2) judge whether combinational circuit a includes combinational circuit b, detailed process is：
A. variable f is set, initializing variable f, makes variable f=1；
B. variable u is set, initializing variable u, makes u=1；Variable t is set, initializing variable t, makes variable t=1；
C. f-th of product term b by combinational circuit a to combinational circuit bfMinor function representation be af(x1,x2,…,xn), by group
Close circuit a t-th of product term atTo combinational circuit b f-th of product term bfComplementary minor be designated as
D. makex″tkForThe word variable of kth position, represent corresponding input variable xk Kth position
Appearance form, x "tk∈ 0,1 ,-, NULL }, as x "tkWhen=0, xkWith its contravariantForm appear inKth position, when
x″tkWhen=1, xkWith its x of former variablekForm appear inKth position, as x "tk=-when, represent xkValue it is permanent be 1, xkDo not go out
NowKth position, as x "tkDuring=NULL, x is representedkValue it is permanent be 0；
It is right successively according to following ruleU positions word variable x "tuCarry out assignment：
If xt'u=y'fu, then x " is madetu=-；
If x 'tu≠y'fu, and x 'tu=-, y'fu=0, then make x "tu=-；
If x 'tu≠y'fu, and x 'tu=-, y'fu=1, then make x "tu=-；
If x 'tu≠y'fu, and x 'tu=0, y'fu=1, then make x "tu=NULL；
If x 'tu≠y'fu, and x 'tu=1, y'fu=0, then make x "tu=NULL；
If x 'tu≠y'fu, and x 'tu=0, y'fu=-, then makes x "tu=0；
If x 'tu≠y'fu, and x 'tu=1, y'fu=-, then makes x "tu=1；
E. x " is judgedtuValue whether be NULL, if x "tuValue be NULL, then directly makeObtain the of combinational circuit a
T product term atTo combinational circuit b f-th of product term bfComplementary minorExpression formula, subsequently into step F；Otherwise, sentence
Whether disconnected u currency is equal to n, if u currency is equal to n, showsThe 1st~n-th word variable all assign
Value is completed, and the 1st~n-th word variable whole assignment is completedExpression formulaAs group
Close circuit a t-th of product term atTo combinational circuit b f-th of product term bfComplementary minorExpression formula, subsequently into step
Rapid F, if u currency is not equal to n, the value after 1 is added to go to update u using u currency, then repeat step D and step
E；
F. judgeThe 1st word variable~the n-th word variable value whether all for-, if it is, showingValue perseverance be
1, then directly make af(x1,x2,…,xk,…,xn)=1, obtain f-th product term bs of the combinational circuit a to combinational circuit bfIt is remaining
Subfunction af(x1,x2,…,xn) expression formula, subsequently into step G, if it is not, then judging whether t currency is equal to p, such as
Fruit is equal to, then makesObtain f-th products of the combinational circuit a to combinational circuit b
Item bfMinor function af(x1,x2,…,xn) expression formula, subsequently into step G, if being not equal to p, using t currency
The value after 1 is added to go to update t, and repeat step D~step F；
G. f-th of product term b of the combinational circuit a to combinational circuit b is judgedfMinor function af(x1,x2,…,xn) expression formula
Whether it is tautology, detailed process is：
G-1. minor function a is first determined whetherf(x1,x2,…,xn) the value of expression formula whether be 0, if minor function af(x1,
x2,…,xn) the value of expression formula be 0, then minor function af(x1,x2,…,xn) expression formula be not tautology, combinational circuit a
Not comprising combinational circuit b, combinational circuit a and combinational circuit b are not logically equivalent relations, and detection is completed；If minor function af
(x1,x2,…,xn) expression formula value not be 0, then into step G-2, to minor function af(x1,x2,…,xn) expression formula
Value whether be 1 to be judged；
G-2. if minor function af(x1,x2,…,xn) the value of expression formula be 1, then minor function af(x1,x2,…,xn) table
It is tautology up to formula, into step G-6, if minor function af(x1,x2,…,xn) the value of expression formula be not 1, then enter step
Rapid G-3；
G-3. from complementary minorIn randomly select the complementary minor for being not equal to 0 of unselected mistake, be designated asv
For integer and 1≤v≤p, fromExpression formula in randomly select one not equal to-word variable, be designated as x "vs, s is
Integer more than or equal to 1 and less than or equal to n, by x "vsCorresponding variable xsAs variable is split, calculated according to shannon's expansion theorem
Minor function af(x1,x2,…,xn) expression formula to xsFormer variable xsComplementary minor, obtained complementary minor is designated asAccording to
Shannon's expansion theorem calculates minor function af(x1,x2,…,xn) expression formula to xsContravariantComplementary minor, by what is obtained
Complementary minor is designated asSubsequently into step G-4, judgeWhether it is tautology；
G-4. judgeWhether it is tautology, is specially：IfValue be 0, thenIt is not tautology, combinational circuit a is not wrapped
B containing combinational circuit, combinational circuit a and combinational circuit b are not logically equivalent relations, and detection is completed；IfValue be 0, then
Continue to judgeValue whether be 1, ifValue be not 1, then repeat step G-3 and step G-4；IfValue be 1,
ThenIt is tautology, into step G-5；
G-5. using judgementWhether it is that the method for tautology judgesWhether it is tautology, ifTautology, then group
It is not logically equivalent relation to close circuit a not including combinational circuit b, combinational circuit a and combinational circuit b, and detection is completed；IfIt is weight
Speech formula, then show af(x1,x2,…,xn) it is tautology, into step G-6；
Whether the currency for G-6. judging f is q, if f currency is not q, adds the value after 1 to go more using f currency
New f, then repeat step (2) step B~step G, if f currency is q, show that combinational circuit a includes combination electricity
Road b, into step (3)；
(3) whether combinational circuit b identicals method is included to judge whether combinational circuit b includes group using judgement combinational circuit a
Circuit a is closed, if combinational circuit b includes combinational circuit a, it is logically equivalent relation to show combinational circuit a and combinational circuit b,
If it is not logically equivalent relation that combinational circuit b, which does not include combinational circuit a, combinational circuit a and combinational circuit b, detection is completed.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109188825A (en) * | 2018-10-09 | 2019-01-11 | 宁波大学 | Optics half adder based on graphene surface plasmon |
| CN111797588A (en) * | 2020-07-03 | 2020-10-20 | 国微集团(深圳)有限公司 | Formal verification comparison point matching method, system, processor and memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6611947B1 (en) * | 2000-08-23 | 2003-08-26 | Jasper Design Automation, Inc. | Method for determining the functional equivalence between two circuit models in a distributed computing environment |
| US6993730B1 (en) * | 2001-01-10 | 2006-01-31 | Tempus Fugit, Inc. | Method for rapidly determining the functional equivalence between two circuit models |
| US7890901B2 (en) * | 2006-03-24 | 2011-02-15 | International Business Machines Corporation | Method and system for verifying the equivalence of digital circuits |
| CN103258079A (en) * | 2013-04-08 | 2013-08-21 | 宁波大学 | Equivalent function test method for digital combined logic circuits |
| CN104133931A (en) * | 2013-05-02 | 2014-11-05 | 国际商业机器公司 | Method and system for detecting corresponding paths in combinationally equivalent circuit designs |
| CN106997408A (en) * | 2016-01-22 | 2017-08-01 | 奇捷科技股份有限公司 | Circuit verification |
-
2017
- 2017-11-16 CN CN201711136173.6A patent/CN107798203B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6611947B1 (en) * | 2000-08-23 | 2003-08-26 | Jasper Design Automation, Inc. | Method for determining the functional equivalence between two circuit models in a distributed computing environment |
| US6993730B1 (en) * | 2001-01-10 | 2006-01-31 | Tempus Fugit, Inc. | Method for rapidly determining the functional equivalence between two circuit models |
| US7890901B2 (en) * | 2006-03-24 | 2011-02-15 | International Business Machines Corporation | Method and system for verifying the equivalence of digital circuits |
| CN103258079A (en) * | 2013-04-08 | 2013-08-21 | 宁波大学 | Equivalent function test method for digital combined logic circuits |
| CN104133931A (en) * | 2013-05-02 | 2014-11-05 | 国际商业机器公司 | Method and system for detecting corresponding paths in combinationally equivalent circuit designs |
| CN106997408A (en) * | 2016-01-22 | 2017-08-01 | 奇捷科技股份有限公司 | Circuit verification |
Non-Patent Citations (6)
| Title |
|---|
| Y. MATSUNAGA: ""An efficient equivalence checker for combinational circuits"", 《33RD DESIGN AUTOMATION CONFERENCE PROCEEDINGS, 1996》 * |
| YUAN YUE等: ""An Equivalence Checking Method for Circuits with Black Boxes Based on Logic Cone and SAT"", 《2010 INTERNATIONAL CONFERENCE ON MANAGEMENT AND SERVICE SCIENCE》 * |
| 曾琼 等: ""组合电路等价性检验方法研究"", 《计算机工程》 * |
| 曾琼: ""基于递归学习的组合电路等价性检验方法研究"", 《成都信息工程学院学报》 * |
| 李光辉 等: ""基于BDD的组合电路等价性检验方法"", 《微电子学与计算机》 * |
| 郑飞君 等: ""使用布尔可满足性的组合电路等价性验证算法"", 《电子与信息学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109188825A (en) * | 2018-10-09 | 2019-01-11 | 宁波大学 | Optics half adder based on graphene surface plasmon |
| CN111797588A (en) * | 2020-07-03 | 2020-10-20 | 国微集团(深圳)有限公司 | Formal verification comparison point matching method, system, processor and memory |
| WO2022000576A1 (en) * | 2020-07-03 | 2022-01-06 | 国微集团(深圳)有限公司 | Formal verification comparison point matching method and system, processor, and memory |
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