CN104598352B - Rapid reliability evaluation method for SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) - Google Patents

Abstract

The invention specifically provides a rapid reliability evaluation method for an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array). The method comprises the following steps: (1) dividing a to-be-processed VHD (Virtual Hard Disk) source program into L modules according to a module division criterion determined according to a VHDL (Very High Speed Integrated Circuit Hardware Description Language) hardware language; (2) performing integration, mapping, layout wiring and XDL (Xilinx Design Language) file generation operation on the L modules in combination with a hardware design tool ISE (Integrated Software Environment) in sequence; (3) performing rough calculation by using a probability analysis method to obtain the soft error rate of each module and adding the soft error rates to a rough calculation set C1; (4) selecting a threshold value delta for the C1 by using a maximum between-class variance algorithm OSTU; adding the module with the soft error rate of being greater than the delta into an accurate calculation set C2; (5) performing accurate calculation on the soft error rate SER for each module in the accurate calculation set C2 by using a monte carlo method respectively, and saving the results in a protection set S from big to small. While the calculation accuracy is guaranteed, the calculation time in the reliability evaluation process of the SRAM type FPGA can be reduced as much as possible.

Description

A kind of fast reliability evaluation method for SRAM type FPGA

Technical field

The invention belongs to circuit reliability assessment technology field, particularly to the reliability estimation method of SRAM type FPGA, A kind of fast reliability evaluation method for SRAM type FPGA.

Background technology

SRAM type FPGA is the FPGA circuitry structure of main flow in the market, and it all obtains in fields such as space flight, medical treatment, automobiles To being widely applied.But, SRAM type FPGA, under the bombardment of high energy particle, is susceptible to soft error, and soft error mainly shows For: the circuit configuration bit of FPGA, i.e. sram cell changes, and causes circuit topology logical error；FPGA trigger stores Logical value change, cause circuit operations conditions mistake.Along with the continuous progress of chip manufacturing process, chip feature sizes More and more less, the high-energy particle bombardment energy required for FPGA generation soft error decreases, and causes the soft error of SRAM type FPGA Incidence rate is increasing by mistake.Therefore, in the design process, generally SRAM type FPGA is carried out reliability assessment, and then instructs Reliability optimization.

The reliability estimation method of SRAM type FPGA is broadly divided into two classes: reliability estimation method based on hardware simulation and Reliability estimation method based on software.Reliability estimation method based on hardware simulation needs the hardware experiments equipment such as irradiation, SRAM type fpga chip is positioned in radiation environment, the actual working environment of simulation SRAM type fpga chip, observes and analyze SRAM type fpga chip is by the fault occurrences after high-energy particle bombardment, thus assesses the reliable of SRAM type fpga chip Property.But, reliability estimation method based on hardware simulation needs the equipment that price is high, and is for general on circuit design Later stage assessment reliability, it is impossible to instruct the optimization of circuit reliability in circuit design early stage.Generally, based on hardware simulation Reliability estimation method be only used for SRAM type fpga chip is carried out chip characteristics analysis.

Reliability estimation method based on software simulation is only broken down by software program models SRAM type FPGA circuitry Situation, it is not necessary to build hardware irradiation platform, and reliability assessment can be carried out, at the beginning of circuit design after circuit meshwork list generates Phase is reliability optimization and provides effective guidance.Therefore, SRAM type FPGA reliability assessment mainly uses and simulates based on software Method.

At present, the index that reliability estimation method based on software simulation uses is soft error rate SER (Soft Error Rate).The computational methods of the soft error rate SER of SRAM type FPGA can be divided into two classes, respectively: reliability based on Monte Carlo Appraisal procedure (hereinafter referred to as Monte Carlo method) and reliability estimation method based on probability analysis are (the most general Rate analytic process).Monte Carlo method needs to travel through all faults to be assessed and input vector.First fault F to be assessed is chosen, Then travel through all possible input vector, for each input vector P, analyze whether fault F under this input vector P makes circuit Losing efficacy, concrete analysis method is to calculate circuit under input vector P to export vector P output electricity under result, and fault F normally The output result of gained behind road, as result difference then decision circuitry lost efficacy.Wait to travel through all input vectors and all events to be assessed After barrier, the soft error rate SER of SRAM type FPGA can be drawn.

Monte Carlo method has the highest computational accuracy.But, it needs input vector all possible to circuit to enter Row is analyzed.For the circuit of N number of input, each fault to be assessed is required for analyzing 2^NIndividual input vector.Along with circuit scale Increasing, the number of input vector is in exponential increase, and in circuit, the number of fault to be assessed is consequently increased, and therefore, calculates fault Probability of spreading needs the time grown very much.Such as, for the circuit of 10,000, Monte Carlo method is used to calculate fault propagation Probability needs the yearlong time.

Probability analysis method needs also exist for traveling through all faults to be assessed, but different from Monte Carlo method, and it need not traversal All input vectors, therefore can effectively reduce the calculating time.Probability analysis method calculates the computing formula of soft error rate SER such as Under:

$\mathrm{SER}=\underset{i=1}{\overset{N_F}{\mathrm{\Σ}}}{\mathrm{NER}}_i\×{\mathrm{EPP}}_i$

Wherein, N_FMalfunctioning node sum to be assessed in indication circuit.It is said that in general, each in SRAM type FPGA circuitry Bar line, each look-up table (LUT, Look Up Table) is all it may happen that fault.If look-up table LUT there occurs fault, So arise that fault value on the output lead of this look-up table, it is believed that break down on line.Therefore, it can by dividing The fault of analysis line analyzes the reliability of SRAM type FPGA, i.e. every line in SRAM type FPGA circuitry is all a fault Node.Probability of node failure NER_i(Node Error Rate) represents the probability that i-th fault occurs, and it is mainly strong by irradiation Spend the configuration bit number corresponding with abort situation to determine.Irradiation intensity is the biggest, and i.e. high energy particle is the most, energy is the biggest, then SRAM type FPGA is the biggest by the probability broken down after high-energy particle bombardment.On the other hand, the configuration ratio that abort situation is corresponding Special number is the most, and the probability that fault occurs is the biggest.Such as, the line in SRAM type FPGA circuitry is by multiple configuration bit certainly Fixed, any one configuration bit is overturn by high-energy particle bombardment, and this line all may be caused to break down.Fault propagation Probability EPP_i(Error Propagation Probability) represents that i-th fault makes the probability of circuit malfunction, it mainly by Circuit topology logic determines.Calculate probability of failure propagation EPP_iTime, assume initially that each input takes the probability of logical value 0 and 1 each Be 0.5, then by definition logical operations and two kinds of calculative rule of the probabilities of fault propagation, obtain each fault propagation to exporting, Make the probability of circuit malfunction.

Specifically, the calculative rule of the probability of logical operations defines: each input of a known look-up table is 0 or is 1 Probability, how to calculate this look-up table be output as 0 or be 1 probability.Such as, two inputs for an AND function are searched Table, its probability being output as 0 is equal to the probability that the input of any look-up table is 0, and it is output as probability of 1 equal to all look-up tables Input is the probability of 1 simultaneously；For two input look-up tables of an OR function, it is output as the probability of 1 equal to arbitrarily searching Table input is the probability of 1, and its to be output as probability of 0 be the probability of 0 equal to the input of all look-up tables simultaneously.Fault propagation general Rate computation rule defines: known fault travels to some probability inputted of a look-up table LUT and other input of look-up table is 0 Or be 1 probability, how to calculate the probability that fault propagation exports to this look-up table.For example, it is assumed that fault only travels to look-up table An input, for the look-up table of an AND function, the probability that fault propagation to look-up table exports arrives equal to fault propagation Look-up table one input and simultaneously another input are the probability of 1；For the look-up table of an OR function, fault propagation is to looking into The probability looking for table to export is the probability of 0 equal to the input of fault propagation to look-up table one and another input simultaneously.

Therefore, probability analysis method need not analyze concrete input vector, it is possible to is calculated the soft error of SRAM type FPGA Rate SER, decreases a large amount of calculating time by mistake.But, logical operations defined above and two kinds of calculative rule of the probabilities of fault propagation All assume circuit does not exist between each input of each look-up table the dependency of logical value, i.e. assume appointing of a look-up table Anticipate and there is not dependency between logical value and other logical value inputted of this look-up table of an input.This hypothesis is at actual electricity Road is not always set up, thus the precision of probability analysis method can not show a candle to Monte Carlo method.

As can be seen here, Monte Carlo method has the advantage that computational accuracy is high, but its calculating time is long, and probability analysis method is gathered around There is the advantage that the calculating time is short, but its computational accuracy is not enough.Therefore, in the urgent need to finding a kind of preferably reliability assessment side Method, it can reduce the calculating time, it is achieved the most accurate to SRAM type FPGA circuitry while ensureing computational accuracy as far as possible True reliability assessment.

Summary of the invention

It is an object of the invention to the shortcoming overcoming above-mentioned prior art, it is provided that one can either ensure computational accuracy, again may be used To reduce the fast reliability evaluation solution being applicable to SRAM type FPGA of calculating time.

For achieving the above object, the invention provides a kind of fast reliability evaluation method being applicable to SRAM type FPGA, Comprise the steps:

(1) according to the design rule of VHDL hardware language, Module Division criterion is determined, and by pending VHD source program It is divided into L module according to Module Division criterion；

(2) combined with hardware design tool ISE, L module after dividing is carried out successively comprehensively, maps, placement-and-routing with And generate XDL file operation；

(3) utilizing probability analysis method to be analyzed the XDL file of L module, rough calculation obtains the soft error rate of each module SER is also added to rough calculation set C₁, i.e. C₁={ SER₁,SER₂,...,SER_L, wherein, SER_iRepresent rough calculation obtain i-th The soft error rate of individual module；

(4) to rough calculation set C₁Use maximum between-cluster variance algorithm OSTU selected threshold δ；If the soft error of i-th module Rate is more than threshold value δ, i.e. SER_i>=δ, 1≤i≤L, then it is assumed that this module need to carry out the accurate calculating of soft error rate SER, is added It is added to count carefully set C₂In；

(5) to counting carefully set C₂In each module be respectively adopted Monte Carlo method and carry out the accurate calculating of soft error rate SER, and By result of calculation according to being stored in from big to small in protection set S；Protection set S is used for instructing reliability optimization.

Module Division criterion described in above-mentioned steps (1) is specific as follows:

2.1) if this section of VHDL code is process statements, then as a module；

2.2) if this section of VHDL code is element example statement, then as a module；

2.3) if this section of VHDL code is generated statement, then as a module；

2.4) if this section of VHDL code is block statement, then as a module；

2.5) if this section of VHDL code is function statement, then as a module；

2.6) if this section of VHDL code is procedure statement, then as a module.

In above-mentioned steps (2), the concrete operations to described module process as follows:

3.1) independent, the VHD file that can comprehensively map of read module；

3.2) VHD file to this module, calls the order in ISE software successively, and combined process uses XST order, reflects Being emitted through journey uses MAP order, placement-and-routing's process to use PAR and TRCE order, and the generation process of XDL file uses XDL order；

3.3) if also having the module not carrying out aforesaid operations, then step 3.1 is returned) untreated module is processed； Until described L module is all disposed.

The concrete rough calculation step of the individual module in above-mentioned steps (3) is as follows:

4.1) node error probability NER of each node in module is obtained by the XDL file of module_i, node mistake is general Rate NER_iBy obtaining with following formula<1>,

NER_i=R_p×N_SRAM <1>

Wherein, R_pFor the original error rate of each sram cell, by searching the simple grain of concrete SRAM type fpga chip Sub-laboratory manual obtains；N_SRAMFor the configuration bit number that node location is corresponding, the configuration bit number that each node location is corresponding Mesh is by analyzing the XDL file acquisition of module；

4.2) by the XDL file of module, it is thus achieved that the probability of failure propagation EPP of each node in module_i。

The concrete operation step of above-mentioned steps (4) is as follows:

5.1) to rough calculation set C₁In the soft error rate SER of all modules carry out histogram calculation normalized, soft Error rate SER only gets 2 significant digits, obtains rough calculation set C₁The probability that soft error rate SER is 0.01～1 of middle module；

5.2) making thresholding is t, and the soft error rate SER module less than or equal to t is classified as A class, and soft error rate SER is more than t's Module is classified as B class, calculates when thresholding t takes 0.01 to 1 respectively, when step-length is 0.01, and the probability of occurrence P of A class and B class_A、P_BAnd Average Avg_AAnd Avg_B；

5.3) the inter-class variance σ of A class and B class is calculated by following formula<2>；When inter-class variance σ takes maximum, its Corresponding thresholding t is threshold value δ；

σ (t)=P_A×(Avg_A-T)+P_B×(Avg_B-T) <2>

Wherein, T is the soft error rate SER average that all modules are total,

5.4) by rough calculation set C₁Middle soft error rate SER adds to more than the module of threshold value δ and counts carefully set C₂In, then count carefully Set C₂In all modules be the targets needing preferential protection.

Beneficial effects of the present invention:

1. the present invention is determined by Module Division criterion, VHD source file is divided into multiple module, enters in units of module The calculating of row soft error rate SER, it is to avoid the engineering that process is fairly large, saves the substantial amounts of calculating time, simple to operate, just In enforcement；

2. the present invention uses probability analysis method to carry out the calculating of soft error rate SER during rough calculation, is ensureing substantially essence The calculating time is reduced as far as possible while degree.Compared with Monte Carlo method, probability analysis method is used to be more suitable for during rough calculation The realization of concrete engineering；

3. the present invention passes through maximum between-cluster variance algorithm OSTU algorithm picks threshold value δ, finds the module needing preferential protection, I.e. soft error rate SER, more than the module of threshold value δ, eliminates a large amount of without accurately calculating the module of soft error rate, thus is Time needed for reducing the reliability of assessment SRAM type FPGA further lays the foundation；

4. the present invention is to counting carefully set C₂In all modules use Monte Carlo method calculate soft error rate, take full advantage of The advantage that Monte Carlo method computational accuracy is high, and owing to counting carefully set C₂In the number of modules that comprises less, overcome illiteracy spy Calot's method processes the shortcoming that a large amount of modules cause calculating time length；

5. the present invention uses rough calculation and counts carefully two steps and combine, and can be greatly reduced soft on the premise of ensureing precision The calculating time of error rate, protection set S can be directly used for instructing the enforcement of the safeguard procedures for SRAM type FPGA.

Below with reference to accompanying drawing, the present invention is described in further details.

Accompanying drawing explanation

Fig. 1 is the flowchart of the present invention；

Fig. 2 Monte Carlo method calculates the flow chart of soft error rate SER.

Detailed description of the invention

Referring to the drawings the present invention is described in detail.

With reference to Fig. 1, the present invention to implement step as follows:

Step one, according to the design rule of VHDL hardware language, determines Module Division criterion.Read VHD engineering source file, Carry out the division of module according to Module Division criterion, divide independent, the VHD file that can comprehensively map obtaining L module, L's Value depends on scale and the design structure of VHD engineering source program.Module Division criterion is specific as follows:

(1) if this section of VHDL code is process statements (process), then as a module；

(2) if this section of VHDL code is element example statement, then as a module, wherein element example statement list Show for connecting bottom module, build the statement of upper layer module；

(3) if this section of VHDL code is generated statement (generate), then as module, wherein a generated statement Represent the statement for describing the element example process with regularity；

(4) if this section of VHDL code is block statement (block), then as a module, wherein block statement represents use Statement in the submodule of description scheme body；

(5) if this section of VHDL code is function statement (function), then as module, wherein a function statement Represent for defining specific conventional module, for the statement of routine call；

(6) if this section of VHDL code is procedure statement (procedure), then as module, wherein a process language Sentence represents for defining specific conventional module, for the statement of routine call.

Step 2, in conjunction with hardware designs instrument ISE (the Integrated Software of Xilinx company exploitation Environment), L module after dividing is carried out comprehensively successively, mapping, placement-and-routing, generation XDL file etc. operate, have Body step is as follows:

2.1) independent, the VHD file that can comprehensively map of read module；

2.2) VHD file to this module, calls the order in ISE software successively, and combined process uses XST order, reflects Being emitted through journey uses MAP order, placement-and-routing's process to use PAR and TRCE order, and the generation process of XDL file uses XDL order；

2.3) if also having the module not carrying out aforesaid operations, then return step 2.1 and untreated module is carried out accordingly Process；If L module is processed complete, then carry out step 3.

Step 3, utilizes probability analysis method to be analyzed the XDL file of L module, and rough calculation obtains the soft error of each module Rate SER of mistake is also added to rough calculation set C₁.The concrete rough calculation step of individual module is as follows:

3.1) the XDL file of module is analyzed, it is thus achieved that node error probability NER of each node in module_i(Node Error Rate).Node error probability NER_iCan be obtained by following formula,

NER_i=R_p×N_SRAM<1>wherein, R_pFor the original error rate of each sram cell, itself and concrete SRAM The concrete model of type fpga chip is relevant with irradiation intensity, and original error rate can be by searching the single-particle laboratory manual of this chip Obtain；N_SRAMFor the configuration bit number that node location is corresponding.The XDL file of module describes the concrete configuration of each node Situation, the configuration bit number that the most each node location is corresponding can be obtained automatically by the XDL file of software analysis module；

3.2) the XDL file of module is analyzed, it is thus achieved that the probability of failure propagation EPP of each node in module_i.The fault of node Probability of spreading EPP_iConcrete calculation procedure as follows:

Table 1 fault propagation rule

3.2.1) inst and the net information in the XDL file of acquisition module, what inst represented is the fault joint in circuit Point, what net represented is the annexation between malfunctioning node.Therefore, Depth Priority Algorithm and topological sorting algorithm, structure are utilized Produce the circuit meshwork list of module；

3.2.2) assuming that each input node in module takes the probability of logical value 0 and 1 is respectively 0.5, and defines logic fortune Calculate and two kinds of calculative rule of the probabilities of fault propagation.Wherein, the logical operations of malfunctioning node can be believed by analyzing the configuration in inst Breath obtains, and fault propagation rule is as shown in table 1 below.Thus obtain each malfunctioning node and travel to output, make the general of circuit malfunction Rate, i.e. probability of failure propagation EPP_i。

3.3) it is calculated the soft error rate SER of module according to formula (1), and its result of calculation is saved in rough calculation set C₁ In.

Step 4, to rough calculation set C₁Use maximum between-cluster variance algorithm OSTU selected threshold δ, it is thus achieved that need to preferentially protect Count carefully set C₂.Specifically comprise the following steps that

4.1) to rough calculation set C₁In the soft error rate SER of all modules carry out histogram calculation normalized, soft Error rate SER only gets 2 significant digits, thus obtains rough calculation set C₁The soft error rate SER of middle module is 0.01～1 Probability.Such as, if rough calculation set C₁In have 100 modules, the soft error rate SER having 5 modules is 0.02, then soft error rate SER be the probability of 0.02 be P=5/100=0.05；

4.2) making thresholding is t, and the soft error rate SER module less than or equal to t is classified as A class, and soft error rate SER is more than t's Module is classified as B class.Calculate when thresholding t takes 0.01 to 1 respectively, when step-length is 0.01, the probability of occurrence P of A class and B class_A、P_BAnd Average Avg_AAnd Avg_B.Wherein, probability P_AAnd P_BAs step 4.1 computational methods；Average Avg_AAnd Avg_BIt is respectively

${\mathrm{Avg}}_A=\underset{i=0.01}{\overset{t}{\mathrm{\&Sigma;}}}i\&times;P\left(i\right),{\mathrm{Avg}}_B=\underset{i=t+0.01}{\overset{1}{\mathrm{\&Sigma;}}}i\&times;P\left(i\right);$

4.3) the inter-class variance σ of A class and B class can be calculated by formula<2>.When inter-class variance σ takes maximum, it is corresponding Thresholding t be threshold value δ.

σ (t)=P_A×(Avg_A-T)+P_B×(Avg_B-T) <2>

Wherein, T is the soft error rate SER average that all modules are total,

4.4) by rough calculation set C₁Middle soft error rate SER adds to more than the module of threshold value δ and counts carefully set C₂In, count carefully collection Close C₂In all modules be the targets needing preferential protection, step 5 carry out the accurate calculating of soft error rate SER.

Step 5, to counting carefully set C₂In each module be respectively adopted Monte Carlo method and calculate its soft error rate SER ', cover spy Calot's method calculates the flow chart of soft error rate as in figure 2 it is shown, result of calculation is stored in protection set S.Specifically comprise the following steps that

5.1) set C is being counted carefully₂One untreated module of middle selection；

5.2) select fault F to be assessed, travel through all possible input vector, for each input vector P, point Analysing whether fault F under this input vector P makes modular circuit lose efficacy, concrete analysis method is to calculate input vector P lower module electricity Road exports under result, and fault F the output result of gained after vector P input module circuit normally, if two result differences Then judge that this fault F makes modular circuit lose efficacy under vector P；

5.3) if modular circuit also has the fault do not assessed, then step 5.2 is returned；If the institute in modular circuit is faulty The most analyze complete, then calculated the soft error rate SER ' of this module according to formula<3>, and carry out step 5.4,

${\mathrm{SER}}^{\&prime;}=\frac{N_{\mathrm{Fail}}}{N_{\mathrm{Input}}}---<3>$

Wherein, N_InputFor the sum of the spendable input vector of modular circuit, N_FailDefeated for cause modular circuit to lose efficacy The sum of incoming vector；

5.4) if counting carefully set C₂In also have untreated module, then return step 5.1 this module is processed；If it is thin Calculate set C₂In all modules be processed complete, then will count carefully set C₂In all modules according to soft error rate SER ' from It is saved in protection set S to little greatly.Protection set S can be directly used for instructing the reliability optimization to SRAM type FPGA.

In sum, the invention have the advantages that

1. the present invention is determined by Module Division criterion, VHD source file is divided into multiple module, enters in units of module The calculating of row soft error rate SER, it is to avoid the engineering that process is fairly large, saves the substantial amounts of calculating time, simple to operate, just In enforcement；

2. the present invention uses probability analysis method to carry out the calculating of soft error rate SER during rough calculation, is ensureing substantially essence The calculating time is reduced as far as possible while degree.Compared with Monte Carlo method, probability analysis method is used to be more suitable for during rough calculation The realization of concrete engineering；

3. the present invention passes through maximum between-cluster variance algorithm OSTU algorithm picks threshold value δ, finds the module needing preferential protection, I.e. soft error rate SER, more than the module of threshold value δ, eliminates a large amount of without accurately calculating the module of soft error rate, thus is Time needed for reducing the reliability of assessment SRAM type FPGA further lays the foundation；

4. the present invention is to counting carefully set C₂In all modules use Monte Carlo method calculate soft error rate, take full advantage of The advantage that Monte Carlo method computational accuracy is high, and owing to counting carefully set C₂In the number of modules that comprises less, overcome illiteracy spy Calot's method processes the shortcoming that a large amount of modules cause calculating time length；

5. the present invention uses rough calculation and counts carefully two steps and combine, and can be greatly reduced soft on the premise of ensureing precision The calculating time of error rate, protection set S can be directly used for instructing the enforcement of the safeguard procedures for SRAM type FPGA.

Parts, technique and the letter representation that embodiment describes the most in detail belongs to well-known components and the conventional means of the industry And general knowledge, describe the most one by one.Exemplified as above is only the illustration to the present invention, is not intended that the protection to the present invention The restriction of scope, within the every and same or analogous design of the present invention belongs to protection scope of the present invention.

Claims (5)

1. the fast reliability evaluation method being applicable to SRAM type FPGA, it is characterised in that: comprise the steps:

(1) according to the design rule of VHDL hardware language, determine Module Division criterion, and by pending VHD source program according to Module Division criterion is divided into L module；

(2) combined with hardware design tool ISE, carries out successively comprehensively L module after dividing, maps, placement-and-routing and life Become XDL file operation；

(3) utilizing probability analysis method to be analyzed the XDL file of L module, rough calculation obtains the soft error rate SER of each module also It is added to rough calculation set C₁, i.e. C₁={ SER₁,SER₂,…,SER_L, wherein, SER_iRepresent the i-th module that rough calculation obtains Soft error rate；

(4) to rough calculation set C₁Use maximum between-cluster variance algorithm OSTU selected threshold δ；If the soft error rate of i-th module is more than Threshold value δ, i.e. SER_i>=δ, 1≤i≤L, then it is assumed that this module need to carry out the accurate calculating of soft error rate SER, is added to thin Calculate set C₂In；

(5) to counting carefully set C₂In each module be respectively adopted Monte Carlo method and carry out the accurate calculating of soft error rate SER, and will meter Calculate result according to being stored in from big to small in protection set S；Protection set S is used for instructing reliability optimization.

A kind of fast reliability evaluation method being applicable to SRAM type FPGA, it is characterised in that: step Suddenly the Module Division criterion described in (1) is specific as follows:

2.1) if a certain section of VHDL code in described VHD source program is process statements, then as a module；

2.2) if a certain section of VHDL code in described VHD source program is element example statement, then as a module；

2.3) if a certain section of VHDL code in described VHD source program is generated statement, then as a module；

2.4) if a certain section of VHDL code in described VHD source program is block statement, then as a module；

2.5) if a certain section of VHDL code in described VHD source program is function statement, then as a module；

2.6) if a certain section of VHDL code in described VHD source program is procedure statement, then as a module.

A kind of fast reliability evaluation method being applicable to SRAM type FPGA, it is characterised in that: step Suddenly as follows to the concrete operations process of described module in (2):

3.1) independent, the VHD file that can comprehensively map of read module；

3.2) VHD file to this module, calls the order in ISE software successively, and combined process uses XST order, maps Journey uses MAP order, placement-and-routing's process to use PAR and TRCE order, and the generation process of XDL file uses XDL order；

3.3) if also having the module not carrying out aforesaid operations, then step 3.1 is returned) untreated module is processed；Until Described L module is all disposed.

A kind of fast reliability evaluation method being applicable to SRAM type FPGA, it is characterised in that: institute The concrete rough calculation step stating individual module in step (3) is as follows:

4.1) node error probability NER of each node in module is obtained by the XDL file of module_i, node error probability NER_i By obtaining with following formula<1>,

NER_i=R_p×N_SRAM <1>

Wherein, R_pFor the original error rate of each sram cell, test by searching the single-particle of concrete SRAM type fpga chip Handbook obtains；N_SRAMFor the configuration bit number that node location is corresponding, the configuration bit number that each node location is corresponding passes through Analyze the XDL file acquisition of module；

4.2) by the XDL file of module, it is thus achieved that the probability of failure propagation EPP of each node in module_i。

A kind of fast reliability evaluation method being applicable to SRAM type FPGA, it is characterised in that: institute The concrete operation step stating step (4) is as follows:

5.1) to rough calculation set C₁In the soft error rate SER of all modules carry out histogram calculation normalized, soft error rate SER only gets 2 significant digits, obtains rough calculation set C₁The probability that soft error rate SER is 0.01～1 of middle module；

5.2) making thresholding is t, and the soft error rate SER module less than or equal to t is classified as A class, the soft error rate SER module more than t It is classified as B class, calculates when thresholding t takes 0.01 to 1 respectively, when step-length is 0.01, the probability of occurrence P of A class and B class_A、P_BAnd average Avg_AAnd Avg_B；

5.3) the inter-class variance σ of A class and B class is calculated by following formula<2>；When inter-class variance σ takes maximum, it is corresponding Thresholding t be threshold value δ；

σ (t)=P_A×(Avg_A-T)+P_B×(Avg_B-T) <2>

Wherein, T is the soft error rate SER average that all modules are total,

5.4) by rough calculation set C₁Middle soft error rate SER adds to more than the module of threshold value δ and counts carefully set C₂In, then count carefully set C₂In all modules be the targets needing preferential protection.