CN107797892B - A kind of memory SPD adjustment method - Google Patents
A kind of memory SPD adjustment method Download PDFInfo
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- CN107797892B CN107797892B CN201711215906.5A CN201711215906A CN107797892B CN 107797892 B CN107797892 B CN 107797892B CN 201711215906 A CN201711215906 A CN 201711215906A CN 107797892 B CN107797892 B CN 107797892B
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- 230000005611 electricity Effects 0.000 claims description 6
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- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 claims description 3
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- 238000011084 recovery Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims 1
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- 238000004519 manufacturing process Methods 0.000 description 2
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- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
- G06F11/2635—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers using a storage for the test inputs, e.g. test ROM, script files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a kind of memory SPD adjustment methods, realize process are as follows: are first stored in SPD on debugging host with document form；Then the web management interface for logging in BMC, selects SPD firmware, into the more new stage；So that debugging host is in off-mode, and use Standby power voltage supply, EEPROM is accessed by BMC, firmware is written to EEPROM；Mainboard booting decides whether the configuration for further adjusting memory SPD according to the situation that starts and runs of system.A kind of memory SPD adjustment method of the invention compared with prior art, using the outband management function of BMC, debugs memory SPD by carrying out on line refreshable operation to SPD firmware, it is simple and effective, cost can greatly be saved, it is practical, it is applied widely, it is easy to spread.
Description
Technical field
The present invention relates to computer server technical field, specifically a kind of memory SPD adjustment method.
Background technique
It is often placed on server master board a BMC (Baseboard Management Controller), BMC is provided
The interfaces such as I2C access external devices, can be not keyed up in host by the management network of BMC, the inaccessible when progress of business network
Server outband management.
For reinforcement type server, memory is often by the way of Surface Mount memory grain, to improve stability and reliability.
Since Surface Mount memory grain is different from the standardized memory bar of memory bar manufacturer production, server production firm needs in
SPD (Serial Presence Detect) configuration parameter of the PCB characteristic design specialized of parameter configuration specification and mainboard is deposited, it is no
It then may cause mainboard that can not start since memory parameters setting is unreasonable, may need that memory is varied multiple times in this course
SPD configuration parameter can just make memory reach the working condition of reliable and stable operation.Therefore, it for this needs that SPD is varied multiple times
The case where firmware, using burning SPD firmware to EEPROM so that test the whether feasible method of SPD configuration parameter have it is very big not
Just.How simply and effectively to carry out debugging to memory SPD firmware is a technical issues that need to address.
Summary of the invention
Technical assignment of the invention be against the above deficiency place, a kind of memory SPD adjustment method is provided.
A kind of memory SPD adjustment method realizes process are as follows:
One, SPD is stored on debugging host with document form first；
Two, the web management interface of BMC is then logged in, SPD firmware is selected, into the more new stage；
Three, so that debugging host is in off-mode, and use Standby power voltage supply, EEPROM is accessed by BMC, will be consolidated
Part is written to EEPROM；
Four, mainboard is switched on, and decides whether the configuration for further adjusting memory SPD according to the situation that starts and runs of system.
The debugging host refers to reinforcement type server, in the server configured with mainboard, DDR4 Surface Mount memory,
CPLD, EEPROM place a BMC on mainboard, and BMC has the management network independently of debugging host and provides out-of-band access,
The Web client with web management interface is provided in debugging host, which connects BMC.
Refresh mould configured with Web server, power management module, power supply and channel switching module, firmware in the BMC
Block, wherein configured with web interface module, the file upload function module communicated with Web page in Web server；Power management
Module connects above-mentioned web interface module and the CPLD independently of BMC；Power supply connects above-mentioned web interface mould with channel switching module
Block and switching circuit independently of BMC, the switching circuit is for switching Always voltage and Standby voltage；Firmware refreshes
Module receives the SPD firmware that file upload function module is sent and dumps in EEPROM.
Firmware is written in EEPROM by I2C bus by the BMC, i.e., passes through between firmware refresh module and EEPROM
The connection of I2C bus.
In the step 1, first according to the memory SPD of memory parameters configuration specification and mainboard PCB characteristic design,
Then it is stored in the debugging host for logging in BMC administration interface in the form of a file again.
BMC administration interface process is logged in the step 2 are as follows: debugging host first powers on, and system to be managed completes starting
It manages network and the web management interface for logging in BMC after can be used selects in step 1 in the web management interface with document form
The memory SPD firmware of storage issues the order for updating SPD firmware and entering the firmware update stage.
The process of Standby power voltage supply is used in the step 3 are as follows:
The web interface module of BMC calls power management module to obtain main-board on-off state, if mainboard is in booting shape
State then prompts user to shut down computer, and the web interface module of BMC is called power management module to send and closed after obtaining user and agreeing to
Machine order；
The web interface module of BMC calls the power supply and I2C letter of power supply and channel switching module execution eeprom chip
Road switching action makes the system electricity under default situations be changed to the Standby voltage that BMC is used, by CPU access EEPROM be changed to by
BMC accesses EEPROM.
Firmware is written to the file upload function module upload SPD firmware that EEPROM refers to the Web server of BMC, and
It is stored under a certain specified directory, SPD firmware is then refreshed to EEPROM by the firmware refresh module of BMC again.
After SPD firmware update, it is also necessary to which the step of carrying out state recovery, i.e. power supply and channel are cut in power supply and channel
It changes the mold and is switched to default connection mode under the control of block, system electricity is changed to Always voltage.
In step 4, after SPD firmware update, the web interface module of BMC calls power management module to send out to mainboard
Send power-on command；According to internal memory initialization when the starting shown in system serial ports and the type information of training, whether it is able to enter
System, into system after system operating condition decide whether change SPD configuration, SPD has been debugged if reaching design requirement
At return step one repeats if meeting design requirements, until reaching design requirement.
Compared to the prior art a kind of memory SPD adjustment method of the invention, has the advantages that
A kind of memory SPD adjustment method of the invention is uploaded by the file upload function that the Web server of BMC provides
SPD firmware to be debugged is to BMC, and firmware is written in EEPROM by I2C bus by BMC, to improve memory SPD debugging efficiency；Make
With the outband management function of BMC, memory SPD, simple and effective, Neng Gouji are debugged by carrying out on line refreshable operation to SPD firmware
Big saving cost, it is practical, it is applied widely, it is easy to spread.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Attached drawing 1 is realization schematic diagram of the invention.
Specific embodiment
Scheme in order to enable those skilled in the art to better understand the present invention, With reference to embodiment to this
Invention is described in further detail.Obviously, described embodiments are only a part of the embodiments of the present invention, rather than all
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art institute without making creative work
The every other embodiment obtained, shall fall within the protection scope of the present invention.
As shown in Fig. 1, a kind of memory SPD adjustment method, the file upload function provided by the Web server of BMC
It uploads SPD firmware to be debugged firmware is written in EEPROM by I2C bus to BMC, BMC, to improve memory SPD debugging effect
Rate.
It realizes process are as follows:
One, SPD is stored on debugging host with document form first；
Two, the web management interface of BMC is then logged in, SPD firmware is selected, into the more new stage；
Three, so that debugging host is in off-mode, and use Standby power voltage supply, EEPROM is accessed by BMC, will be consolidated
Part is written to EEPROM；
Four, mainboard is switched on, and decides whether the configuration for further adjusting memory SPD according to the situation that starts and runs of system.
In above-mentioned steps, the web management interface of BMC is logged in, it is solid to click to update SPD for SPD firmware of the selection by design
Part button enters the firmware update stage, by possible shutdown, file upload, power supply and channel switching and firmware refresh operation
Firmware is written to EEPROM, power supply and channel can be under the controls of power supply and channel switching module after SPD firmware update
It is switched to default connection mode, mainboard booting decides whether further to adjust memory SPD according to the situation that starts and runs of system
Configuration.
The debugging host refers to reinforcement type server, in the server configured with mainboard, DDR4 Surface Mount memory,
CPLD, EEPROM place a BMC on mainboard, and BMC has the management network independently of debugging host and provides out-of-band access,
The Web client with web management interface is provided in debugging host, which connects BMC.
Refresh mould configured with Web server, power management module, power supply and channel switching module, firmware in the BMC
Block, wherein configured with web interface module, the file upload function module communicated with Web page in Web server；Power management
Module connects above-mentioned web interface module and the CPLD independently of BMC；Power supply connects above-mentioned web interface mould with channel switching module
Block and switching circuit independently of BMC, the switching circuit is for switching Always voltage and Standby voltage；Firmware refreshes
Module receives the SPD firmware that file upload function module is sent and dumps in EEPROM.
Further, the method for the present invention realization the following steps are included:
(1) it according to the memory SPD of memory parameters configuration specification and mainboard PCB characteristic design, deposits in the form of a file
Storage is in the debugging host for logging in BMC administration interface；
(2) server powers on, and system to be managed completes the web management interface that BMC is logged in after starting management network is available；
(3) the above-mentioned memory SPD firmware stored with document form is selected in the BMC memory SPD firmware update page, clicked more
New SPD firmware button enters the firmware update stage；
(4) the web interface module of BMC calls power management module to obtain main-board on-off state, opens if mainboard is in
Machine state then prompts user to shut down computer, and the web interface module of BMC calls power management module hair after obtaining user and agreeing to
Send shutdown command；
(5) the web interface module of BMC call power supply and channel switching module execute eeprom chip power supply and
I2C channel switching action makes the system electricity under default situations be changed to the Standby electricity that BMC is used, and is changed by CPU access EEPROM
To access EEPROM by BMC；
(6) the file upload function module of the Web server of BMC uploads SPD firmware, storage to/dev/shm carry/
Under mnt catalogue；
(7) the firmware refresh module of BMC refreshes SPD firmware to EEPROM；
(8) power supply and channel are switched to default under the control of power supply and channel switching module after SPD firmware update
Connection type；
(9) the web interface module of BMC calls power management module to send power-on command to mainboard；
(10) according to the type information of internal memory initialization when the starting shown in system serial ports and training and whether can be into
Enter system and decides whether to change SPD configuration, the SPD tune if reaching design requirement into the operating condition of system after system
Examination is completed, and thens follow the steps (1) until reaching design requirement if met design requirements.
The technical personnel in the technical field can readily realize the present invention with the above specific embodiments,.But it answers
Work as understanding, the present invention is not limited to above-mentioned specific embodiments.On the basis of the disclosed embodiments, the technical field
Technical staff can arbitrarily combine different technical features, to realize different technical solutions.
Except for the technical features described in the specification, it all is technically known to those skilled in the art.
Claims (4)
1. a kind of memory SPD adjustment method, which is characterized in that it realizes process are as follows:
One, SPD is stored on debugging host with document form first；
Two, the web management interface of BMC is then logged in, SPD firmware is selected, into the more new stage；
Three, so that debugging host is in off-mode, and use Standby power voltage supply, EEPROM is accessed by BMC, firmware is write
Enter to EEPROM；
Four, mainboard is switched on, and decides whether the configuration for further adjusting memory SPD according to the situation that starts and runs of system；
The debugging host refers to reinforcement type server, in the server configured with mainboard, DDR4 Surface Mount memory, CPLD,
EEPROM, a BMC is placed on mainboard, and BMC has the management network independently of debugging host and provides out-of-band access, debugging
The Web client with web management interface is provided in host, which connects BMC；
Web server, power management module, power supply and channel switching module, firmware refresh module are configured in the BMC,
Configured with web interface module, the file upload function module communicated with Web page in middle Web server；Power management module connects
Meet above-mentioned web interface module and the CPLD independently of BMC；Power supply connected with channel switching module above-mentioned web interface module and solely
The switching circuit of BMC is stood on, the switching circuit is for switching Always voltage and Standby voltage；Firmware refresh module connects
SPD firmware that message in-coming part upload function module is sent simultaneously dumps in EEPROM；
In the step 1, first according to the memory SPD of memory parameters configuration specification and mainboard PCB characteristic design, then
It is stored in the debugging host for logging in BMC administration interface in the form of a file again；
BMC administration interface process is logged in the step 2 are as follows: debugging host first powers on, and system to be managed completes starting management
Network and it is available after log in the web management interface of BMC and select to store in step 1 with document form in the web management interface
Memory SPD firmware, issue update SPD firmware and enter the firmware update stage order；
The process of Standby power voltage supply is used in the step 3 are as follows:
The web interface module of BMC calls power management module to obtain main-board on-off state, if mainboard is in open state
Prompt user shuts down computer, and the web interface module of BMC calls power management module to send shutdown life after obtaining user and agreeing to
It enables；
The web interface module of BMC calls the power supply of power supply and channel switching module execution eeprom chip and I2C channel to cut
Move work, and the system electricity under default situations is made to be changed to the Standby voltage that BMC is used, and is changed to by CPU access EEPROM by BMC
Access EEPROM；
In step 4, after SPD firmware update, the web interface module of BMC calls power management module to open to mainboard transmission
Machine order；According to internal memory initialization when the starting shown in system serial ports and training type information, whether be able to enter system,
The operating condition of system decides whether to change SPD configuration after into system, and SPD debugging is completed if reaching design requirement, such as
Fruit meet design requirements, and return step one repeats, until reaching design requirement.
2. a kind of memory SPD adjustment method according to claim 1, which is characterized in that the BMC will by I2C bus
Firmware is written in EEPROM, i.e., is connected between firmware refresh module and EEPROM by I2C bus.
3. a kind of memory SPD adjustment method according to claim 1, which is characterized in that firmware, which is written to EEPROM, is
Refer to that the file upload function module of the Web server of BMC uploads SPD firmware, and be stored under a certain specified directory, then leads to again
The firmware refresh module for crossing BMC refreshes SPD firmware to EEPROM.
4. a kind of memory SPD adjustment method according to claim 1, which is characterized in that after SPD firmware update, also
The step of carrying out state recovery is needed, i.e. power supply and channel is switched to default connection under the control of power supply and channel switching module
System electricity is changed to Always voltage by mode.
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| CN201711215906.5A CN107797892B (en) | 2017-11-28 | 2017-11-28 | A kind of memory SPD adjustment method |
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| CN201711215906.5A CN107797892B (en) | 2017-11-28 | 2017-11-28 | A kind of memory SPD adjustment method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108763138A (en) * | 2018-04-03 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of method and system accessing multisystem by single serial ports |
| CN110045967B (en) * | 2019-04-03 | 2023-03-24 | 昆仑太科(北京)技术股份有限公司 | Serial graphical interface interaction method and device of firmware layer |
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| CN103077102A (en) * | 2011-10-25 | 2013-05-01 | 鸿富锦精密工业（深圳）有限公司 | Computer starting detection system |
| CN103377061A (en) * | 2012-04-27 | 2013-10-30 | 鸿富锦精密工业（深圳）有限公司 | Firmware updating management system and method |
| CN106055438A (en) * | 2016-05-27 | 2016-10-26 | 深圳市国鑫恒宇科技有限公司 | Method and system for rapidly locating anomaly of memory banks on mainboard |
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2017
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|---|---|---|---|---|
| CN102446146A (en) * | 2010-10-13 | 2012-05-09 | 鸿富锦精密工业（深圳）有限公司 | Server and method for avoiding bus collision |
| CN102855146A (en) * | 2011-06-30 | 2013-01-02 | 鸿富锦精密工业（深圳）有限公司 | Firmware updating system and method |
| CN103077102A (en) * | 2011-10-25 | 2013-05-01 | 鸿富锦精密工业（深圳）有限公司 | Computer starting detection system |
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Effective date of registration: 20191017 Address after: 250100 Ji'nan high tech Zone, Shandong, No. 1036 wave road Applicant after: Tidal Group Co., Ltd. Address before: 250100, Ji'nan province high tech Zone, Sun Village Branch Road, No. 2877, building, floor, building, on the first floor Applicant before: Ji'nan wave high and New Technology Investment Development Co., Ltd. |
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