CN107797441B

CN107797441B - The time-amplitude of low-jitter clock signal modulates numeric field representation method

Info

Publication number: CN107797441B
Application number: CN201610810646.5A
Authority: CN
Inventors: 宋茂忠; 宋纪康
Original assignee: Nanjing University of Aeronautics and Astronautics
Current assignee: Nanjing University of Aeronautics and Astronautics
Priority date: 2016-09-05
Filing date: 2016-09-05
Publication date: 2019-11-19
Anticipated expiration: 2036-09-05
Also published as: CN107797441A

Abstract

The invention discloses a kind of time-amplitudes of clock signal to modulate numeric field representation method, the clock that it is different from general waveform domain or sequential relationship to indicate, but pass through the data structure sequence of numeric field, to indicate the forward position arrival time in clock each period, afterwards along arrival time, positive half cycle length and negative half period length parameter, ahead of the curve and in the expression of the arrival time on rear edge, the score arrival time on clock signal forward position or rear edge is indicated using two fixed intervals sample magnitudes, convert the sample quantization of score arrival time to the quantization of sample amplitude, realize clock leading edge or after along arrival time time-amplitude modulation Serial No. indicate, it is generated for the number of low-jitter clock signal, transmission, synchronous and digital processing provides convenience.

Description

The time-amplitude of low-jitter clock signal modulates numeric field representation method

One, technical field

The invention belongs to Design of Signal and signal processing technology field, more particularly to the satellite handled using clock The method of the Designs of Digital System and signal processing such as ranging, communication and radar, is a kind of high-precision low-jitter clock when navigation, survey Signal generates and the new technology of processing.

Two, background technique

Clock signal is the digitized premise of all contemporary electronic systems, and without clock reference and driving, digital display circuit will It can not work.The effect of clock signal be with certain frequency or period, by forward position arrival time or after along arrival time come Digital system operation is driven, the characteristic sooner or later and system performance and reliability of multiple clock arrival times is closely related.When at present Clock signal is mainly described with waveform characteristic, portrays frequency and arrival time relationship by the relative timing of waveform.But in clock synchronization When clock signal carries out analysing in depth processing, waveform description is not easy to digital processing, and the sample quantization of clock signal is also very difficult. Although time interval measurement is likely to be breached several picoseconds of magnitude, the forward position arrival time that picosecond is obtained to clock signal is taken out Sample or expression, general method will have 10¹²The reference clock of Hz, it is very unrealistic.

Clock signal studies more prolonged frequency and stability characteristic, and jittering characteristic is mainly also to carry out from spectral domain It analyzes, the slight change in temporal properties or a cycle can only be portrayed by waveform domain.The forward position of waveform domain description is special Property be affected in transmission and radio wave propagation by channel, be not easy to digital modeling or digital processing.With high-frequency clock reference The shake for sample or carrying out clock and generate all uncontrollable forward position arrival time to clock signal, it is whole to digital display circuit The raising of performance brings difficulty.And the variation or shake of clock leading edge influence significantly the performance indicator of whole system.When to surveying System determines time difference method, determines range accuracy to navigation and radar signal, determines synchronization accuracy to signal of communication, therefore to mention The performance of high digital display circuit must start with from basic forward position arrival time characteristic.Therefore this patent provides a kind of low-jitter clock The time-amplitude of signal modulates numeric field representation method, provides possibility for the generation and processing of low-jitter clock.

Time-amplitude transfer or time-to-digital converter are universal after having compared in measurement in the time, and main purpose is to survey Single time interval is measured, except that the time-amplitude modulation of invention is to be modulated to a series of forward position arrival times In clock sampled sequence, arrival time is indicated using the amplitude of sampling samples.Arrival time number of the solution never on sampled point Word sampled representation problem.

Three, summary of the invention

1, goal of the invention

The object of the present invention is to provide it is a kind of can accurately reflect clock signal forward position or after along arrival time variation time Amplitude modulated digital domain mathematical notation method, solves low jitter or the clock signal mathematical description of controllable arrival time, number produce Raw and digital processing basic problem.

2, technical solution

In order to achieve the above object of the invention, the present invention includes the following steps:

(1) time-amplitude of clock signal pulse forward position arrival time modulates representation method

In order to solve to the waveform sampling for being clock signal under s (t), cannot collect clock leading edge or after along arrival time Temporal information problem, having invented with the amplitude ab in Fig. 1 indicates the time-amplitude modulator approach of forward position moment p point.If preceding Time along arrival time p from sampling instant a is ap=yT_S, T_SFor the sampled reference clock cycle, 0≤y < 1 then takes sampling sample This ab=-y, cd=1-y.In this way, any forward position arrival time can use the two neighboring sample magnitude value of equal interval sampling To indicate.The normalization amplitude length of ab just directly indicates forward position arrival time p point to sampling instant a T_SWhen normalized Between.The quantified precision of forward position arrival time translates into the quantified precision of amplitude of samples sample ab.It therefore, can be with using the present invention With more low-frequency benchmark sample sequence Precise Representation pulse front edge arrival time, the modulation of clock signal time-amplitude is realized Digital domain representation.

(2) the compressed data structure representation method of clock signal

If clock signal characteristic passes through a series of samplings after the one reference clock sequential sampling of a clock signal Value sequence provides, but information redundancy is more, and Yao Jinhang stored digital and treatment effeciency be not high, the present invention devise as it is next when The data structure in clock period:

Structure s_clock (i)={ n_positive, p_back, n_nagitive, y_leading }

Wherein i indicates i-th of clock cycle, and n_positive indicates+1 number that positive half cycle samples in this period, p_ Back indicates failing edge zero crossing to the time of previous sampling point moment, with normalization sampling clock cycle T_SIt indicates.n_ Nagitive is -1 number sampled in negative half period, is indicated with positive integer.Y_leading indicates the forward position moment in next period To the time of previous sampled point, with normalization sampling clock cycle T_SIt indicates.Such as s_clock (10)={ 3,0.2,4,0.6 }.

The representation method of clock signal first phase can also indicate with similar structures, such as:

Structure s_clock (0)={ n_positive, p_back, n_nagitive, y_leading }=0,0, 0,0.5 } or s_clock (0)={ 0,0,2,0.8 } or s_clock (0)={ 0,0.1,9,0.8 }.

(3) calculation method of parameters of the clock signal Serial No. of high-precision forward position arrival time

If the clock cycle to be generated is T₀, the sampled reference clock cycle is T_S, initial phase is that a cycle forward position is arrived It is the zero point of time shaft up to the moment, 0.5T has occurred in first sampled point_SPlace, then the first phase data structure of clock signal is

S_clock (0)={ n_positive, p_back, n_nagitive, y_leading }={ 0,0,0,0.5 }.

Since a cycle, subsequent clock data structure calculation method of parameters is as follows:

If (i)M is positive integer, 0≤x < 1；

(ii)

Fix (u) represents less than the maximum positive integer equal to u, y_leading (i)=y_leading (i-1)+x,

If y_leading (i) >=1, y_leading (i)=y_leading (i) -1,

And n_nagitive (i)=n_nagitive (i)+1；

(iii) p_back (i)=y_leading (i)+0.5x,

If p_back (i) >=1, p_back (i)=p_back (i) -1.

3, the device have the advantages that

Numeric field representation method is modulated using clock signal time-amplitude of the invention, relatively low reference clock can be used Sequence carrys out sampled clock signal, accurately reflects clock signal forward position with the clock signal data structure in each period or rear along arrival Moment changing rule solves clock signal mathematical description, number generation and the digital processing of low jitter or controllable arrival time Basic problem, to high-precision low-jitter clock signal generate and digital processing provider just.

Four, Detailed description of the invention

The time-amplitude modulation of the digital sample of Fig. 1 clock signal indicates figure.

The waveform diagram for the 1.023MHz clock that Fig. 2 10MHz clock sampling generates.

Five, specific embodiment

Embodiment one: ignore the simplification clock signal numerical method of failing edge

Many occasions are only concerned the rising edge time of clock, how to change without concern for failing edge, corresponding clock data Structure can simplify are as follows:

The first structure: s_clock (i)={ n_positive, 0, n_nagitive, y_leading }, i.e. p_back= 0, failing edge moment oversampled points；

Second of structure: s_clock (i)={ n_positive, p_back, n_nagitive, y_leading }, i.e. p_ Back=y_leading, i.e., within each clock cycle, forward position sample magnitude is equal along sample magnitude with after, the folding of zero crossing Negative, the variation characteristic antisymmetry of line slope one positive one.

The representation method of both structures can simplify failing edge parameter p_back calculating, but the clock positive half period generated With negative half-cycle asymmetry, clock signal averaging is not 0, and failing edge arrival time is not also in 0.5T₀Place.

Embodiment two: the generation algorithm of low sampling rate low-jitter clock signal

If clock frequency to be generated is 1.023MHz, sampled reference clock frequency is 10MHz, if with conventional sampling The 1.023MHz clock leading edge of method, generation will be uniformly distributed in [0,0.1 μ s], it is difficult to ranging when realizing high-precision survey. If generating the clock waveform of 10MHz in FPGA, then export by D/A, forward position precision is solely dependent upon with method of the invention The quantizing bit number of D/A and digital waveform.When 8 bit quantization, the 1.023MHz clock leading edge of generation will be at [0,0.00078 μ s] It is inside uniformly distributed, forward position precision improves 128 times.If forward position precision improves 215 times with 16 bit quantizations.

The algorithmic procedure of clock data structure parameter are as follows:

(2) s_clock (0)={ n_positive, p_back, n_nagitive, y_leading }={ 0,0,0,0.5 }；

The clock waveform figure of generation is shown in attached drawing 2.

Claims

1. a kind of time-amplitude of low-jitter clock signal modulates numeric field representation method, pass through the data structure sequence of numeric field To indicate the parameter in clock each period, which is characterized in that by data structure sequence, to indicate the forward position in clock each period Arrival time, after along arrival time, positive half cycle length and negative half period length parameter, the data structure parameter of adjacent periods can adopt Calculated with iterative algorithm, make clock generation, transmission, synchronization and processing can for this data structure parameter into Row.

2. the time-amplitude of low-jitter clock signal as described in claim 1 modulates numeric field representation method, which is characterized in that Ahead of the curve arrival time and after along the expression of arrival time, use time-amplitude modulator approach, by clock signal forward position or The score arrival time on edge is modulated on the sample magnitude of two adjacent spaces sampling afterwards, believes the broken line of sample sequence and clock Number zero crossing is overlapped, and converts the sample quantization of score arrival time to the quantization of sample amplitude, realize clock leading edge and after Along the high accuracy number domain representation of arrival time.