CN107785419A - A kind of fin formula field effect transistor and its manufacture method - Google Patents
A kind of fin formula field effect transistor and its manufacture method Download PDFInfo
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- CN107785419A CN107785419A CN201610726754.4A CN201610726754A CN107785419A CN 107785419 A CN107785419 A CN 107785419A CN 201610726754 A CN201610726754 A CN 201610726754A CN 107785419 A CN107785419 A CN 107785419A
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- 238000002360 preparation method Methods 0.000 claims abstract description 7
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of fin formula field effect transistor and preparation method thereof, and methods described includes：Semiconductor substrate is provided；The first separation layer is formed on the first area of the Semiconductor substrate；The second separation layer is formed on the second area of the Semiconductor substrate, the density of second separation layer is less than the density of first separation layer；First separation layer and second separation layer are etched, forms the first groove and second groove for defining fin, the width of the second groove is more than the width of the first groove；The first groove and second groove are filled, to form the first fin and the second fin.According to the manufacture method of fin formula field effect transistor proposed by the present invention, different in width and the fin of effective depth can be obtained.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of fin formula field effect transistor and its manufacturer
Method.
Background technology
The continuous diminution of dimensions of semiconductor devices is to promote the improved principal element of ic manufacturing technology.Due to adjustment
The limitation of the thickness of gate oxide layers and the junction depth of source/drain, it is difficult to which the planar MOSFET devices of routine are contracted into 32nm
Following technique, therefore, multiple gate field effect transistor is developed.
Typical multiple gate field effect transistor is fin formula field effect transistor (FinFET), and it causes the size of device more
Small, performance is higher.Fin formula field effect transistor includes the fin perpendicular to substrate, and conducting channel is formed in the fin, and fin
On piece and both sides, which surround, grid.Compared with traditional planar structure, fin formula field effect transistor realizes the work of fully- depleted
Pattern, gate electrode controls conducting channel from three sides of vertical fin structure, thus fin formula field effect transistor has more preferable raceway groove
Control ability and more preferable sub-threshold slope, smaller Leakage Current, smaller gate delay and bigger electricity can be provided
Flow driving force.
Although fin formula field effect transistor provides improved performance for planar structure field-effect transistor,
It is also to bring some design challenges.Specifically, conventional MOSFET is substantially unrestricted for device widths, and fin field is imitated
It is usually fixed to answer the width of transistor fin and height, therefore, for given transistor length, fin field effect crystal
The saturation current of pipe is fixed.However, in high performance integrated circuit, it is often necessary to which there is the crystal of different driving ability
Pipe, such as SRAM (static RAM) unit.SRAM is typically made up of electric it is necessary to have different drivings 6 MOS
Stream, to realize the optimum performance of sram cell.But for fin formula field effect transistor, it can only use and change fin in parallel
The method of quantity achieves the goal.
Therefore, it is necessary to propose a kind of manufacture method of fin formula field effect transistor, can obtain different in width with effectively
The fin of height.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of preparation method of new fin formula field effect transistor, bag
Include：
Semiconductor substrate is provided；
The first separation layer is formed on the first area of the Semiconductor substrate；
The second separation layer is formed on the second area of the Semiconductor substrate, the density of second separation layer is less than institute
State the first separation layer；
First separation layer and second separation layer are etched, forms the first groove and second groove for defining fin,
The width of the second groove is more than the first groove；
The first groove and second groove are filled, to form the first fin and the second fin.
Exemplarily, in addition to first separation layer and second separation layer are etched back to, make first fin and
Second fin exposes the step of predetermined effective depth, and the effective depth of second fin is more than the effective of first fin
Highly.
Exemplarily, the etch rate of second separation layer and polishing speed are more than the etching speed of first separation layer
Rate and polishing speed.
Exemplarily, the etch step include by using mask dry etching formed define fin first groove and
Second groove, and the width of the second groove is more than described the by first groove described in wet etching and second groove
The width of one groove.
Exemplarily, the forming method of first fin and the second fin is epitaxial growth method.
Exemplarily, formed after second separation layer, in addition to perform flatening process, make first separation layer
The step of staged height being formed with second separation layer.
Exemplarily, the flatening process is chemical mechanical polishing method.
Exemplarily, the mask that the etch step uses is mask stack.
Exemplarily, the mask stack includes spun-on carbon layer and dielectric anti reflective layer.
Exemplarily, the mask stack includes silicon anti-reflecting layer and bottom anti-reflection layer.
Exemplarily, the stand out of first fin and second fin is 3-5nm.
Exemplarily, the effective height diffrence of first fin and second fin is 50-200 angstroms.
Exemplarily, in addition on first fin and the second fin formed grid structure the step of.
Exemplarily, first separation layer and the second separation layer are oxide skin(coating).
The present invention also provides a kind of fin formula field effect transistor, it is characterised in that including：
Semiconductor substrate；
The first separation layer on the Semiconductor substrate first area, and on the semiconductor second area
The second separation layer, the height of second separation layer is less than the height of first separation layer；
The first fin kept apart by first separation layer and the second fin kept apart by second separation layer,
The width of first fin is less than second fin, the height that second fin is exposed to beyond second separation layer
The height being exposed to more than first fin beyond first separation layer.
Exemplarily, the density of second separation layer is less than the density of first separation layer.
Exemplarily, the etch rate of second separation layer and polishing speed are more than the etching speed of first separation layer
Rate and polishing speed.
Exemplarily, in addition to the grid structure that is formed on first fin and the second fin.
Exemplarily, the stand out of first fin and second fin is 3-5nm.
Exemplarily, the effective height diffrence of first fin and second fin is 50-200 angstroms.
Exemplarily, first separation layer and the second separation layer are oxide skin(coating).
Compared with the prior art, according to the manufacture method of fin formula field effect transistor proposed by the present invention, can obtain not
With width and the fin of effective depth.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is obtains respectively the step of implementation successively according to the preparation method of fin formula field effect transistor in the prior art
Device schematic cross sectional view.
Fig. 2 is flow chart the step of implementation successively according to the method for the present invention.
Fig. 3-Figure 11 is the schematic cross section of the device obtained respectively the step of implementation successively according to the method for the present invention
Figure；
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Fig. 1 is the method for using self-alignment type Dual graphing fabrication techniques fin formula field effect transistor in the prior art
Schematic diagram：Semiconductor substrate 101 is provided first, on the semiconductor substrate formed with hard mask 102；Described in selective etch
Semiconductor substrate 101 and the hard mask 102, to form fin, the fin both sides formed with shallow trench and its upper surface still
Covered with hard mask 102；Pad insulating layers 103 are formed on the shallow ridges groove sidewall and bottom, and the hard mask 102；
Separation layer 104 is filled in the shallow trench, the separation layer 104 covers the hard mask 102 at the top of the fin；Perform annealing
Processing；The hard mask 102 and part separation layer are removed using technique is etched back to, makes the fin exposure predetermined altitude.However,
Because the height of all fins with a polishing process all by being defined, the fin field effect prepared using this method is brilliant
All fins all have identical height in body pipe, and the width of fin also faces similar situation.
In order to solve the above problems, the invention provides a kind of preparation method of fin formula field effect transistor, including：
Semiconductor substrate is provided；
The first separation layer is formed on the first area of the Semiconductor substrate；
The second separation layer is formed on the second area of the Semiconductor substrate, the density of second separation layer is less than institute
State the density of the first separation layer；
First separation layer and second separation layer are etched, forms the first groove and second groove for defining fin,
The width of the second groove is more than the width of the first groove；
The first groove and second groove are filled, to form the first fin and the second fin.
Also include being etched back to first separation layer and second separation layer, the fin is exposed predetermined effective height
The step of spending, the effective depth of second fin are more than the effective depth of first fin.
The etch rate and polishing speed of second separation layer are more than etch rate and the polishing of first separation layer
Speed.
The etch step includes forming the first groove and second groove for defining fin by using mask dry etching,
And the width of the second groove is set to be more than the first groove by first groove described in wet etching and second groove
Width.
The forming method of the fin is epitaxial growth method.
Formed after second separation layer, in addition to perform flatening process, make first separation layer and described the
Two separation layers form the step of staged height.The flatening process is chemical mechanical polishing method.
The mask that the dry etch step uses is mask stack.The mask stack includes spun-on carbon layer and medium resists
Reflecting layer or including silicon anti-reflecting layer and bottom anti-reflection layer.
The stand out of first fin and second fin is 3-5nm.First fin and second fin
Effective height diffrence be 50-200 angstroms.
Also include on the fin formed grid structure the step of.
First separation layer and the second separation layer are oxide skin(coating).
Compared with the prior art, the present invention proposes the manufacture method of fin formula field effect transistor, can obtain different in width
With the fin of effective depth.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to explain this
Invent the technical scheme proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.[exemplary embodiment one]
The preparation method of the fin formula field effect transistor of an embodiment of the present invention is done in detail below with reference to Fig. 2~Figure 11
Thin description.
First, step 201 is performed, there is provided Semiconductor substrate 301.
Specifically, heretofore described Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, absolutely
Silicon (SOI) on edge body, silicon (SSOI) is laminated on insulator, is laminated SiGe (S-SiGeOI), germanium on insulator on insulator
Silicon (SiGeOI) and germanium on insulator (GeOI) etc..
Then, step 202 is performed, the first separation layer 302 is formed on the first area of the Semiconductor substrate 301, such as
Shown in Fig. 3.Exemplarily, the material of first separation layer 302 includes oxide, such as silica etc..First isolation
The formation process of layer 302 can be chemical vapor deposition, high-density plasma CVD, atomic layer deposition, plasma enhancing original
Sublayer deposit, pulsed laser deposition or other suitable methods, it is preferred that chemical vapour deposition technique.When Semiconductor substrate 301
Material when being silicon, the formation process of first separation layer 302 can also be thermal oxidation method.Then, as shown in figure 4, in institute
The hard mask layer that the first insulation surface forms patterning is stated, first separation layer 302 is etched, it is covered the semiconductor
The first area of substrate.
Then, step 203 is performed, as shown in figure 5, forming the second separation layer on the second area of the Semiconductor substrate
303, the density of second separation layer is less than the density of first separation layer 302.The formation work of second separation layer 303
Skill is similar with first separation layer.After second separation layer 303 is deposited, to first separation layer 302 with it is described
Second separation layer 303 carries out planarization process, and the flatening process is CMP (chemical mechanical polishing method).Exemplarily, use
The slurry of metal oxide particle carries out CMP, such as SiO2、Al2O3And CeO2Deng.Rotating speed of table from 30rpm to
In the range of 110rpm, downward force in the range of from 0.5psi to 5psi, slurry flow rate from 50 ml/mins to 500 milli
In the range of liter/min.Because the density of second insolated layer materials 303 is less than first separation layer 302, it polishes speed
Rate is less than first separation layer 302, and performing planarization, the first separation layer 302 and the second separation layer 303 can form ladder later
The height of formula.
Then, step 204 is performed, etches the separation layer 303 of the first separation layer 302 and second, is formed and defines fin
First groove 309 and second groove 310, the width of the second groove 310 are more than the width of the first groove 309.Due to
The staged height of separation layer can cause cycloid effect in photoetching process etc., influence lithographic results, thus in the present embodiment,
The separation layer is performed etching using the mask stack including anti-reflecting layer.In one embodiment, as shown in Figure 6 a, successively
Spun-on carbon layer 304 and dielectric anti reflective layer (DARC) 305 are formed on the surface of 302 and second separation layer of the first separation layer 303.
The spun-on carbon layer 304 may act as the planarization film formed in the region with step difference, anti-reflective film and and lower material
Paper has the mask of Etch selectivity.The spun-on carbon layer 304 preferably includes the polymer rich in carbon, and wherein carbon accounts for
85wt%~90wt% of total molecular weight.The darc layer 305 can be nitrogen-oxygen-silicon layer (SiON), and thickness can arrive for 20nm
60nm.Photoresist 306 is formed on the darc layer 305, the photoresist is exposed, developed, to form patterning
Photoresist.Using the photoresist of the patterning as mask, the anti-reflecting layer is etched, and carve by hard mask of the anti-reflecting layer
Erosion separation layer defines the first groove 309 and second groove 310 of fin, the first groove 309 and second groove 310 to be formed
Depth be 2000 angstroms to 3000 angstroms, as shown in Figure 7.
In another embodiment, as shown in Figure 6 b, successively in the table of 302 and second separation layer of the first separation layer 303
Face forms silicon anti-reflecting layer 307, bottom anti-reflection layer (BARC) 308 and photoresist layer 306.First in the first separation layer 302
And the second separation layer 303 surface spin coating, one layer of silicon anti-reflecting layer 307, such as silicon oxynitride or silicon nitride, then it is formed on one
Layer BARC308, such as polyimide or polysulfones.Exemplarily, by using the solution spin coating substrate comprising monomer and trigger
Polymerisation forms BARC, and the BARC of formation thickness is in the range of from 300 angstroms to 5000 angstroms.In 100 DEG C to 500 DEG C temperature
Toasted in the range of degree so that BARC is crosslinked.Photoresist 306 is formed on the BARC, the photoresist is exposed,
Development, to form the photoresist of patterning.Using the photoresist of the patterning as mask, the anti-reflecting layer is etched, and with institute
State anti-reflecting layer for hard mask etching separation layer with formed define fin first groove 309 and second groove 310, described first
The depth of groove 309 and second groove 310 is 2000 angstroms to 3000 angstroms, as shown in Figure 7.
Then, second step etching is carried out to the groove using wet etching, as shown in Figure 8.The wet etching uses
Solution include hydrofluoric acid solution, hydrofluoric acid solution etc..By the wet-etch rate of second insolated layer materials is more than institute
The first separation layer is stated, therefore the width of second groove 310 is more than the width of first groove 309 after wet etching.Exemplarily, institute
It is 3-5nm to state first groove and the difference of second groove width.
Then, step 205 is performed, as shown in figure 9, fill the first groove 309 and second groove 310, to form the
One fin 311 and the second fin 312.Specifically, epitaxially grown silicon or polysilicon in the trench, to fill the groove.
The silicon or polysilicon can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy and molecule
Beam epitaxy etc..Gas and/or Liquid precursor can be used in epitaxy technique.The fin can also be to pass through sige epitaxial deposition technique shape
Into SiGe (SiGe).In fin growth course by add impurity into the original material of epitaxy technique or then by from
Sub- injection technology addition impurity can doped semiconductor materials into the growth technique of semi-conducting material.Then, chemical machinery is implemented
(CMP) technique is polished to planarize the fin 312 of the first fin 311 and second.
Then, step 206 is performed, as shown in Figure 10, is etched back to first separation layer 302 and second separation layer
303, the fin 312 of the first fin 311 and second is exposed predetermined effective depth, effective height of second fin 312
Effective depth of the degree more than first fin 311.Because the thickness of first separation layer 302 is more than second separation layer
303 thickness, therefore the effective depth of first fin 311 is less than the effective depth of second fin 312.It is exemplary
The effective height diffrence of ground, first fin and second fin is 50-200 angstroms.The etch back process can be dry method
Etch process, wet etching process, other etch process or its combination.In this example, using plasma etching, source gas is etched
Body uses HBr, Cl2And O2Mixture, the flow velocity of source gas is in the range of from 5 ml/mins to 1000 ml/mins.Pressure
Power is in the range of 1 millitorr to 100 millitorrs.Radio frequency (RF) bias supply of etch process can be about 30W to about 400W.Another
In one embodiment, also the hydrofluoric acid (DHF) of dilution can be used to carry out etch-back to the separation layer.Exemplarily, the dilution
Hydrofluoric acid (DHF) concentration percent by volume be 1:50~1:1000.
Then, grid structure 313 is formed on the fin, as shown in figure 11.The grid structure 313 can include grid
Pole dielectric layer and gate electrode.Gate dielectric includes dielectric material such as silica, high-k dielectric material, other suitable dielectrics
Material or its composition.The example of high-k dielectric material includes HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO etc..Grid
Pole electrode include polysilicon and/or comprising Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN,
TaCN, TaC, TaSiN metal, other conductive materials, or its composition.Grid structure may include many other layers as covered
Layer, boundary layer, diffusion layer, barrier layer, hard mask layer or its combination.Pass through suitable technique such as deposition, lithographic patterning and erosion
Carving technology forms grid structure.Depositing operation such as chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD), ald
(ALD) etc..Lithographic patterning technique includes baking, photoresistance after light blockage coating (such as rotary coating), soft baking, mask alignment, exposure, exposure
Development, cleaning, dry (such as hard drying), other suitable techniques or its combination.Alternatively, can by other methods for example without
Mask lithography, electron beam write-in or ion beam write-in are implemented or replace photoetching exposure process.Etch process includes dry etching, wet
Method etches and/or other engraving methods.
It should be noted that the both ends that fin is additionally included in the present embodiment form low-doped source/drain (LDD), then
The step of forming source/drain (not shown) of heavy doping.It can also carry out last part technology (BEOL) processing.For example, it can pass through
Deposition and cmp form one layer of insulating materials on this structure, by photoresist mask and etching technics in insulating barrier
Middle formation contact hole, the contact hole is filled, form similar electric connection structure such as metal interconnection etc..
So far, the processing step that according to an exemplary embodiment of the present one method is implemented is completed.It is understood that
The present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include afterwards
Other desired step, it is included in the range of this implementation preparation method.
Compared with the prior art, the manufacture method of fin formula field effect transistor proposed by the present invention, different width can be obtained
Degree and the fin of effective depth.
[exemplary embodiment two]
Reference picture 11, it illustrated therein is the fin field effect crystal of the device obtained according to manufacture method provided by the invention
The schematic cross sectional view of pipe.Fin formula field effect transistor provided by the invention includes：Semiconductor substrate 301, the first separation layer
302, the second separation layer 303, the first fin 311, the second fin 312, grid structure 313.
Wherein, the Semiconductor substrate 301 can be at least one of following material being previously mentioned：On silicon, insulator
Silicon (SSOI) is laminated on silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).
First separation layer 302 is located at the first area in the Semiconductor substrate.Exemplarily, first isolation
The material of layer 302 includes oxide, such as silica etc..The formation process of first separation layer 302 can be chemical gaseous phase
Deposition, high-density plasma CVD, atomic layer deposition, plasma enhanced atomic layer deposit, pulsed laser deposition or other conjunctions
Suitable method, it is preferred that chemical vapour deposition technique.When the material of Semiconductor substrate 301 is silicon, first separation layer 302
Formation process can also be thermal oxidation method.
Second separation layer 303 is located at the second area in the Semiconductor substrate.Exemplarily, second isolation
The material of layer 303 includes oxide, such as silica etc., and its formation process is similar with first separation layer.Described second every
The density of layer material is less than first separation layer 302, and its etch rate and polishing speed are more than first separation layer
302, therefore after planarization process is performed, the thickness of second separation layer 303 is less than the thickness of first separation layer 302
Degree.
First fin 311 and second fin 312 are respectively formed in first separation layer 302 and described second
In separation layer 303.Specifically, dry etching and wet etching are first passed through respectively in first separation layer 302 and described second
The first groove 309 and second groove 310 for defining fin are formed in separation layer 303, due to the wet method of second separation layer 303
Etch rate is more than first separation layer 302, therefore the width of second groove 310 is more than first groove 309；Then using outer
Epitaxial growth fills the groove, to form the first fin 311 and the second fin 312, and carries out planarization process, makes described the
One fin 311 and the upper surface flush of the second fin 312；Then first separation layer 302 and second separation layer are etched back to
303, make the fin 312 of the first fin 311 and second exposure predetermined altitude.Because the width of the second groove 310 is more than
The first groove 309, thus the width of second fin 312 is more than first fin 311；Due to first fin
311 with the upper surface flush of second fin 312, and the thickness of first separation layer 302 is more than second separation layer
303, thus the effective depth of second fin 312 is more than first fin 311.First fin and second fin
The stand out of piece is 3-5nm, and the effective height diffrence of first fin and second fin is 50-200 angstroms.
The grid structure 313 include be formed on separation layer and fin, across fin gate dielectric layer and be formed at
Gate electrode on gate dielectric layer.Gate dielectric layer includes dielectric material such as silica, high-k dielectric material, other suitable dielectrics
Material or its composition.The example of high-k dielectric material includes HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO etc..Grid
Pole electrode include polysilicon and/or comprising Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN,
TaCN, TaC, TaSiN metal, other conductive materials, or its composition.Grid structure 313 may include that many other layers such as cover
Cap rock, boundary layer, diffusion layer, barrier layer, hard mask layer or its combination.By suitable technique as deposit, lithographic patterning and
Etch process forms grid structure 313.
Compared with the prior art, fin formula field effect transistor proposed by the present invention, there is different in width and effective depth
Fin.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (21)
- A kind of 1. preparation method of fin formula field effect transistor, it is characterised in that including：Semiconductor substrate is provided；The first separation layer is formed on the first area of the Semiconductor substrate；Form the second separation layer on the second area of the Semiconductor substrate, the density of second separation layer is less than described the The density of one separation layer；First separation layer and second separation layer are etched, forms the first groove and second groove for defining fin, it is described The width of second groove is more than the width of the first groove；The first groove and second groove are filled, to form the first fin and the second fin.
- 2. according to the method for claim 1, it is characterised in that also include being etched back to first separation layer and described second Separation layer, the step of making first fin and the second fin expose predetermined effective depth, effective height of second fin Effective depth of the degree more than first fin.
- 3. according to the method for claim 1, it is characterised in that the etch rate and polishing speed of second separation layer are big In the etch rate and polishing speed of first separation layer.
- 4. according to the method for claim 1, it is characterised in that the etch step is included by using mask dry etching The first groove and second groove for defining fin are formed, and is made by first groove described in wet etching and second groove described The width of second groove is more than the width of the first groove.
- 5. according to the method for claim 1, it is characterised in that the forming method of first fin and the second fin is outer Epitaxial growth.
- 6. according to the method for claim 1, it is characterised in that formed after second separation layer, in addition to performed flat Smooth chemical industry skill, make the step of first separation layer is with second separation layer formation staged height.
- 7. according to the method for claim 6, it is characterised in that the flatening process is chemical mechanical polishing method.
- 8. according to the method for claim 4, it is characterised in that the mask that the etch step uses is mask stack.
- 9. according to the method for claim 8, it is characterised in that the mask stack includes spun-on carbon layer and dielectric anti reflective Layer.
- 10. according to the method for claim 8, it is characterised in that the mask stack includes silicon anti-reflecting layer and bottom resists Reflecting layer.
- 11. according to the method for claim 1, it is characterised in that the stand out of first fin and second fin For 3-5nm.
- 12. according to the method for claim 2, it is characterised in that effective height of first fin and second fin Degree difference is 50-200 angstroms.
- 13. according to the method for claim 1, it is characterised in that also include the shape on first fin and the second fin The step of into grid structure.
- 14. according to the method for claim 1, it is characterised in that first separation layer and the second separation layer are oxidation Nitride layer.
- A kind of 15. fin formula field effect transistor prepared using one of claim 1-14 methods described, it is characterised in that bag Include：Semiconductor substrate；The first separation layer on the Semiconductor substrate first area, and on the semiconductor second area Two separation layers, the height of second separation layer are less than the height of first separation layer；The first fin kept apart by first separation layer and the second fin kept apart by second separation layer, it is described The width of first fin is less than second fin, and the height that second fin is exposed to beyond second separation layer is more than The height that first fin is exposed to beyond first separation layer.
- 16. fin formula field effect transistor according to claim 15, it is characterised in that the density of second separation layer is small In the density of first separation layer.
- 17. fin formula field effect transistor according to claim 15, it is characterised in that the etching speed of second separation layer Rate and polishing speed are more than the etch rate and polishing speed of first separation layer.
- 18. fin formula field effect transistor according to claim 15, it is characterised in that also include being formed at first fin Grid structure on piece and the second fin.
- 19. fin formula field effect transistor according to claim 15, it is characterised in that first fin and described second The stand out of fin is 3-5nm.
- 20. fin formula field effect transistor according to claim 15, it is characterised in that first fin and described second The effective height diffrence of fin is 50-200 angstroms.
- 21. fin formula field effect transistor according to claim 15, it is characterised in that first separation layer and second every Absciss layer is oxide skin(coating).
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| CN113972267A (en) * | 2020-07-24 | 2022-01-25 | 格芯(美国)集成电路科技有限公司 | Transistor with mixed source/drain region |
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