CN111403276A - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

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Publication number
CN111403276A
CN111403276A CN202010211618.8A CN202010211618A CN111403276A CN 111403276 A CN111403276 A CN 111403276A CN 202010211618 A CN202010211618 A CN 202010211618A CN 111403276 A CN111403276 A CN 111403276A
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CN
China
Prior art keywords
layer
material layer
etched
mask layer
graphical
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Pending
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CN202010211618.8A
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Chinese (zh)
Inventor
邵克坚
张大明
陈云
刘昭
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202010211618.8A priority Critical patent/CN111403276A/en
Publication of CN111403276A publication Critical patent/CN111403276A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

The invention provides a preparation method of a semiconductor structure, which comprises the following steps: providing a material layer to be etched; forming a first mask layer on the surface of the material layer to be etched; obtaining a first graphical mask layer comprising a graphical area, wherein the graphical area comprises a plurality of graphical structures which are arranged at intervals; forming a side wall material layer on the surface of the pattern structure, the bottom of the gap of the adjacent pattern structure and the surface of the first patterned mask layer; forming a second mask layer on the surface of the side wall material layer; obtaining a second graphical mask layer, wherein the second graphical mask layer comprises an opening; the opening is positioned outside the graphical region; etching the side wall material layer, the first graphical mask layer and the material layer to be etched based on the second graphical mask layer; removing the second graphical mask layer; and continuously etching the material layer to be etched to form a first groove and a second groove in the material layer to be etched. The invention can simplify the process steps, reduce the production cost and improve the production efficiency; the yield of the product can be ensured.

Description

Method for manufacturing semiconductor structure
Technical Field
The invention belongs to the technical field of integrated circuit design and manufacture, and particularly relates to a preparation method of a semiconductor structure.
Background
In the prior art, a pattern doubling process is generally adopted for obtaining a pattern structure with smaller size, and generally comprises the following steps of forming a patterned mask layer with a plurality of pattern structures on the surface of a material layer to be etched, forming a low-temperature hydrogen-rich oxide layer on the surface of the obtained structure by adopting an atomic layer deposition (A L D) process to serve as a side wall material layer, forming a gap between the side wall material layers between adjacent pattern structures, etching the side wall material layer to remove the side wall material layer positioned at the top of the side wall material layer and at the bottom of the gap to form a side wall structure, removing the patterned mask layer, and etching the material layer to be etched on the basis of the side wall structure to form a groove in the material layer to be etched.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for fabricating a semiconductor structure, which solves the above-mentioned problems of the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
providing a material layer to be etched;
forming a first mask layer on the surface of the material layer to be etched;
performing graphical processing on a partial area of the first mask layer to obtain a first graphical mask layer comprising a graphical area, wherein the graphical area comprises a plurality of graphical structures which are arranged at intervals;
forming a side wall material layer on the surface of the pattern structure, the bottom of the gap adjacent to the pattern structure and the surface of the first patterned mask layer;
forming a second mask layer on the surface of the side wall material layer, wherein the second mask layer fills gaps between adjacent pattern structures and covers the side wall material layer;
carrying out graphical processing on the second mask layer to obtain a second graphical mask layer, wherein the second graphical mask layer is positioned outside the graphical area; the second patterned mask layer comprises an opening, the shape and the position of the second groove are defined by the first opening, and the side wall material layer is exposed;
etching the side wall material layer, the first graphical mask layer and the material layer to be etched based on the second graphical mask layer; and
removing the second graphical mask layer; and continuously etching the material layer to be etched to form a first groove and a second groove in the material layer to be etched.
Optionally, the step of removing the patterned mask structure is further included after the first trench and the second trench are formed.
Optionally, the forming the first mask layer on the surface of the material layer to be etched includes the following steps:
forming a spin-coating carbon layer on the surface of the material layer to be etched; and
and forming a silicon oxynitride layer on the surface of the spin-coating carbon layer.
Optionally, the material layer to be etched includes a first material layer to be etched and a second material layer to be etched, the second material layer to be etched is located on the surface of the first material layer to be etched, and the first mask layer is formed on the surface of the second material layer to be etched.
Optionally, the step of removing the second material layer to be etched is further included after the material layer to be etched is etched.
Optionally, the thickness of the side wall material layer is smaller than half of the width of a gap between adjacent pattern structures and smaller than the height of the pattern structures, so as to ensure that a groove is formed between the adjacent pattern structures after the side wall material layer is formed; the width of the pattern structure is equal to the width of the groove.
Optionally, the step of performing patterning on the partial region of the first mask layer includes:
forming a first photoresist layer on the surface of the first mask layer;
exposing and developing the first photoresist layer to obtain a first graphical photoresist layer, wherein a photoresist graph defining the first graph structure is formed in the first graphical photoresist layer;
and etching the first mask layer based on the first patterned photoresist layer to form the first patterned mask layer.
Optionally, the step of removing the first patterned photoresist layer is further included after the first patterned mask layer is formed.
Optionally, the step of performing patterning on the second mask layer includes:
forming a second photoresist layer on the surface of the second mask layer;
exposing and developing the second photoresist layer to obtain a second patterned photoresist layer, wherein an opening pattern defining the opening is formed in the second patterned photoresist layer;
and etching the second mask layer based on the second patterned photoresist layer to form the second patterned mask layer.
Optionally, the step of removing the second patterned photoresist layer is further included after the second patterned mask layer is formed.
Optionally, the width of the first trench is greater than the width of the second trench.
Optionally, the second trench comprises a bit line trench or a word line trench.
As described above, the method for manufacturing a semiconductor structure of the present invention has the following advantages:
the preparation method of the semiconductor structure can simplify the process steps, reduce the production cost and improve the production efficiency (the WPH (Wafer per hour) can be improved by about 60%); the risk of suffering from the defects of the process window can be reduced, and the yield of products is ensured; the resulting trenches in the semiconductor structure meet the performance requirements of either the bitline trenches or the wordline trenches.
Drawings
Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to the present invention.
Fig. 2 to 15 are schematic cross-sectional structures of structures obtained in the steps of the method for manufacturing a semiconductor structure according to the present invention.
Description of the element reference numerals
10 layer of material to be etched
101 first layer of material to be etched
102 second layer of material to be etched
11 first mask layer
111 spin-on carbon layer
112 silicon oxynitride layer
12 first patterned mask layer
121 pattern structure
13 side wall material layer
14 second mask layer
141 first layer of masking material
142 layer of a second masking material
15 second patterned mask layer
151 opening
16 first trench
17 second trench
20 first patterned photoresist layer
201 photoresist pattern
21 second patterned photoresist layer
211 first opening pattern
212 second opening pattern
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1, the present embodiment further provides a method for manufacturing a semiconductor structure, where the method for manufacturing a semiconductor structure includes the following steps:
s11: providing a material layer to be etched;
s12: forming a first mask layer on the surface of the material layer to be etched;
s13: performing graphical processing on a partial area of the first mask layer to obtain a first graphical mask layer comprising a graphical area, wherein the graphical area comprises a plurality of graphical structures which are arranged at intervals;
s14: forming a side wall material layer on the surface of the pattern structure, the bottom of the gap adjacent to the pattern structure and the surface of the first patterned mask layer;
s15: forming a second mask layer on the surface of the side wall material layer, wherein the second mask layer fills gaps between adjacent pattern structures and covers the side wall material layer;
s16: carrying out graphical processing on the second mask layer to obtain a second graphical mask layer, wherein the second graphical mask layer is positioned outside the graphical area; the second patterned mask layer comprises an opening, the shape and the position of the second groove are defined by the first opening, and the side wall material layer is exposed;
s17: etching the side wall material layer, the first graphical mask layer and the material layer to be etched based on the second graphical mask layer;
s18: removing the second graphical mask layer; and continuously etching the material layer to be etched to form the first groove and the second groove in the material layer to be etched.
As an example, in step S11, the material layer to be etched 10 provided may be formed on a substrate (not shown); as shown in fig. 2, the material layer to be etched 10 may include a first material layer to be etched 101 and a second material layer to be etched 102, where the second material layer to be etched 102 is located on a surface of the first material layer to be etched 101 away from the substrate; specifically, the first material layer to be etched 101 may include, but is not limited to, a silicon oxide layer, and the second material layer to be etched 102 may include, but is not limited to, a polysilicon layer.
In one example, step S12 may include the steps of:
s121: forming a spin-on carbon layer 111 on the surface of the material layer to be etched 10, specifically, forming the spin-on carbon layer 111 on the surface of the second material layer to be etched 102; and
s122: forming a silicon oxynitride layer 112 on the surface of the spin-on carbon layer 111, as shown in fig. 3; the silicon oxynitride layer 112 and the spun-on carbon layer 111 together constitute the first mask layer 11.
In one example, step S13 may include the steps of:
s131: forming a first photoresist layer (not labeled) on the surface of the first mask layer 11; specifically, the first photoresist layer may be formed by, but not limited to, a spin coating process;
s132: exposing and developing the first photoresist layer to form a first patterned photoresist layer 20, where the first patterned photoresist layer 20 includes a plurality of photoresist patterns 201, as shown in fig. 4; the photoresist pattern 201 defines the shape and position of a subsequently formed pattern structure;
s133: etching the first mask layer 11 based on the first patterned photoresist layer 20 to form the first patterned mask layer 12, as shown in fig. 5;
s134: removing the first patterned photoresist layer 20; specifically, the first patterned photoresist layer 20 may be removed using, but not limited to, an ashing process.
In an example, in step S14, the sidewall material layer 13 may be formed by, but not limited to, an atomic deposition process, as shown in fig. 6; the side wall material layer 13 may include, but is not limited to, a silicon oxide layer. Specifically, the thickness of the sidewall material layer 13 is smaller than half of the width of the gap between the adjacent pattern structures 121 and smaller than the height of the pattern structure 12, so as to ensure that after the sidewall material layer 13 is formed, a groove (not shown) is formed between the adjacent pattern structures 121; preferably, the width of the pattern structure 121 is equal to the width of the groove.
In one example, in step S15, the second mask layer 14 can be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. Specifically, the second mask layer 14 may include a first mask material layer 141 and a second mask material layer 142, where the first mask material layer 141 is located on the surface of the sidewall material layer 13, and the second mask material layer 142 is located on the surface of the first mask material layer 142, as shown in fig. 7. The first mask material layer 141 may include, but is not limited to, a silicon nitride layer, and the second mask material layer 142 may include, but is not limited to, a silicon oxide layer.
In one example, step S16 may include the steps of:
s161: forming a second photoresist layer (not shown) on the surface of the second mask layer 14;
s162: exposing and developing the second photoresist layer to obtain a second patterned photoresist layer 21, wherein an opening pattern 211 defining the opening is formed in the second patterned photoresist layer 21, as shown in fig. 8;
s163: etching the second mask layer 14 based on the second patterned photoresist layer 21 to form the second patterned mask layer 15, as shown in fig. 9; it should be noted that, after the etching in this step, the portions of the second mask layer 14 located in the patterned region are all removed, as shown in fig. 9
S164: the second patterned photoresist layer 21 is removed, and particularly, the second patterned photoresist layer 21 can be removed by, but not limited to, an ashing process.
In an example, in step S17, the sidewall material layer 13, the first patterned mask layer 12, and the material layer to be etched 10 may be etched by, but not limited to, a dry etching process. Specifically, step S17 may specifically be:
the sidewall material layer 13 and the silicon oxynitride layer 112 are etched based on the second patterned mask layer 15, the opening 151 extends downward and penetrates through the sidewall material layer 13 and the silicon oxynitride layer 112, the sidewall material layer 13 on the top of the pattern structure 121, the silicon oxynitride layer 112 on the top of the pattern structure 121, and the sidewall material layer 13 between the pattern structures 121 are all removed, and the second material layer 102 to be etched in the patterned region is partially removed, as shown in fig. 10.
In one example, step S18 may include the steps of:
s181: removing the second masking material layer 142, as shown in fig. 10;
s182: removing the first mask material layer 141, and etching the spun-on carbon layer 111, in which the spun-on carbon layer 111 located in the patterned region is removed after the etching, and the opening corresponding to the opening 151 penetrates through the spun-on carbon layer 111 remaining outside the patterned region, as shown in fig. 11;
s183: continuing to etch the material layer to be etched 10 until the second material layer to be etched 102 is etched through, as shown in fig. 12;
s184: removing the sidewall material layer 13 remaining outside the patterned region and the silicon oxynitride layer 112 remaining outside the patterned region, and continuing to etch the material layer to be etched 10 until the first trench 16 and the second trench 17 are formed in the first material layer to be etched 101, as shown in fig. 13;
s185: the spun-on carbon layer 111 remaining outside the pattern area is removed, as shown in fig. 14.
In one example, the step of removing the second material layer to be etched 102 is further included after removing the spin-on carbon layer 111 remaining outside the pattern region. Specifically, an etching process or a chemical mechanical polishing process may be used to remove the second material layer to be etched 102, as shown in fig. 15.
In one example, the width of the first trench 17 is greater than the width 18 of the second trench.
In one example, the second trenches 18 include bit line trenches or word line trenches.
As described above, the method for manufacturing a semiconductor structure of the present invention includes the steps of: providing a material layer to be etched; forming a first mask layer on the surface of the material layer to be etched; performing graphical processing on a partial area of the first mask layer to obtain a first graphical mask layer comprising a graphical area, wherein the graphical area comprises a plurality of graphical structures which are arranged at intervals; forming a side wall material layer on the surface of the pattern structure, the bottom of the gap adjacent to the pattern structure and the surface of the first patterned mask layer; forming a second mask layer on the surface of the side wall material layer, wherein the second mask layer fills gaps between adjacent pattern structures and covers the side wall material layer; carrying out graphical processing on the second mask layer to obtain a second graphical mask layer, wherein the second graphical mask layer is positioned outside the graphical area; the second patterned mask layer comprises an opening, the shape and the position of the second groove are defined by the first opening, and the side wall material layer is exposed; etching the side wall material layer, the first graphical mask layer and the material layer to be etched based on the second graphical mask layer; removing the second graphical mask layer; and continuously etching the material layer to be etched to form the first groove and the second groove in the material layer to be etched. The preparation method of the semiconductor structure can simplify the process steps, reduce the production cost and improve the production efficiency (the WPH (wafer hour) can be improved by about 60%); the risk of suffering from the defects of the process window can be reduced, and the yield of products is ensured; the resulting trenches in the semiconductor structure meet the performance requirements of either the bitline trenches or the wordline trenches.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A method for manufacturing a semiconductor structure, comprising the steps of:
providing a material layer to be etched;
forming a first mask layer on the surface of the material layer to be etched;
performing graphical processing on a partial area of the first mask layer to obtain a first graphical mask layer comprising a graphical area, wherein the graphical area comprises a plurality of graphical structures which are arranged at intervals;
forming a side wall material layer on the surface of the pattern structure, the bottom of the gap adjacent to the pattern structure and the surface of the first patterned mask layer;
forming a second mask layer on the surface of the side wall material layer, wherein the second mask layer fills gaps between adjacent pattern structures and covers the side wall material layer;
carrying out graphical processing on the second mask layer to obtain a second graphical mask layer, wherein the second graphical mask layer is positioned outside the graphical area; the second patterned mask layer comprises an opening, the shape and the position of the second groove are defined by the first opening, and the side wall material layer is exposed;
etching the side wall material layer, the first graphical mask layer and the material layer to be etched based on the second graphical mask layer; and
removing the second graphical mask layer; and continuously etching the material layer to be etched to form a first groove and a second groove in the material layer to be etched.
2. The method of claim 1, further comprising removing the patterned mask structure after forming the first trench and the second trench.
3. The method of claim 1, wherein: forming the first mask layer on the surface of the material layer to be etched comprises the following steps:
forming a spin-coating carbon layer on the surface of the material layer to be etched; and
and forming a silicon oxynitride layer on the surface of the spin-coating carbon layer.
4. The method of claim 1, wherein: the material layer to be etched comprises a first material layer to be etched and a second material layer to be etched, the second material layer to be etched is located on the surface of the first material layer to be etched, and the first mask layer is formed on the surface of the second material layer to be etched.
5. The method of claim 4, wherein: and removing the second material layer to be etched after the material layer to be etched is etched.
6. The method of claim 1, wherein: the thickness of the side wall material layer is smaller than half of the width of a gap between the adjacent graphic structures and smaller than the height of the graphic structures, so that a groove is formed between the adjacent graphic structures after the side wall material layer is formed; the width of the pattern structure is equal to the width of the groove.
7. The method of claim 1, wherein: the step of carrying out graphical processing on the partial area of the first mask layer comprises the following steps:
forming a first photoresist layer on the surface of the first mask layer;
exposing and developing the first photoresist layer to obtain a first graphical photoresist layer, wherein a photoresist graph defining the first graph structure is formed in the first graphical photoresist layer;
and etching the first mask layer based on the first patterned photoresist layer to form the first patterned mask layer.
8. The method of claim 7, further comprising removing the first patterned photoresist layer after the forming of the first patterned mask layer.
9. The method of claim 1, wherein: the step of carrying out graphical processing on the second mask layer comprises the following steps:
forming a second photoresist layer on the surface of the second mask layer;
exposing and developing the second photoresist layer to obtain a second patterned photoresist layer, wherein an opening pattern defining the opening is formed in the second patterned photoresist layer;
and etching the second mask layer based on the second patterned photoresist layer to form the second patterned mask layer.
10. The method of claim 9, further comprising removing the second patterned photoresist layer after forming the second patterned mask layer.
11. The method of claim 1, wherein a width of the first trench is greater than a width of the second trench.
12. The method of any one of claims 1-11, wherein the second trench comprises a bitline trench or a wordline trench.
CN202010211618.8A 2020-03-24 2020-03-24 Method for manufacturing semiconductor structure Pending CN111403276A (en)

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WO2022160568A1 (en) * 2021-01-29 2022-08-04 长鑫存储技术有限公司 Method for preparing memory
US11956941B2 (en) 2021-01-29 2024-04-09 Changxin Memory Technologies, Inc. Manufacturing method for memory
CN113013076A (en) * 2021-02-25 2021-06-22 长鑫存储技术有限公司 Method for forming overlay mark and semiconductor structure
CN113013076B (en) * 2021-02-25 2022-06-10 长鑫存储技术有限公司 Method for forming overlay mark and semiconductor structure
CN113643966A (en) * 2021-08-09 2021-11-12 长鑫存储技术有限公司 Mask structure and preparation method thereof and preparation method of semiconductor structure
CN113643966B (en) * 2021-08-09 2023-05-02 长鑫存储技术有限公司 Mask structure and preparation method thereof and preparation method of semiconductor structure

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Application publication date: 20200710