CN107768448B - Charge trapping type memory device with bidirectional ladder energy band memory oxide and preparation method thereof - Google Patents
Charge trapping type memory device with bidirectional ladder energy band memory oxide and preparation method thereof Download PDFInfo
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- GIRKRMUMWJFNRI-UHFFFAOYSA-N tris(dimethylamino)silicon Chemical group CN(C)[Si](N(C)C)N(C)C GIRKRMUMWJFNRI-UHFFFAOYSA-N 0.000 claims description 3
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
Abstract
The invention discloses a preparation method of a charge trapping type memory device with a bidirectional ladder energy band memory oxide, which prepares a tunneling oxide, a laminated memory oxide and a blocking oxide by an atomic layer deposition system. The stacked memory oxide comprises nine films sequentially grown, wherein each film is [ M ]]m[SiO2]n[M]m[SiO2]nM may be La2O3、ZrO2、HfO2Any one of m and n represents the deposition cycle number in the atomic layer deposition process, and the growth sequence is as follows: first M cycles of M followed by n cycles of SiO2Regrowing M cycles of M and finally n cycles of SiO2And m + n is 5. Starting from the tunnel oxide, the sequence is first layer m is 1, second layer m is 2, third layer m is 3, fourth layer m is 4, fifth layer m is 5, sixth layer m is 4, seventh layer m is 3, eighth layer m is 2, and ninth layer m is 1. By adjusting each layer M and SiO in the stacked memory oxide2The growth sequence and the number of deposition cycles to form a bidirectional step energy band.
Description
Technical Field
The invention belongs to the field of microelectronic devices and materials thereof, and relates to a bidirectional ladder energy band storage oxide and application thereof in a nonvolatile memory device.
Background
As the feature size of conventional floating gate type nonvolatile memories gradually approaches its physical limit, finding new memory structures becomes a hot spot of research, mainly focusing on finding solid-state memories with low power consumption and high storage density, such as memory devices that can be used on cameras, mobile phones, and computers. Among the many non-volatile memory candidates, charge storage devices of the silicon-oxide-nitride-oxide-polysilicon (SONOS) type are widely studied as the most promising memory structure, with the oxide next to the silicon as the tunneling oxide, the nitride as the storage layer and the oxide next to the polysilicon electrode as the blocking oxide. However, conventional nitride (Si)3N4) The density of trap states faced by the storage layer is not high, the charge storage density is lower and shallowThe energy level defect state density is high, and the like, so that the stored charge is easy to lose. There is a need for developing next generation non-volatile memory devices based on conventional SONOS-type memory structures. High dielectric constant (high-k) material instead of Si3N4As a memory oxide, not only can a high electric field be generated through the tunnel oxide and a greater defect state density, but also a corrected Fowler-Nordheim tunneling occurs due to a smaller conduction band offset with the silicon substrate.
Among the solutions, increasing the density of deep-level defect states in the device and changing the storage oxide band structure have been the focus of research by workers in the semiconductor device field. From the viewpoint of improving defect state density: in charge trap memory devices, charge is mainly trapped by defect states in the memory oxide, the higher the density of defect states, the higher the memory density, and the higher the density of defect states at grain boundaries inside the material, the higher the density of defect states at other locations. From the viewpoint of changing the energy band of the storage oxide: in the data retention state, the charge trapped by the storage oxide should have a higher band offset in both the direction of the tunnel oxide and the blocking oxide; the distance that charges in the conduction band of the substrate reach the conduction band of the storage oxide in the written or erased state of the device should be small. In view of the above, we have invented a charge trapping memory device with a bidirectional ladder energy band storage oxide and a method for fabricating the same. The method comprises the steps of sequentially growing a tunneling oxide, a laminated storage oxide and a blocking oxide on a silicon substrate by means of an atomic layer deposition system method, wherein the laminated storage oxide is divided into nine layers, controlling the growth sequence and the deposition cycle times of components in each layer in the storage oxide by the atomic layer deposition system, changing the forbidden bandwidth of each layer, forming a bidirectional ladder energy band structure directing the storage oxide to the tunneling oxide and the blocking oxide, achieving the purposes of improving the defect state density of a device and changing the energy band of the storage oxide, and further achieving the improvement of the storage performance of the device.
Disclosure of Invention
The invention provides a preparation method of a charge trapping memory device with a bidirectional ladder energy band memory oxide, which is simple to operate and easy to control the bidirectional ladder energy band in the memory oxide.
The invention also provides the application of the charge trapping memory device obtained by the preparation method in information storage and nonvolatile semiconductor memory devices.
The preparation method of the charge trapping memory device with the bidirectional ladder energy band storage oxide comprises the following steps:
a) placing the substrate material cleaned by acetone and hydrofluoric acid on a tray of a cavity of an atomic layer deposition system, and then growing a layer of SiO on the surface of the substrate by using the atomic layer deposition system2As a tunneling oxide, wherein SiO2The precursor is tri (dimethylamino) silane (SiH [ N (CH) ]3)2]3)，H2O is taken as an oxygen source, the temperature in the deposition chamber is 300 +/-25 ℃, and the temperature is shown in figure 1 (a);
b) growing a laminated film structure on the surface of the tunneling oxide by utilizing an atomic layer deposition system to serve as a storage oxide, wherein the laminated structure comprises nine films which are sequentially grown, and the growth sequence of each film is [ M [ ]]m[SiO2]n[M]m[SiO2]nWherein M may be La2O3、ZrO2、HfO2Any one of m and n represents the number of pulse cycles in the atomic layer deposition process, and the sequence is as follows: first M cycles of M followed by n cycles of SiO2Regrowing M cycles of M and finally n cycles of SiO2(ii) a Different M, precursors can be in tris [ N, N-bis (trimethylsilyl) amine]Lanthanum (La (N (Si (CH))3)3)2)3) Zirconium tetrachloride (ZrCl)4) Hafnium tetrachloride (HfCl)4) Of medium selection, SiO2The precursor is tri (dimethylamino) silane (SiH [ N (CH) ]3)2]3)，H2O is taken as an oxygen source; nine films grown sequentially, where M and n have different values, such that M + n is 5, are the first layer [ M ] in sequence starting immediately after the tunnel oxide]1[SiO2]4[M]1[SiO2]4M1, n 4, second layer [ M]2[SiO2]3[M]2[SiO2]3M2, n 3, a third layer [ M ═ M]3[SiO2]2[M]3[SiO2]2M3, n 2, a fourth layer [ M ═ M]4[SiO2]1[M]4[SiO2]1M is 4, n is 1, fifth layer [ M ═ M]5[SiO2]0[M]5[SiO2]0M is 5, n is 0, sixth layer [ M]4[SiO2]1[M]4[SiO2]1M4, n 1, seventh layer [ M ═ M]3[SiO2]2[M]3[SiO2]2M is 3, n is 2, eighth layer [ M]2[SiO2]3[M]2[SiO2]3M2, n 3, and a ninth layer [ M]1[SiO2]4[M]1[SiO2]4M is 1, n is 4, as shown in fig. 1 (b);
c) growing a layer of SiO on the surface of the previously formed stacked memory oxide by utilizing an atomic layer deposition system2As the barrier oxide, the precursor is tris (dimethylamino) silane (SiH [ N (CH) ]3)2]3)，H2O is taken as an oxygen source, the temperature in a deposition cavity is 300 +/-25 ℃, and the prepared structure is subjected to in-situ heat preservation for 2-3 hours, as shown in figure 1 (c);
d) deposition on SiO by pulsed laser2Growing a layer of TaN on the surface of the barrier oxide to serve as an upper electrode, and smearing silver colloid on the back of the silicon substrate to serve as a lower electrode, as shown in FIG. 1 (d);
as a general knowledge, SiO is used for the purpose of improving the performance of a memory device and reducing the size of the device2The thickness of the tunneling oxide is controlled to be 1-4nm and SiO2The thickness of the barrier oxide should be controlled to be 15-20nm, and the thickness of the TaN upper electrode should be controlled to be 100-200 nm; the substrate material can be selected from GaAs, GaN, Ge, Si, preferably Si.
The charge trapping memory device comprises sequentially connected tunneling oxide, storage oxide and blocking oxide, and is prepared by using a laminated structure with nine layers of films as the storage oxidePreparing M and SiO in each film2The number of deposition cycles of, and the selection of M and SiO2Compared with the prior art, has smaller forbidden band width (La)2O3、ZrO2、HfO2And SiO2With band gaps of 4.3eV, 7.8eV, 5.eV 7 and 8.9eV, respectively). Therefore, according to the manufacturing process, the deposition cycle number of M is gradually increased from the first layer to the fifth layer, and SiO2The number of deposition cycles of (A) is gradually reduced, from the fifth layer to the ninth layer, the number of deposition cycles of (M) is gradually reduced, and SiO is added2The deposition cycle times are gradually increased, the fifth layer is a pure M film, and the forbidden bandwidth of M is less than that of SiO2Therefore, after the atoms are fully diffused, the SiO layer is arranged along each layer in the directions of the fifth layer pointing to the tunneling oxide and the barrier oxide2The number of deposition cycles is increased, and the forbidden bandwidth of each layer of thin film is gradually increased to form a step-shaped energy band structure, i.e. a bidirectional step energy band of the stacked memory oxide is formed, as shown in fig. 2.
The application of the charge trapping memory device with the bidirectional ladder energy band storage oxide obtained by the preparation method in programming speed can be explained by the energy band structure of the device in a writing state, as shown in fig. 3:
a forward voltage is applied to the TaN grid of the device structure, and an electric field points to the direction of the substrate, so that the energy band of the device is inclined. Electrons travel through the tunnel oxide and into the storage oxide under the influence of an electric field force. For a device with stacked memory oxides, as shown in fig. 3(a), the device has a bidirectional staircase energy band, such that the distance that electrons reach the conduction band of the memory oxide is smaller than that of a single oxide memory layer (as shown in fig. 3(b)), thereby increasing the programming speed of the device; in addition, under the action of the electric field force, electrons have a tendency to continue moving toward the blocking oxide. However, due to the existence of the bi-directional step energy band, electrons need to pass through the stacked structure to reach the blocking oxide, so that the probability of leakage of electrons in the direction of the blocking oxide is reduced, and the writing speed of the device is further improved, as shown in fig. 3 (a). While electrons can reach the blocking oxide without passing through the stack structure due to the single storage oxide band, the probability of electron leakage is increased, and the writing speed is reduced, as shown in fig. 3 (b).
The application of the charge trap memory device with the bidirectional ladder energy band storage oxide obtained by the preparation method in the data holding state can be explained by the energy band structure of the device in the data holding state, as shown in fig. 4:
the device adopts the laminated oxide as a storage structure, and a large number of deep-level defect states exist in the interfaces between layers. Electrons entering the storage structure are captured by the defects at the interface, so that the storage density of the device is improved; in addition, the charge loss mechanism of the charge storage device in the data retention state is two steps of thermally exciting charges into the conduction band of the storage structure and then through the tunnel oxide to the conduction band of the substrate. As can be seen from fig. 4(a), due to the adoption of the stacked structure, in the process of leakage to the tunnel oxide after the charges trapped by the interface defect state are excited into the conduction band, the thickness of the passing film is different, the distance which needs to be passed is larger as the trapped charges are closer to the middle of the stacked structure, and the distance which needs to be passed by the charges stored at other interfaces back to the substrate conduction band is larger than the thickness of the tunnel oxide except the charges at the first layer interface in the stacked structure, so that the data retention capability of the device is improved. The leakage of the stored charge to the blocking layer is performed in the same manner as described above. The single oxide (M) film is used as a storage device of the storage oxide, the storage oxide has lower defect state density, and the charge storage density is difficult to improve; in addition, the storage oxide has a uniform forbidden bandwidth, and charges only need to pass through the tunneling oxide in the process of leaking to the tunneling layer after being thermally excited into the conduction band of the storage oxide, so that the data retention performance is poorer than that of the stacked storage oxide, as shown in fig. 4 (b).
FIG. 5 shows a memory oxide [ La ] having a stacked structure2O3]m[SiO2]n[La2O3]m[SiO2]nAnd a single storage oxide La2O3The charge trapping memory device of (2) at an operating voltage of +8V, a charge storage window of different writing times. As can be seen from the figure, the memory oxide having a stacked structure[La2O3]m[SiO2]n[La2O3]m[SiO2]nThe device of (3) has a maximum charge storage window at the same operating time. The main reason is that the device of the stacked memory oxide has a bidirectional step energy band, and the distance from the electrons to the conduction band of the memory oxide is smaller than that of a single oxide memory layer, so that the programming speed of the device is improved; in addition, the existence of the bidirectional ladder energy band reduces the probability of leakage of electrons in the direction of the blocking oxide, and further improves the writing speed of the device.
FIG. 6 shows a memory oxide [ La ] having a stacked structure2O3]m[SiO2]n[La2O3]m[SiO2]nAnd a single storage oxide La2O3The charge trap memory device in (2) is powered off after the write operation, and a charge loss map of 10000 seconds(s) elapses. As can be seen from the figure, the oxide [ La ] is stored based on the stacked structure2O3]m[SiO2]n[La2O3]m[SiO2]nHas the smallest charge loss amount under the same holding time. Due to the adoption of the laminated structure, after charges trapped by interface defect states are excited to enter a conduction band, in the process of leaking to a tunneling oxide, the passing thin films are different in thickness, the closer to the trapped charges in the middle of the laminated structure, the longer the distance needs to pass, and except the charges at the first layer of interface in the laminated structure, the longer the distance needs to pass for the charges stored at other interfaces to return to the substrate conduction band is greater than the thickness of the tunneling oxide, so that the data retention capability of the device is improved. While using a single oxide film La2O3As a memory device for storing an oxide, La2O3The density of medium defect state is smaller than that of the laminated structure, and the charge storage density is difficult to be improved; in addition, the storage oxide has a consistent forbidden bandwidth, and charges only need to pass through the tunneling oxide in the process of leaking to the tunneling layer after being heated and excited to enter the conduction band of the storage oxide, so that the data retention performance is poorer than that of the laminated storage oxide.
Drawings
FIG. 1: a process for fabricating a charge trapping memory device having a bidirectional ladder energy band storage oxide, a) growing a tunneling oxide using an atomic layer deposition system; b) sequentially growing a stack structure as a storage oxide on the surface of a previously grown tunnel oxide by using an atomic layer deposition system, by using M and SiO in each layer2The growth order and cycle number of the cells, and the regulation and control of energy bands; c) growing a barrier oxide on the surface of the previously grown stacked oxide by utilizing an atomic layer deposition system; d) and growing a TaN electrode on the surface of the barrier oxide by using pulsed laser deposition.
FIG. 2: having a band structure of a bidirectional ladder band storage oxide charge trapping type memory device.
FIG. 3: the TaN electrode has a band structure in the written state of the bidirectional ladder band memory oxide charge trapping memory device with a forward voltage applied thereto, where "●" represents electrons.
FIG. 4: having a band structure in a data retention state of a bidirectional ladder band storage oxide charge trap type memory device, wherein "●" represents electrons.
FIG. 5: stacked memory oxide [ La2O3]m[SiO2]n[La2O3]m[SiO2]nSingle storage oxide La2O3Write speed of the base charge trap memory device, in which the operating voltage is + 8V.
FIG. 6: stacked memory oxide [ La2O3]m[SiO2]n[La2O3]m[SiO2]nSingle storage oxide La2O3Data retention capability of a charge trapping memory device, where the x-axis represents retention time (in seconds) and the y-axis represents percent charge loss of the charge storage device.
Detailed Description
Example 1: the charge trap memory device having a stacked memory oxide is prepared as follows:
a) placing the substrate material cleaned by acetone and hydrofluoric acid on a tray of a cavity of an atomic layer deposition system, and then growing a layer of 2nm SiO on the surface of the substrate by using the atomic layer deposition system2As a tunneling oxide, wherein SiO2The precursor is SiH [ N (CH)3)2]3，H2O is taken as an oxygen source, and the temperature in the deposition chamber is 300 ℃;
b) growing a laminated film structure on the surface of the tunneling oxide by utilizing an atomic layer deposition system to serve as a storage oxide, wherein the laminated structure comprises nine films which are sequentially grown, and the growth sequence of each film is [ La2O3]m[SiO2]n[La2O3]m[SiO2]nAnd m and n represent the number of pulse cycles in the atomic layer deposition process, in the following order: growing m cycles of La first2O3Followed by n cycles of growing SiO2Regrown m cycles of La2O3Finally growing n cycles of SiO2；La2O3The precursor is La (N (Si (CH)3)3)2)3，SiO2The precursor is SiH [ N (CH)3)2]3，H2O is taken as an oxygen source; nine films grown sequentially, where m and n have different values, such that m + n is 5, are the first layer [ La ] in sequence starting immediately after the tunnel oxide2O3]1[SiO2]4[La2O3]1[SiO2]4 M 1, n 4, a second layer [ La2O3]2[SiO2]3[La2O3]2[SiO2]3 M 2, n 3, a third layer [ La2O3]3[SiO2]2[La2O3]3[SiO2]2M is 3, n is 2, fourth layer [ La2O3]4[SiO2]1[La2O3]4[SiO2]1M is 4, n is 1, fifth layer [ La2O3]5[SiO2]0[La2O3]5[SiO2]0M is 5, n is 0, sixth layer [ La2O3]4[SiO2]1[La2O3]4[SiO2]1M is 4, n is 1, seventh layer [ La2O3]3[SiO2]2[La2O3]3[SiO2]2M is 3, n is 2, eighth layer [ La2O3]2[SiO2]3[La2O3]2[SiO2]3 M 2, n 3, and a ninth layer [ La2O3]1[SiO2]4[La2O3]1[SiO2]4，m＝1，n＝4；
c) Growing a layer of 15nm SiO on the surface of the previously formed stacked memory oxide by utilizing an atomic layer deposition system2As a barrier oxide, SiH [ N (CH) is a precursor3)2]3，H2Taking O as an oxygen source, keeping the temperature in a deposition cavity at 300 +/-25 ℃, and carrying out in-situ heat preservation on the prepared structure for 3 hours;
d) deposition on SiO by pulsed laser2Growing a layer of 200nm TaN on the surface of the barrier oxide to serve as an upper electrode, and smearing silver colloid on the back of the silicon substrate to serve as a lower electrode;
example 2: la with single storage oxide2O3The process for fabricating the charge trap memory device of (1) is as follows:
a) placing the substrate material cleaned by acetone and hydrofluoric acid on a tray of a cavity of an atomic layer deposition system, and then growing a layer of 2nm SiO on the surface of the substrate by using the atomic layer deposition system2As a tunneling oxide, wherein SiO2The precursor is SiH [ N (CH)3)2]3，H2O is taken as an oxygen source, and the temperature in the deposition chamber is 300 ℃;
b) growing single storage oxide La on surface of tunneling oxide by utilizing atomic layer deposition system2O, La (N (Si (CH)) as precursor3)3)2)3Number of cycles of 90, H2O is taken as an oxygen source;
c) growing a layer of 15nm SiO on the surface of the previously formed stacked memory oxide by utilizing an atomic layer deposition system2As a barrier oxide, SiH [ N (CH) is a precursor3)2]3，H2Taking O as an oxygen source, keeping the temperature in a deposition cavity at 300 +/-25 ℃, and carrying out in-situ heat preservation on the prepared structure for 3 hours;
d) deposition on SiO by pulsed laser2And growing a layer of 200nm TaN on the surface of the barrier oxide to serve as an upper electrode, and smearing silver colloid on the back of the silicon substrate to serve as a lower electrode.
Claims (2)
1. A method for preparing a charge trapping memory device with a bidirectional ladder energy band memory oxide is characterized by comprising the following steps:
a) growing a layer of 1-4nm SiO on the surface of the silicon substrate by utilizing an atomic layer deposition system2As the tunneling oxide, the precursor is tris (dimethylamino) silane (SiH [ N (CH) ]3)2]3)，H2O is taken as an oxygen source, and the temperature in the deposition chamber is 300 +/-25 ℃;
b) growing a laminated film structure on the surface of the tunneling oxide by utilizing an atomic layer deposition system to serve as a storage oxide, wherein the laminated structure comprises nine films which are sequentially grown, and the growth sequence of each film is [ M [ ]]m[SiO2]n[M]m[SiO2]nWherein M may be La2O3、ZrO2、HfO2Any one of m and n represents the number of atomic layer deposition cycles in the order: first M cycles of M followed by n cycles of SiO2Regrowing M cycles of M and finally n cycles of SiO2(ii) a Different M, precursors can be in tris [ N, N-bis (trimethylsilyl) amine]Lanthanum (La (N (Si (CH))3)3)2)3) Zirconium tetrachloride (ZrCl)4) Hafnium tetrachloride (HfCl)4) Optionally one of (1), SiO2The precursor is tri (dimethylamino) silane (SiH [ N (CH) ]3)2]3)，H2O is taken as an oxygen source; nine films grown sequentially, where M and n have different values, such that M + n is 5, are the first layer [ M ] in sequence starting immediately after the tunnel oxide]1[SiO2]4[M]1[SiO2]4M1, n 4, second layer [ M]2[SiO2]3[M]2[SiO2]3M2, n 3, a third layer [ M ═ M]3[SiO2]2[M]3[SiO2]2M3, n 2, a fourth layer [ M ═ M]4[SiO2]1[M]4[SiO2]1M is 4, n is 1, fifth layer [ M ═ M]5[SiO2]0[M]5[SiO2]0M is 5, n is 0, sixth layer [ M]4[SiO2]1[M]4[SiO2]1M4, n 1, seventh layer [ M ═ M]3[SiO2]2[M]3[SiO2]2M is 3, n is 2, eighth layer [ M]2[SiO2]3[M]2[SiO2]3M2, n 3, and a ninth layer [ M]1[SiO2]4[M]1[SiO2]4，m＝1，n＝4；
c) Growing a layer of 15-20nm SiO on the surface of the previously formed stacked memory oxide by utilizing an atomic layer deposition system2As the barrier oxide, the precursor is tris (dimethylamino) silane (SiH [ N (CH) ]3)2]3)，H2Taking O as an oxygen source, keeping the temperature in a deposition cavity at 300 +/-25 ℃, and carrying out in-situ heat preservation on the prepared structure for 2-3 hours;
d) deposition on SiO by pulsed laser2A layer of TaN with the thickness of 100-200nm is grown on the surface of the barrier oxide to serve as an upper electrode, and silver colloid is coated on the back surface of the silicon substrate to serve as a lower electrode.
2. A charge trapping memory device prepared according to the method of claim 1.
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| 多层HfO2/Al2O3薄膜基电荷陷阱存储器件的存储特性研究;汤振杰;《真空科学与技术学报》;20141215;第34卷(第12期);1347-1351 * |
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