CN107768379A - A kind of low-power consumption charge trapping memory based on graphene oxide quantum dot and preparation method thereof - Google Patents
A kind of low-power consumption charge trapping memory based on graphene oxide quantum dot and preparation method thereof Download PDFInfo
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Abstract
The invention provides a kind of low-power consumption charge trapping memory based on graphene oxide quantum dot and preparation method thereof, its structure is successively by Si substrates, SiO2Tunnel layer, GQODs/Zr0.5Hf0.5O2Capture layer, SiO2Barrier layer, Pd top electrodes are formed；Its preparation method：Si substrates carry out cleaning corrosion and are substrate, high annealing growth SiO2Tunnel layer, one layer of GQODs is equably got rid of in tunnel layer SiO with SC 1B sol evenning machines2On, the method sputtered by magnetron sputtering plates capture layer, barrier layer and electrode film layer in existing structure.Have the advantages that for the relatively general charge trapping memory of this memory relatively low operating voltage, fatigue resistance be good, data preserve persistently, memory window is big, charge leakage is small, low-power consumption and low cost, it is especially suitable for, using on an electronic device, there is certain market application value.
Description
Technical field
It is specifically a kind of to be aoxidized based on graphene the present invention relates to non-volatile type memory devices and preparation method thereof
Low-power consumption charge trapping memory of thing quantum dot and preparation method thereof.
Background technology
Traditional flash storage is nonvolatile storage, is followed successively by silicon substrate, tunnel layer, floating gate layer, resistance from top to bottom
Barrier and top electrode.In the case where applying certain bias voltage effect, the carrier meeting tunnel oxide insulating barrier in substrate enters floating
In gate layer, now metal floating boom is powered compared with before, and powered not charged two kinds of completely different states realize information
Storage.Influenceed by Moore's Law, in order to which by device miniaturization, by its scaled down, this is the physics that tunnel layer has reached 7nm
The limit.Because electric charge is evenly distributed on floating gate layer, it is easy for causing electric charge disposably to reveal if very thin tunnel layer is defective,
The purpose preserved for a long time is not reached.As integrated level raising and size reduce, two grid degree of coupling decline, crosstalk between device
Enhancing, so as to cause logicality mistake, and then device miniaturization is limited.1967, A.R. Wegner et al. were proposed for the first time
Trapped-charge memory（CTM）Concept, its initial configuration MNOS, as device size is less and less, trapping medium layer is too thin,
The electric charge being stored therein can be revealed in the presence of electric field from the control gate at top.In order to prevent the leakage of electric charge, scientific research people
Member plus one layer of insulating oxide, i.e. MONOS, due to the presence of barrier oxide layer, the situation that electric charge is revealed by control gate obtains
Good control.The introducing of high K dielectric material (high-K, Al2O3) and high work function grid material (TaN), by CTM
Push to a new high.This CTM structure relative maturity is developed into, the research of trapping layer materials, phase are more directed in research afterwards
Prestige can obtain the more preferable charge trapping memory of new storage performance.
The content of the invention
An object of the present invention there is provided a kind of low-power consumption charge trap-type based on graphene oxide quantum dot and deposit
Reservoir, to overcome the problems such as trapped-charge memory operating voltage of existing structure is high, power consumption is big, realize electric capacity retention property
The purpose of good, low-power consumption, low-leakage current and low voltage operating.
The second object of the present invention is to provide the low-power consumption charge trap-type based on graphene oxide quantum dot simultaneously to deposit
The preparation method of reservoir.
What an object of the present invention was realized in：
A kind of low-power consumption charge trapping memory based on graphene oxide quantum dot, it is to be sequentially formed with a si substrate
SiO2Tunnel layer, GQODs/Zr0.5Hf0.5O2Capture layer, SiO2Barrier layer and Pd top electrodes, wherein the GQODs/
Zr0.5Hf0.5O2GQODs layers in capture layer are single-layer graphene oxide quantum dot layer.
The described low-power consumption charge trapping memory based on graphene oxide quantum dot, the single-layer graphene oxide
Quantum dot layer is that graphene oxide quantum dot water slurry is added into the SiO using the method for drop coating-rotation2Tunnel layer
Go up and dry to obtain, the graphene oxide quantum dot water slurry is prepared as follows obtaining：
In quartz glass tube, 40: 1 by concentration 0.5mg/mL graphene oxide waterborne suspension and concentration by volume
30wt% aqueous hydrogen peroxide solution mixing, then at the uniform velocity stirs 40 minutes to obtain reactant under the conditions of ultra violet lamp, then will
The reactant produces graphene oxide quantum dot water slurry using 3500 Da bag filter to product dialysis more than 72h.
The described low-power consumption charge trapping memory based on graphene oxide quantum dot, the SiO2The thickness of tunnel layer
Spend for 2 ~ 5nm, the GQODs/Zr0.5Hf0.5O2Zr in capture layer0.5Hf0.5O2The thickness of layer is 5 ~ 80nm, the SiO2Stop
The thickness of layer is 5 ~ 50nm.
What the second object of the present invention was realized in：
The preparation method of low-power consumption charge trapping memory based on graphene oxide quantum dot, step are as follows：
（a）Si substrates are cleaned in acetone, alcohol and deionized water with ultrasonic wave successively, then 1 is cleaned with HF solution ~
2min, then be cleaned by ultrasonic with deionized water, N is used after taking-up2Drying, obtains the good Si substrates of cleaning treatment；
（b）The Si substrates handled well are put into high-temperature annealing furnace, in the environment of oxygen, carry out annealing growth SiO2Tunnel layer：
200 DEG C first are raised to from room temperature with 20s, is then raised to 500 DEG C from 200 DEG C with 60s, 150s is kept at 500 DEG C, is dropped afterwards with 10s
To 100 DEG C, then room temperature is dropped to from 100 DEG C in 40s, form SiO2Tunnel layer, obtain SiO2/ Si structures；
（c）By the SiO2/ Si structures are placed on the rotation sucker of SC-1B sol evenning machines, and rotating speed is arranged to 2500 ~ 4000r/min,
Graphene oxide quantum dot water slurry, which is drawn, with rubber head dropper and is added dropwise 1 ~ 2 drops to SiO2Tunnelling layer surface, start, so that
SiO2Tunnelling layer surface uniformly gets rid of one layer of graphene oxide quantum dot, forms single-layer graphene oxide quantum dot layer, obtains GQODs/
SiO2/ Si structures；
The preparation method of the graphene oxide quantum dot water slurry is：, by volume 40: 1 will be dense in quartz glass tube
The aqueous hydrogen peroxide solution mixing of 0.5mg/mL graphene oxide waterborne suspension and concentration 30wt% is spent, then ultraviolet
Reactant is at the uniform velocity stirred 40 minutes to obtain under the conditions of light irradiation, the reactant is then used into 3500 Da bag filter to product
Dialysis more than 72h produces graphene oxide quantum dot water slurry；
（d）By the GQODs/SiO2/ Si structures are put into the growth room of high vacuum magnetron sputtering apparatus, it is evacuated down to 1 ×
10-3~1× 10-5Pa, it is passed through the Ar that flow is 20 ~ 100sccm and the O that flow is 10 ~ 50sccm2, adjust the gas in growth room
It is pressed in 0.5 ~ 10Pa, 20 ~ 180W of power is set, allows pick hafnium oxygen target build-up of luminance, after pre-sputtering 7min, 1 ~ 4hour of formal sputtering,
Single-layer graphene oxide quantum dot layer surface forms pick hafnium oxygen film layer, obtains Zr0.5Hf0.5O2/GQODs/SiO2/ Si structures；
（e）By the Zr0.5Hf0.5O2/GQODs/SiO2/ Si structures are put into Grown by Magnetron Sputtering room, are evacuated down to 1 × 10-3
~1× 10-5Pa, it is passed through the Ar that flow is 30 ~ 150sccm and the O that flow is 10 ~ 50sccm2, adjust growth room in air pressure exist
0.5 ~ 10Pa, 60 ~ 200W of power is set, makes silica target build-up of luminance, after pre-sputtering 7min, 0.25 ~ 1hour of formal sputtering,
SiO is formed in pick hafnium oxygen film surface2Barrier layer, obtain SiO2/Zr0.5Hf0.5O2/GQODs/SiO2/ Si structures；
（f）In the SiO2/Zr0.5Hf0.5O2/GQODs/SiO2The SiO of/Si structures2Barrier layer surface places mask plate, together
Put magnetron sputtering apparatus growth room into, be evacuated down to 0.1 × 10-4~4×10-4Pa, the Ar that flow is 20 ~ 30sccm is passed through, is adjusted
Air pressure in whole growth room sets 5 ~ 20W of power in 0.5 ~ 6Pa, makes Pd target build-ups of luminance, after pre-sputtering 7min, formal sputtering
0.25 ~ 1hour, in SiO2Barrier layer surface forms some circular Pd electrode film layers, obtains Pd/SiO2/Zr0.5Hf0.5O2/GQODs/
SiO2/ Si structures, it is the low-power consumption charge trapping memory based on graphene oxide quantum dot.
Charge trapping memory provided by the present invention, showing more has relatively low operating voltage, fatigue resistance
Well, data preservation is lasting, memory window is big（Under ± 5V scanning voltages, 1.67V memory windows）, charge leakage is small, low-power consumption and
The advantages that inexpensive, it is especially suitable for, using on an electronic device, there is certain market application value.Preparation side provided by the invention
Method is simple and easy, good operability, by controlling sputtering time, pressure, power and the gas flow of magnetron sputtering, obtains performance
Superior Zr0.5Hf0.5O2、SiO2Film；By controlling annealing temperature, time and oxygen flow, the suitable SiO of thickness has been obtained2
Tunnel layer, due to Zr0.5Hf0.5O2Capture layer is done jointly with GQODs, and its defect is very big to component influences, so the present invention passes through
Unique structure, relatively low operating voltage, the holding of high data and the electric charge capture of low-power consumption has been made in certain material by ad hoc approach
Type memory.
Brief description of the drawings
Fig. 1 is charge trapping memory structural representation provided by the present invention.
In Fig. 1：1st, Si substrates, 2, SiO2Tunnel layer, 3, GQODs layers, 4, Zr0.5Hf0.5O2Layer, 5, SiO2Barrier layer, 6, Pd
Electrode film layer.
Fig. 2 is to be splashed in the present invention for preparing the charge trapping memory high vacuum magnetic control of graphene oxide quantum dot
The structural representation of jet device.
In Fig. 2：7th, the first intake valve, 8, growth room, the 9, second intake valve, 10, side take out valve, 11, target, 12, substrate,
13rd, substrate table, 14, slide valve.
Fig. 3 is the C-V characteristic curve schematic diagrames for implementing the charge trapping memory part prepared by 2 in the present invention.
Fig. 4 is the memory window-scanning voltage characteristic for implementing the charge trapping memory part prepared by 2 in the present invention
Figure.
Fig. 5 is the high and low electric capacity retention performance figure for implementing the charge trapping memory part prepared by 2 in the present invention.
Fig. 6 is the I-V characteristic schematic diagram for implementing the charge trapping memory part prepared by 2 in the present invention.
Fig. 7 is the C-V characteristic curve schematic diagrames of the memory cell prepared by comparative example 1.
Fig. 8 is the high and low electric capacity retention performance figure of the memory cell prepared by comparative example 1.
Fig. 9 is GQODs layers XPS detections data in device prepared by embodiment 2.
Figure 10 is GQODs layer SEM scanning figures in device prepared by embodiment 2.
Figure 11 is the capacitance-voltage characteristics schematic diagram of the memory cell prepared by comparative example 2.
Embodiment
Example below is used to the present invention be further described, but embodiment does not do any type of limit to the present invention
It is fixed.Unless stated otherwise, the reagent of the invention used, method and apparatus is the art conventional reagent, methods and apparatus.But
The invention is not limited in any way.
Embodiment 1
Charge trapping memory structure prepared by the present invention is as shown in figure 1, its structure is integrated with successively on Si substrates 1
SiO2Tunnel layer 2, GQODs/Zr0.5Hf0.5O2Capture layer, SiO2Barrier layer 5, Pd electrode film layers 6, GQODs/ Zr0.5Hf0.5O2Prisoner
Layer is obtained by GQODs layers 3 and Zr0.5Hf0.5O2Layer 4 is formed, and GQODs layers 3 are single-layer graphene oxide quantum dot layer.
Si substrates 1 are the p-type Si materials of 100 crystal orientation；SiO2The thickness of tunnel layer 2 is 2 ~ 5nm；GQODs/Zr0.5Hf0.5O2Prisoner
It is 5 ~ 80nm to obtain the thickness of layer 4, preferentially from 10 ~ 40nm；SiO2The thickness of barrier layer 5 is 5 ~ 50nm, most preferably in 5 ~ 20nm；Pd electricity
Pole film layer 6 for 20 ~ 150nm of thickness, 60 ~ 300 μm of circular electrode films of diameter.
Embodiment 2
The preparation method of the charge trapping memory of the present invention, step are as follows：
（a）P-Si substrates are cleaned in acetone, alcohol and deionized water with ultrasonic wave successively, with HF solution（Volume ratio H2O:
HF=2:1）2min is cleaned, then is cleaned by ultrasonic with deionized water, N is used after taking-up2Drying；The silicon substrate handled well is put into high temperature
Annealing furnace, in the environment of oxygen, carry out annealing growth SiO2Tunnel layer：First 200 DEG C are raised to 20s from room temperature, 60s is from 200
500 DEG C DEG C are raised to, 500 DEG C of holdings 150s, 10s drop to 100 DEG C, and 40s drops to room temperature, gained SiO from 100 DEG C2The thickness of tunnel layer
Spend for 3nm, obtain SiO2/ Si structural substracts.
（c）By SiO2/ Si structural substracts are placed on SC-1B sol evenning machines and rotated on sucker, carry out rotating speed and set 4000r/min,
Graphene oxide quantum dot water slurry is drawn with rubber head dropper and 2 drop to SiO2Tunnelling layer surface, start sol evenning machine, in SiO2
Tunnelling layer surface forms GQODs layers, i.e. single-layer graphene oxide quantum dot layer, obtains GQODs/SiO2/ Si structural substracts；
In this step, graphene oxide quantum dot water slurry is in quartz glass tube, and 40: 1 by concentration by volume
0.5mg/mL graphene oxide waterborne suspension（Purchased in market or self-control）Mixed with concentration 30wt% aqueous hydrogen peroxide solution,
Then reactant is at the uniform velocity stirred 40 minutes to obtain under the conditions of ultra violet lamp, the reactant is then used into the saturating of 3500 Da
Analysis bag produces graphene oxide quantum dot water slurry to product dialysis 72h.
（d）Utilize magnetron sputtering apparatus（Such as Fig. 2）, by Zr0.5Hf0.5O2Target 11 is arranged on the target platform in growth room 8,
By substrate 12（I.e. upper step gained GQODs/SiO2/ Si structural substracts）It is compressed on substrate table 13, closes the first intake valve 7, open
Mechanical pump, open side and take out valve 10, vacuumize under 5Pa, close side and take out valve 10, drive molecular pump, open a sluice gate plate valve 14 and be evacuated down to 3 × 10-4Pa,
Open the second intake valve 9 and be passed through the Ar that flow is 50sccm and the O that flow is 25sccm2, adjust growth room 8 in air pressure exist
3Pa, power 80W is set, allows pick hafnium oxygen target build-up of luminance, after pre-sputtering 7min, formal sputtering 1.8hour, form the thick pick of 18nm
Hafnium oxygen film, i.e. Zr0.5Hf0.5O2Layer, obtains Zr0.5Hf0.5O2/GQODs/SiO2/ Si structural substracts.
（e）By Zr0.5Hf0.5O2/GQODs/SiO2/ Si structural substracts are put into Grown by Magnetron Sputtering room, same operating procedure
（Change SiO2Target）It is evacuated down to 3 × 10-4Pa, it is passed through the Ar that flow is 75sccm and the O that flow is 25sccm2, adjustment growth
Indoor air pressure is after 3Pa, setting power 150W, pre-sputtering 7min, formal sputtering 30min, forms the thick SiO of 18nm2Stop
Layer, obtains SiO2/Zr0.5Hf0.5O2/GQODs/SiO2/ Si structural substracts.
（f）In SiO2/Zr0.5Hf0.5O2/GQODs/SiO2Mask plate is placed on/Si structural substracts, magnetic control is together put into and splashes
Jet device growth room, is equally evacuated down to 2 × 10-4Pa, is passed through the Ar that flow is 25sccm, and the air pressure adjusted in growth room exists
After 1Pa, setting power 10W, pre-sputtering 7min, formal sputtering 12min, the thick Pd electrode film layers of 60nm are formed, obtain Pd/SiO2/
Zr0.5Hf0.5O2/GQODs/SiO2The memory cell of/Si structures.
Comparative example 1
According to implementation same as Example 2, wherein step is deleted（c）Preparation structure is Pd/SiO2/Zr0.5Hf0.5O2/
SiO2The memory cell of/Si structures.
Comparative example 2
According to implementation same as Example 2, wherein pick hafnium oxygen film preparation step is deleted, prepares Pd/SiO2/GOQDs/
SiO2The memory cell of/Si structures.
Structure detection：
In the memory cell preparation process of embodiment 2, step（c）Afterwards, XPS detections are carried out to the GQODs formed and SEM is swept
Retouch, as a result respectively as shown in Figure 9 and Figure 10.In Fig. 9, peak value 284.5eV, 286.4eV, 287.8eV and 288.5eV are corresponded to respectively
In C-C/C=C groups（Curve 3）, CO groups（Curve 5）, C=O groups and COOH group in aromatic rings（Curve 4）.
The peak value provided according to document, find matched curve（Curve 2）And actual curve（Curve 1）Measured value is almost completely the same, this
Suffice to show that the presence for the graphene oxide quantum dot being widely used due to the structure of uniqueness.Figure 10 is in scanning electron
Under microscope, surface texture extraction is carried out, pore is graphene oxide quantum dot micro-structure diagram in Figure 10.
Performance test：
Performance test, its C-V curve such as Fig. 3, memory window-scanning voltage characteristic are carried out to memory cell prepared by embodiment 2
As shown in Figure 4.Show that scanning voltage increases since 3V successively in Fig. 3, Fig. 4, the memory window when scanning voltage increases to 5V
When maximum, i.e. scanning voltage are+5V → -5V →+5V, the memory window of memory device is with the increase of scanning voltage, memory window
Mouth gradually increase.When scanning voltage reaches 5V, the so big memory windows of 1.67V are showed, this demonstrate very outstanding
Storage performance.Fig. 5 is the high and low electric capacity retention performance figure of the charge trapping memory part prepared by embodiment 2 in the present invention
Measure, the decay of height electric capacity about 0.016%, it is seen that retention performance is very good.Fig. 6 is in the present invention prepared by embodiment 2
Charge trapping memory part I-V characteristic schematic diagram measure, it is seen that power consumption of memory is relatively low.
Performance detection is carried out to the memory cell prepared by comparative example 1, applied between its Pd electrode film layer and Si substrates
One come and go scanning voltage, measure its C-V characteristics, as shown in fig. 7, Fig. 7 show prepared by memory cell with
Implement under sample same operation voltage, it is smaller than the window of embodiment 2.Further the memory cell prepared by the comparative example is entered
Row electric capacity does retention performance test, as shown in figure 8, Fig. 8 shows the memory cell 104In the s holding testing time, electric capacity damage
Fail to keep an appointment as 4.76%, show unstable electric capacity retention performance.This explanation GOQDs enough has in trapped-charge memory
Improve the effect of performance.
Memory cell prepared by Figure 11 display comparisons example 2 is under ± 2V operating voltage, the memory prepared by comparative example 2
Element shows minimum memory window and its operating voltage can not be further continued for increasing, the results showed that prepared by comparative example 2
Memory cell can not load effective operating voltage and be captureed with generating enough tunelling electrons into single-layer graphene oxide quantum dot
Obtain layer.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by the embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (4)
1. a kind of low-power consumption charge trapping memory based on graphene oxide quantum dot, it is characterized in that, it is in Si substrates
On be sequentially formed with SiO2Tunnel layer, GQODs/Zr0.5Hf0.5O2Capture layer, SiO2Barrier layer and Pd top electrodes, wherein described
GQODs/Zr0.5Hf0.5O2GQODs layers in capture layer are single-layer graphene oxide quantum dot layer.
2. the low-power consumption charge trapping memory according to claim 1 based on graphene oxide quantum dot, its feature
It is that the single-layer graphene oxide quantum dot layer is the method using drop coating-rotation by graphene oxide quantum dot water slurry
It is added to the SiO2On tunnel layer and dry to obtain, the graphene oxide quantum dot water slurry is prepared as follows
Obtain：
In quartz glass tube, 40: 1 by concentration 0.5mg/mL graphene oxide waterborne suspension and concentration by volume
30wt% aqueous hydrogen peroxide solution mixing, then at the uniform velocity stirs 40 minutes to obtain reactant under the conditions of ultra violet lamp, then will
The reactant produces graphene oxide quantum dot water slurry using 3500 Da bag filter to product dialysis more than 72h.
3. the low-power consumption charge trapping memory according to claim 1 or 2 based on graphene oxide quantum dot, it is special
Sign is the SiO2The thickness of tunnel layer is 2 ~ 5nm, the GQODs/Zr0.5Hf0.5O2Zr in capture layer0.5Hf0.5O2The thickness of layer
Spend for 5 ~ 80nm, the SiO2The thickness on barrier layer is 5 ~ 50nm.
4. the preparation method of the low-power consumption charge trapping memory based on graphene oxide quantum dot described in claim 1, its
It is characterized in, step is as follows：
（a）Si substrates are cleaned in acetone, alcohol and deionized water with ultrasonic wave successively, then 1 is cleaned with HF solution ~
2min, then be cleaned by ultrasonic with deionized water, N is used after taking-up2Drying, obtains the good Si substrates of cleaning treatment；
（b）The Si substrates handled well are put into high-temperature annealing furnace, in the environment of oxygen, carry out annealing growth SiO2Tunnel layer：First
200 DEG C are raised to from room temperature with 20s, is then raised to 500 DEG C from 200 DEG C with 60s, 150s is kept at 500 DEG C, is dropped to afterwards with 10s
100 DEG C, then room temperature is dropped to from 100 DEG C in 40s, form SiO2Tunnel layer, obtain SiO2/ Si structures；
（c）By the SiO2/ Si structures are placed on the rotation sucker of SC-1B sol evenning machines, and rotating speed is arranged to 2500 ~ 4000r/min,
Graphene oxide quantum dot water slurry, which is drawn, with rubber head dropper and is added dropwise 1 ~ 2 drops to SiO2Tunnelling layer surface, start, so that
SiO2Tunnelling layer surface uniformly gets rid of one layer of graphene oxide quantum dot, forms single-layer graphene oxide quantum dot layer, obtains GQODs/
SiO2/ Si structures；
The preparation method of the graphene oxide quantum dot water slurry is：, by volume 40: 1 will be dense in quartz glass tube
The aqueous hydrogen peroxide solution mixing of 0.5mg/mL graphene oxide waterborne suspension and concentration 30wt% is spent, then ultraviolet
Reactant is at the uniform velocity stirred 40 minutes to obtain under the conditions of light irradiation, the reactant is then used into 3500 Da bag filter to product
Dialysis more than 72h produces graphene oxide quantum dot water slurry；
（d）By the GQODs/SiO2/ Si structures are put into the growth room of high vacuum magnetron sputtering apparatus, are evacuated down to 1 × 10-3~1× 10-5Pa, it is passed through the Ar that flow is 20 ~ 100sccm and the O that flow is 10 ~ 50sccm2, adjust the air pressure in growth room
In 0.5 ~ 10Pa, 20 ~ 180W of power is set, allows pick hafnium oxygen target build-up of luminance, after pre-sputtering 7min, 1 ~ 4hour of formal sputtering, in list
Layer graphene oxide quantum dot layer surface forms pick hafnium oxygen film layer, obtains Zr0.5Hf0.5O2/GQODs/SiO2/ Si structures；
（e）By the Zr0.5Hf0.5O2/GQODs/SiO2/ Si structures are put into Grown by Magnetron Sputtering room, are evacuated down to 1 × 10-3~
1× 10-5Pa, it is passed through the Ar that flow is 30 ~ 150sccm and the O that flow is 10 ~ 50sccm2, adjust growth room in air pressure exist
0.5 ~ 10Pa, 60 ~ 200W of power is set, makes silica target build-up of luminance, after pre-sputtering 7min, 0.25 ~ 1hour of formal sputtering,
SiO is formed in pick hafnium oxygen film surface2Barrier layer, obtain SiO2/Zr0.5Hf0.5O2/GQODs/SiO2/ Si structures；
（f）In the SiO2/Zr0.5Hf0.5O2/GQODs/SiO2The SiO of/Si structures2Barrier layer surface places mask plate, together puts
Enter magnetron sputtering apparatus growth room, be evacuated down to 0.1 × 10-4~4×10-4Pa, it is passed through the Ar that flow is 20 ~ 30sccm, adjustment
Air pressure in growth room sets 5 ~ 20W of power in 0.5 ~ 6Pa, makes Pd target build-ups of luminance, after pre-sputtering 7min, formal sputtering 0.25 ~
1hour, in SiO2Barrier layer surface forms some circular Pd electrode film layers, obtains Pd/SiO2/Zr0.5Hf0.5O2/GQODs/SiO2/
Si structures, it is the low-power consumption charge trapping memory based on graphene oxide quantum dot.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047842A (en) * | 2019-03-15 | 2019-07-23 | 南京大学 | A kind of silicon substrate charge trapping memory part and preparation method |
| CN111384267A (en) * | 2018-12-29 | 2020-07-07 | Tcl集团股份有限公司 | Preparation method of graphene quantum dot film, light-emitting diode and preparation method of light-emitting diode |
| CN112310282A (en) * | 2020-11-09 | 2021-02-02 | 河北大学 | Photoelectric resistive random access memory based on two-dimensional narrow band gap bismuth tellurium selenium material and preparation method and application thereof |
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| CN111384267B (en) * | 2018-12-29 | 2021-09-10 | Tcl科技集团股份有限公司 | Preparation method of graphene quantum dot film, light-emitting diode and preparation method of light-emitting diode |
| CN110047842A (en) * | 2019-03-15 | 2019-07-23 | 南京大学 | A kind of silicon substrate charge trapping memory part and preparation method |
| CN112310282A (en) * | 2020-11-09 | 2021-02-02 | 河北大学 | Photoelectric resistive random access memory based on two-dimensional narrow band gap bismuth tellurium selenium material and preparation method and application thereof |
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