CN107733367B - Oscillation circuit with fine adjustment control - Google Patents
Oscillation circuit with fine adjustment control Download PDFInfo
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- CN107733367B CN107733367B CN201610664136.1A CN201610664136A CN107733367B CN 107733367 B CN107733367 B CN 107733367B CN 201610664136 A CN201610664136 A CN 201610664136A CN 107733367 B CN107733367 B CN 107733367B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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Abstract
An oscillation circuit with fine tuning control, comprising: a basic oscillation circuit; the current source array is suitable for adjusting the output clock frequency of the basic oscillation circuit and comprises a plurality of rows of current sources, and the output of each row of current sources is controlled by a corresponding fine tuning switch; the oscillation circuit with fine adjustment control further includes: the gate voltage regulating circuit is suitable for receiving the fine tuning control signal, when the fine tuning control signal is used for controlling the fine tuning switch to be switched off, the voltage value of the fine tuning control signal is regulated to generate an output signal, and the output signal is used for controlling the fine tuning switch; when the trimming switch is a PMOS tube, the voltage value of an output signal of the grid voltage regulating circuit is higher than that of the trimming control signal; when the fine tuning switch is an NMOS tube, the voltage value of the output signal of the grid voltage adjusting circuit is lower than that of the fine tuning control signal. The scheme can reduce the output frequency of the oscillating circuit with fine adjustment control along with the temperature change.
Description
Technical Field
The invention relates to the technical field of oscillating circuits, in particular to an oscillating circuit with fine tuning control.
Background
In order to compensate for the effects of temperature on the oscillating circuit, trimming (trimming) control circuits are usually introduced on the basis of the oscillating circuit. However, when the Critical Dimension (CD) of the semiconductor process is small, the temperature characteristics of the oscillation circuit may be deteriorated due to the influence of the leakage current.
Therefore, if the leakage current is not suppressed in the oscillation circuit with the fine adjustment control, the leakage current may cause a large range of temperature-dependent variation in the output frequency of the oscillation circuit after passing through the fine adjustment control circuit, in other words, the temperature characteristic of the oscillation circuit may be deteriorated, thereby affecting the performance of the oscillation circuit.
Disclosure of Invention
The technical problem to be solved by the embodiment of the invention is to restrain the change of leakage current along with temperature, so that the change of the output frequency of the oscillating circuit with fine tuning control along with the temperature is reduced, and the characteristic of the change of the output frequency of the oscillating circuit with fine tuning control along with the temperature is improved.
To solve the above technical problem, an embodiment of the present invention provides an oscillation circuit with fine tuning control, including: the basic oscillation circuit current source array is suitable for adjusting the output clock frequency of the basic oscillation circuit and comprises a plurality of rows of current sources, the output of each row of current sources is controlled by a corresponding fine tuning switch, and the fine tuning switches are PMOS tubes or NMOS tubes;
the oscillation circuit to be subjected to fine tuning control further comprises:
the gate voltage adjusting circuit is suitable for receiving a fine tuning control signal, and when the fine tuning control signal is used for controlling the fine tuning switch to be switched off, the voltage value of the fine tuning control signal is adjusted to generate an output signal, and the output signal is used for controlling the fine tuning switch; when the fine tuning switch is a PMOS tube, the voltage value of the output signal of the grid voltage regulating circuit is higher than that of the fine tuning control signal; when the fine tuning switch is an NMOS tube, the voltage value of the output signal of the grid voltage regulating circuit is lower than that of the fine tuning control signal.
Optionally, when the trimming switch is a PMOS transistor, the gate voltage adjusting circuit includes: the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the first capacitor and the second capacitor;
a first terminal of the first switch receives a reference voltage, and a second terminal of the first switch is coupled to a first terminal of the second switch; a first terminal of the first capacitor is coupled to a second terminal of the first switch; a first end of the third switch is grounded, and a second end of the third switch is coupled with a second end of the first capacitor; a first terminal of the fourth switch is coupled to a power supply, and a second terminal of the fourth switch is coupled to a second terminal of the first capacitor; a first terminal of the fifth switch is coupled to a second terminal of the second switch, the second terminal of the second switch outputs the output signal, and the second terminal of the fifth switch is grounded, wherein the output signal is output to a gate of the PMOS transistor; the first end of the second capacitor is coupled to the second end of the second switch, and the second end of the second capacitor is grounded.
Optionally, the disconnection or the conduction of the first switch and the third switch is controlled by a first clock signal, the disconnection or the conduction of the second switch and the fourth switch is controlled by a second clock signal, and the disconnection or the conduction of the fifth switch is controlled by the fine tuning control signal, wherein the first clock signal and the second clock signal have the same frequency and are opposite in phase.
Optionally, the first clock signal and the second clock signal are generated based on an output clock signal of the base oscillation circuit.
Optionally, when the trimming switch is a PMOS transistor, a source of the PMOS transistor is connected to a power supply, a source of the PMOS transistor is connected to current sources in a corresponding column in the current source array, a gate of the PMOS transistor receives an output signal generated by the gate voltage adjusting circuit, and a voltage value of the output signal is higher than 10% of a power supply voltage.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the technical scheme of the embodiment of the invention is that the grid voltage regulating circuit is arranged, when the fine tuning switch needs to be switched off, the voltage value of a fine tuning control signal for controlling the fine tuning switch is firstly regulated, and then the regulated signal is used for replacing the fine tuning control signal to control the fine tuning switch. When the fine tuning switch adopts a PMOS (P-channel metal oxide semiconductor) tube, a fine tuning control signal is lifted into an output signal through the grid voltage regulating circuit, and for the PMOS tube, when the grid voltage is higher than the source voltage, the leakage current is greatly reduced, so that the leakage current of the PMOS tube used as the fine tuning switch is restrained under the condition that the signal connected to the grid is lifted, the leakage current of the fine tuning switch is close to zero, the influence of the leakage current on the temperature characteristic of the output frequency of the oscillating circuit with the fine tuning control is reduced, and in other words, the output frequency of the oscillating circuit with the fine tuning control is reduced along with the temperature change by restraining the leakage current. Similarly, for the NMOS, when the gate voltage is lower than the source voltage, the leakage current will be greatly reduced, so that the gate voltage adjusting circuit reduces the trimming control signal to the output signal, and the gate voltage of the NMOS is reduced, so that the leakage current of the NMOS is suppressed, and the leakage current of the trimming switch is close to zero, thereby reducing the influence of the leakage current on the temperature characteristic of the output frequency of the oscillating circuit with trimming control.
Further, the first clock signal and the second clock signal for the gate voltage adjusting circuit may be generated based on an output clock signal of the base oscillation circuit. By multiplexing the clock signal output by the basic oscillation circuit, the normal work of the grid voltage regulating circuit can be realized without additionally designing a clock signal generating circuit, so that the cost can be saved.
Drawings
Fig. 1 is a schematic structural diagram of an oscillating circuit with fine tuning control in the prior art;
FIG. 2 is a schematic diagram of an oscillating circuit with fine tuning control according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a gate voltage adjusting circuit according to an embodiment of the invention when the trimming switch is a PMOS transistor;
FIG. 4 is a graph showing the simulation effect of the prior art oscillator circuit with fine tuning control shown in FIG. 1;
fig. 5 is a diagram showing the effect of simulation of the oscillation circuit with fine adjustment control shown in fig. 2.
Detailed Description
As described in the background art, in an oscillation circuit with fine tuning control, if leakage current is not suppressed, the leakage current may cause a large range of temperature variation of the output frequency of the oscillation circuit after passing through the fine tuning control circuit, in other words, the temperature characteristic of the oscillation circuit may be deteriorated, thereby affecting the performance of the oscillation circuit.
The technical scheme of the embodiment of the invention is that the grid voltage regulating circuit is arranged, when the fine tuning switch needs to be switched off, the voltage value of a fine tuning control signal for controlling the fine tuning switch is firstly regulated, and then the regulated signal is used for replacing the fine tuning control signal to control the fine tuning switch. When the fine tuning switch adopts a PMOS (P-channel metal oxide semiconductor) tube, a fine tuning control signal is lifted into an output signal through the grid voltage regulating circuit, and for the PMOS tube, when the grid voltage is higher than the source voltage, the leakage current is greatly reduced, so that the leakage current of the PMOS tube used as the fine tuning switch is restrained under the condition that the signal connected to the grid is lifted, the leakage current of the fine tuning switch is close to zero, the influence of the leakage current on the temperature characteristic of the output frequency of the oscillating circuit with the fine tuning control is reduced, and in other words, the output frequency of the oscillating circuit with the fine tuning control is reduced along with the temperature change by restraining the leakage current. Similarly, for the NMOS, when the gate voltage is lower than the source voltage, the leakage current will be greatly reduced, so that the gate voltage adjusting circuit reduces the trimming control signal to the output signal, and the gate voltage of the NMOS is lower, so that the leakage current of the NMOS is suppressed, and the leakage current of the trimming switch is close to zero, thereby reducing the influence of the leakage current on the temperature characteristic of the output frequency of the oscillating circuit with trimming control.
In order to clearly illustrate the technical solution of the embodiment of the present invention, an oscillation circuit with fine tuning control in the prior art is first described with reference to fig. 1, and the problems therein are explained. As shown in fig. 1, in general, an oscillation circuit with fine adjustment control includes: a basic oscillation circuit 1 and a current source array 2.
The basic oscillator circuit 1 is used to generate an oscillating signal whose frequency is controlled by an incoming current. In order to compensate for the influence of temperature on the basic oscillator circuit 1, a trimming (trimming) control circuit is generally introduced on the basis of the basic oscillator circuit 1. The trimming control is to adjust the current flowing into the basic oscillation circuit using a plurality of current sources controlled by trimming switches, which are included in the current source array 2. The current sources in the current source array 2 can be formed by PMOS transistors or NMOS transistors, and fig. 1 only shows that the current source array 2 is formed by PMOS transistors, and can be NMOS transistors in practice. The trim switches in fig. 1 comprise trim switches K0, K1 to KN, each of which is controlled by an external trim control signal.
The fundamental principle of implementing the fine tuning control is that the fine tuning switch is turned on or off according to the control value of the received fine tuning control signal, and accordingly, whether the current source connected to the fine tuning switch outputs the current is controlled to adjust the current flowing into the basic oscillation circuit, so that the oscillation frequency output by the basic oscillation circuit can be adjusted. Ideally, the trimming switch turns off the current source and the current for the column is zero. In practice, however, in advanced processes, the size and threshold of the device are small, leakage current still exists when the trimming switch is turned off, and the leakage current can cause the oscillation circuit with the trimming control to have a large range of variation with temperature, and the temperature characteristic of the oscillation circuit with the trimming control is poor.
Generally, the trimming switch is a PMOS transistor or an NMOS transistor. The inventor of the present application has found that the above problem is caused because leakage current still exists although the PMOS transistor or the NMOS transistor is turned off, and the leakage current increases with an increase in temperature, thereby causing the oscillation circuit with fine adjustment control to have a wide range of variation with temperature. Based on the above, the present invention provides a method for suppressing the leakage current by adjusting the gate voltage, so as to reduce the influence of the leakage current on the temperature characteristic of the output frequency of the oscillation circuit.
In order to make the above objects, features and advantages of the present invention more comprehensible, a specific embodiment thereof is described in detail with reference to fig. 2.
Fig. 2 is a schematic structural diagram of an oscillation circuit with fine tuning control according to an embodiment of the present invention. As shown in fig. 2, the oscillation circuit with fine tuning control may include: a basic oscillation circuit 1, a current source array 2, and a plurality of gate voltage adjusting circuits 3.
The basic oscillator circuit 1 is used to generate an oscillating signal whose frequency is controlled by an incoming current. The fundamental oscillation circuit 1 may be various types of oscillator circuits such as a ring oscillator and an RC oscillator.
The current source array 2 is suitable for adjusting the output clock frequency of the basic oscillation circuit 1, the current source array 2 comprises a plurality of columns of current sources, the output of each column of current sources is controlled by a corresponding fine tuning switch, and the fine tuning switches are PMOS tubes or NMOS tubes. It should be noted that the current source in the current source array 2 may be formed by using a PMOS transistor or an NMOS transistor, and only the PMOS transistor is used as an illustration in fig. 2.
It should be noted that only one of the gate voltage adjusting circuits 3 is shown in fig. 3, and actually, the oscillating circuit with trimming control in this embodiment includes a plurality of gate voltage adjusting circuits 3, and the number of the gate voltage adjusting circuits 3 is the same as that of the trimming switches, and the output signal of each gate voltage adjusting circuit 3 is used as the gate control signal of the corresponding PMOS transistor or NMOS transistor.
In this embodiment, each gate voltage adjusting circuit 3 is adapted to receive a trimming control signal, and when the trimming control signal is used to control the trimming switch to be turned off, the voltage value of the trimming control signal is adjusted to generate an output signal, so that the output signal is used to control the trimming switch.
Specifically, compared with the conventional oscillation circuit with fine tuning control shown in fig. 1, the fine tuning control signal in this embodiment firstly passes through the gate voltage adjusting circuit 3, and the gate voltage adjusting circuit 3 adjusts the fine tuning control signal to generate an output signal, where the output signal is used for controlling the fine tuning switch. In other words, the trimming control signal of the present embodiment is not directly used as the control signal of the trimming switch, but first passes through the gate voltage adjusting circuit 3, and then the generated output signal controls the trimming switch.
Ideally, the leakage current of the prior art oscillation circuit with fine tuning control shown in fig. 1 should be zero when the fine tuning control signal controls the fine tuning switch to be turned off, such as controlling the fine tuning switch S0 to be turned off, but actually, the leakage current still exists, and the leakage current in the circuit shown in fig. 1 has a wide variation with temperature variation.
In this embodiment, the gate voltage adjusting circuit 3 receives an external fine tuning control signal, and when the fine tuning control signal is used to control the fine tuning switch to be turned off, the fine tuning control signal is adjusted to be the output signal to control the fine tuning switch S0. Aiming at the situation that the fine tuning switch is a PMOS tube, the adjustment is correspondingly uplifted, namely the voltage value of the output signal of the grid voltage adjusting circuit is higher than that of the fine tuning control signal; and aiming at the condition that the fine tuning switch is an NMOS tube, the adjustment is correspondingly reduced, so that the voltage value of the output signal of the grid voltage adjusting circuit is lower than the voltage value of the fine tuning control signal.
For a PMOS transistor, when the gate voltage is higher than the source voltage, the leakage current will drop significantly. Therefore, when the PMOS transistor needs to be turned off, under the condition that the fine tuning control signal connected to the gate is raised to be the output signal, the leakage current of the PMOS transistor serving as the fine tuning switch is suppressed, so that the leakage current of the branch where the fine tuning switch is located is close to zero, thereby reducing the influence of the leakage current on the temperature characteristic of the output frequency of the oscillation circuit with the fine tuning control, in other words, the output frequency of the oscillation circuit with the fine tuning control is reduced along with the temperature change by suppressing the leakage current. Similarly, for the NMOS, when the gate voltage is lower than the source voltage, the leakage current will be greatly reduced, so when the NMOS needs to be turned off, the gate voltage adjusting circuit reduces the trimming control signal to the output signal, and the output signal controls the gate of the NMOS, so that the leakage current of the NMOS is suppressed, the leakage current of the branch where the trimming switch is located is close to zero, and the influence of the leakage current on the temperature characteristic of the output frequency of the oscillating circuit with trimming control is reduced.
In a specific implementation of the present invention, when the trimming switch is a PMOS transistor, a source of the PMOS transistor is connected to a power supply VDD, a drain of the PMOS transistor is coupled to current sources in a corresponding column in the current source array, and a gate of the PMOS transistor receives an output signal generated by the gate voltage adjusting circuit. The gate voltage adjusting circuit 3 may output the output signal OUT having a voltage value higher than 10% of the power supply voltage VDD. Since the source of the PMOS transistor is connected to the power supply VDD, a voltage value of the output signal OUT which is 10% higher than the power supply VDD is equivalent to a voltage value of the output signal OUT which is 10% higher than the source voltage of the PMOS transistor.
It should be noted that, in the above specific implementation, the voltage value of the output signal OUT is higher than 10% of the source voltage of the PMOS transistor, and particularly in different gate voltage adjusting circuits, different ratios may need to be raised to better suppress the leakage current.
Fig. 3 is a schematic structural diagram of a gate voltage adjusting circuit according to an embodiment of the invention when the trimming switch is a PMOS transistor. The gate voltage adjusting circuit as shown in fig. 3 may include: a first switch S1, a second switch S2, a third switch S3, a third switch S3, a fifth switch S5, a first capacitor C1, and a second capacitor C2;
a first terminal of the first switch S1 receives a reference voltage VREF, a second terminal of the first switch S1 is coupled with a first terminal of the second switch S2;
a first terminal of the first capacitor C1 is coupled to a second terminal of the first switch S1;
a first terminal of the third switch S3 is coupled to ground VSS, and a second terminal of the third switch S3 is coupled to a second terminal of the first capacitor C1;
a first terminal of the fourth switch S4 is coupled to a power source, and a second terminal of the fourth switch S4 is coupled to a second terminal of the first capacitor C1;
a first terminal of the fifth switch S5 is coupled to a second terminal of the second switch S2, a second terminal of the second switch S2 outputs the output signal, and a second terminal of the fifth switch S5 is grounded, wherein the output signal is output to a gate of a PMOS transistor as a trimming switch;
the first terminal of the second capacitor C2 is coupled to the second terminal of the second switch S2, and the second terminal of the second capacitor C2 is grounded to GND.
In a specific implementation, the disconnection or the conduction of the first switch S1 and the third switch S3 is controlled by a first clock signal CLK1, the disconnection or the conduction of the second switch S2 and the fourth switch S4 is controlled by a second clock signal CLK2, and the disconnection or the conduction of the fifth switch S5 is controlled by the fine tuning control signal, wherein the first clock signal CLK1 and the second clock signal CLK2 have the same frequency and opposite phase.
In the embodiment of the present invention, when the trimming switch shown in fig. 2 is a PMOS transistor, the gate voltage adjusting circuit shown in fig. 3 may be used, and further, an output signal of the gate voltage adjusting circuit is used as a control signal of the PMOS transistor in the corresponding column of the current source array shown in fig. 2. Taking the trimming switch S0 shown in fig. 2 as an example, the trimming switch S0 is a first PMOS transistor, the source of the first PMOS transistor is coupled to the power voltage, and the drain of the first PMOS transistor is coupled to the column current source. For the gate voltage regulating circuit shown in fig. 3, when the fine tuning control signal is "1", the output terminal OUT of the gate voltage regulating circuit outputs "0"; when the fine tuning control signal is "0", the output voltage of the output end OUT of the gate voltage regulating circuit is "VDD + VREF", and at this time, the output voltage is higher than the power supply voltage. The source electrode of the first PMOS tube is coupled with the power supply voltage, so that the output voltage is higher than the source electrode voltage of the first PMOS tube at the moment, the leakage current of the row is restrained, the phenomenon that the output frequency of the whole oscillating circuit is greatly changed along with the temperature due to the leakage current of the row is avoided, and the temperature characteristic of the oscillating circuit with fine tuning control is improved.
It can be understood by those skilled in the art that when the trimming switch is a PMOS transistor, the gate voltage bootstrap circuit with other suitable structures may be adopted in the embodiment of the present invention to raise the voltage value of the trimming control signal, so that the gate voltage output to the PMOS transistor serving as the trimming switch is raised, and therefore, the gate voltage adjusting circuit described in the present invention should not be limited by the circuit structure shown in fig. 3.
It should be noted that, when the trimming switch is an NMOS transistor, the gate voltage adjusting circuit 3 may have any suitable structure to reduce the voltage value of the externally input trimming control signal, so that the gate voltage output to the PMOS transistor serving as the trimming switch is reduced, thereby suppressing the leakage current.
In a non-limiting implementation of the present invention, the first clock signal CLK1 and the second clock signal CLK2 for the gate voltage adjusting circuit may be generated based on an output clock signal of the base oscillator circuit. According to the implementation, the clock frequency output by the basic oscillation circuit is multiplexed, and the normal work of the grid voltage regulating circuit can be realized without additionally designing a clock signal generating circuit, so that the additional increase of the implementation cost is avoided.
Next, a comparison of simulation effects before and after applying the oscillation circuit with fine tuning control in the embodiment of the present invention will be described with reference to fig. 4 and 5, where the simulation effects specifically refer to changes in output frequency with temperature. Specifically, fig. 4 is a simulation effect of the oscillation circuit with fine adjustment control shown in fig. 1, in which case the gate voltage adjusting circuit is not employed. Fig. 5 is a diagram of a simulation effect of applying the oscillation circuit with fine adjustment control of fig. 2 and applying the gate voltage adjusting circuit shown in fig. 3.
The curves shown in fig. 4 show that in the temperature range from-40 ° to 125 °, the output frequency is 27.8979KHZ at the lowest, represented by point a, and 29.6941KHZ at the highest, represented by point B, with a 3.2% change in output frequency; the graph shown in fig. 5 shows that the output frequency is 27.90072KHZ at the lowest point C and 28.14526KHZ at the highest point D for a temperature range from-40 ° to 125 °, with a change of 0.4%. Comparing the output frequency variation of the simulation effect shown in fig. 4 and 5, it is found that, after the gate voltage adjusting circuit is adopted, the output frequency variation of the oscillating circuit with fine tuning control along with the temperature is obviously reduced, and the temperature characteristic of the oscillating circuit is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (4)
1. An oscillation circuit with fine tuning control, comprising:
a basic oscillation circuit;
the current source array is suitable for adjusting the output clock frequency of the basic oscillation circuit and comprises a plurality of rows of current sources, the output of each row of current sources is controlled by a corresponding fine tuning switch, and the fine tuning switches are PMOS tubes or NMOS tubes;
it is characterized by also comprising:
the gate voltage adjusting circuit is suitable for receiving a fine tuning control signal, and when the fine tuning control signal is used for controlling the fine tuning switch to be switched off, the voltage value of the fine tuning control signal is adjusted to generate an output signal, and the output signal is used for controlling the fine tuning switch;
when the fine tuning switch is a PMOS tube, the voltage value of the output signal of the grid voltage regulating circuit is higher than that of the fine tuning control signal;
when the fine tuning switch is an NMOS tube, the voltage value of the output signal of the grid voltage regulating circuit is lower than that of the fine tuning control signal;
when the trimming switch is a PMOS tube, the grid voltage regulating circuit comprises: the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the first capacitor and the second capacitor;
a first terminal of the first switch receives a reference voltage, and a second terminal of the first switch is coupled to a first terminal of the second switch;
a first terminal of the first capacitor is coupled to a second terminal of the first switch;
a first end of the third switch is grounded, and a second end of the third switch is coupled with a second end of the first capacitor;
a first terminal of the fourth switch is coupled to a power supply, and a second terminal of the fourth switch is coupled to a second terminal of the first capacitor;
a first end of the fifth switch is coupled to a second end of the second switch, the second end of the second switch outputs the output signal to the gate of the PMOS transistor, and the second end of the fifth switch is grounded;
the first end of the second capacitor is coupled to the second end of the second switch, and the second end of the second capacitor is grounded.
2. The oscillating circuit with the fine adjustment control according to claim 1, wherein the first switch and the third switch are controlled by a first clock signal to turn off or on, the second switch and the fourth switch are controlled by a second clock signal to turn off or on, and the fifth switch is controlled by the fine adjustment control signal to turn off or on, wherein the first clock signal and the second clock signal have the same frequency and are opposite in phase.
3. The oscillating circuit with fine tuning control of claim 2, wherein the first clock signal and the second clock signal are generated based on an output clock signal of the base oscillating circuit.
4. The oscillating circuit with the fine tuning control of claim 1, wherein when the fine tuning switch is a PMOS transistor, a source of the PMOS transistor is connected to a power supply, a source of the PMOS transistor is connected to a current source of a corresponding column in the current source array, and a gate of the PMOS transistor receives an output signal generated by the gate voltage adjusting circuit, wherein a voltage value of the output signal is higher than 10% of a power supply voltage.
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| JP2013214960A (en) * | 2012-03-08 | 2013-10-17 | Fujitsu Semiconductor Ltd | Crystal oscillation circuit and method of controlling crystal oscillation circuit |
| CN103248319B (en) * | 2012-04-25 | 2016-04-06 | 殷明 | A kind of low-power consumption oscillating circuit |
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