CN107731911A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN107731911A CN107731911A CN201710519874.1A CN201710519874A CN107731911A CN 107731911 A CN107731911 A CN 107731911A CN 201710519874 A CN201710519874 A CN 201710519874A CN 107731911 A CN107731911 A CN 107731911A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 210000000746 body region Anatomy 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000012535 impurity Substances 0.000 claims description 17
- 238000001514 detection method Methods 0.000 claims description 6
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052753 mercury Inorganic materials 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000005428 wave function Effects 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
In the semiconductor device of SJ structures, body regions and current detecting region are separated and suppress resistance to drops.The present invention provides a kind of semiconductor device, and the semiconductor device possesses:Semiconductor substrate;Including forming the body regions in the work action cell of more than 1 of the inside of semiconductor substrate;Including being formed in the current detecting region of the current detecting unit of more than 1 of the inside of semiconductor substrate;And it is arranged in the inside of semiconductor substrate between body regions and current detecting region, include the intermediate region in pressure-resistance structure portion, in body regions, current detecting region and intermediate region, the tubing string of the 1st conductivity type and the tubing string of the 2nd conductivity type is set alternately to configure at equal intervals.
Description
Technical field
The present invention relates to semiconductor device.
Background technology
In the past, in the semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor), it is known that have
The body regions and the structure in the current detecting region for detecting electric current being driven as element are (for example, referring to patent text
Offer 1).
Patent document 1:Japanese Unexamined Patent Publication 2010-219258 publications
The content of the invention
Technical problem
There is a situation where to surround current detecting region by pressure-resistance structures such as field plates.In the device with pressure-resistance structure,
If forming super-junction structure in body regions and current detecting region, the electric charge that the p-type of super-junction structure and the impurity of n-type be present is put down
Weighing apparatus is destroyed and makes the situation of resistance to drops.
Technical scheme
One aspect of the present invention, there is provided possess the semiconductor device of semiconductor substrate.Semiconductor device can possess bag
Include the body regions to be formed in the work action cell of more than 1 of the inside of semiconductor substrate.Semiconductor device can possess bag
Include to be formed in the current detecting region of the current detecting unit of more than 1 of the inside of semiconductor substrate.Semiconductor device can
It is arranged on the inside possessed in semiconductor substrate between body regions and current detecting region, and including pressure-resistance structure portion
Intermediate region.In body regions, current detecting region and intermediate region, the tubing string of the 1st conductivity type and the tubing string of the 2nd conductivity type
Can be to be alternately arranged at equal intervals.
Intermediate region can have the field plate formed in the top of semiconductor substrate.Intermediate region can with body regions
Adjacent region and the region adjacent with current detecting region are formed with diode portions.
The base of the 1st conductivity type is could be formed with the inside of semiconductor substrate and is led in formed below the 2nd of base
The drift region of electric type.Body regions and current detecting region can have multiple grooves, the multiple groove be formed as from
The downside for extending to the base is acted in the upper surface of the semiconductor substrate, and is configured with identical interval.Body regions and
Current detecting region can have the high concentration of the 2nd conductivity type of the top of the base formed in the region between each groove
Region.Area with high mercury can not be formed in intermediate region.
The diode portions adjacent with body regions and the diode portions adjacent with current detecting region have common base.
The diode portions adjacent with body regions and the diode portions adjacent with current detecting region can have the base separated.It is middle
Region can also be in the base of the diode portions adjacent with body regions and the base of the diode portions adjacent with current detecting region
There is the base of separation between area.
Semiconductor device can possess the upper surface side electrode in the formation of the top at least a portion region of body regions.
Semiconductor device can possess the current detecting electrode in the formation of the top at least a portion region in current detecting region.With
The adjacent diode portions of body regions can be connected with upper surface side electrode.The diode portions adjacent with current detecting region can be with
Connection is connected with current detecting with electrode.The tubing string of 1st conductivity type and the tubing string of the 2nd conductivity type are in body regions, current detecting
The impurity concentration of region and intermediate region can be with identical.
Foregoing invention content does not include whole features of the present invention.The sub-combination of these feature groups
(subcombination) present invention can also be formed.
Brief description of the drawings
Fig. 1 is the schematic diagram of the upper surface of the semiconductor device 100 of embodiments of the present invention.
Fig. 2 is the figure of one for representing the A-A' sections in Fig. 1.
Fig. 3 is the figure of other for representing the A-A' sections in Fig. 1.
Fig. 4 is the figure of other for representing the A-A' sections in Fig. 1.
Fig. 5 is the schematic diagram for amplifying the current detecting in Fig. 1 with the B portions of the adjacent corner of electrode 12.
Fig. 6 is the schematic diagram for amplifying the current detecting in Fig. 1 with the B portions of the adjacent corner of electrode 12.
Symbol description
11:Source electrode, 12:Current detecting electrode, 13:Grid, 14:Drain electrode, 21:Body regions, 22:Electric current detection region
Domain, 23:Pressure-resistance structure region, 24:Intermediate region, 26:Interlayer dielectric, 30:Semiconductor substrate, 32:Drift region, 33:Drain region,
34:Base, 36:P+ regions, 38:Source region, 40:Groove, 42:Gate insulating film, 44:Electrode portion, 52:Work action cell, 54:
Current detecting unit, 58:Diode portions, 60:Tubing string, 62:Tubing string, 70:Dielectric film, 72:Field plate, 74:Interlayer dielectric,
100:Semiconductor device.
Embodiment
Hereinafter, the present invention will be described according to the embodiment of the present invention, and implementation below does not limit the present invention
Protection domain.In addition, whole combinations of the feature illustrated in embodiments are not essential for invention Xie Decision schemes.
In this manual, by the side in the direction parallel with the depth direction of semiconductor substrate be referred to as " on ", opposite side
Referred to as " under ".In 2 interareas of substrate, layer or other parts, one side is referred to as upper surface, another side is referred to as lower surface.
The direction of " on ", " under " is not limited to gravity direction.
In this manual, although having used " source electrode ", the term of " drain electrode ", semiconductor device is not limited to MOSFET.
" emitter stage " and " colelctor electrode " in the bipolar transistors such as IGBT can also include " source electrode " and " drain electrode " in this manual
Term in the range of.
In embodiments, it is illustrated exemplified by being set to p-type by the 1st conductivity type, the 2nd conductivity type is set into n-type, but
The conductivity type in substrate, layer, region etc. can also be polarity opposite respectively.
Fig. 1 is the schematic diagram of the upper surface of the semiconductor device 100 of embodiments of the present invention.Semiconductor device 100 has
Standby semiconductor substrate 30.Semiconductor substrate 30 can be the compounds such as silicon substrate or nitride-based semiconductor or carborundum
Semiconductor substrate.In the top of the upper surface of semiconductor substrate 30 formed with source electrode 11 and current detecting electrode 12.Source electrode 11
It is one of upper surface side electrode.Can also be formed with grid 13 in the top of the upper surface of semiconductor substrate 30.
As one, source electrode 11, current detecting are with electrode 12 and grid 13 by metal materials such as aluminium, aluminium alloy, copper, copper alloys
Material is formed.Source electrode 11, current detecting are disposed separately each other with electrode 12 and grid 13.The semiconductor device 100 of this example is main
The longitudinal type device of depth direction flowing of the electric current along semiconductor substrate 30.This example semiconductor substrate 30 lower surface formed with
Drain electrode.
Body regions 21, current detecting region 22 and intermediate region 24 have been internally formed in semiconductor substrate 30.Body
Region 21 is the region of the main current flow of semiconductor device 100.Flowed in the principal current that body regions 21 flow via source electrode 11
To outside.Source electrode 11 is formed in the top at least a portion region of body regions 21.
Current detecting region 22 is the region of sensed current flowing.Sensed current flows via current detecting electrode 12
To the current sensing means of outside.Current detecting electrode 12 is formed in the upper of at least a portion region in current detecting region 22
Side.In the upper surface of semiconductor substrate 30, the area that current detecting electrode 12 is covered is less than the area that source electrode 11 is covered.
Current sensing means detects the current value of sensed current.Current sensing means can be based on the current value detected
Control semiconductor device 100.For example, in the case where the current value detected exceedes defined threshold value, current sensing means will
The control of semiconductor device 100 is off state.
Intermediate region 24 is arranged between body regions 21 and current detecting region 22, makes body regions 21 and current detecting
Region 22 separates.The pressure-resistance structures such as field plate are provided with intermediate region 24.
Pressure-resistance structure region 23 is could be formed with along the periphery of semiconductor substrate 30.Pressure-resistance structure region 23 is formed in body
The outside in region 21, current detecting region 22 and intermediate region 24.Formed with protection ring or field plate in pressure-resistance structure region 23
Deng pressure-resistance structure.Intermediate region 24 can have and the identical structure of pressure-resistance structure region 23.
Fig. 2 is the figure of one for representing the A-A' sections in Fig. 1.Each composition shown in Fig. 2 can be formed as along with Fig. 2's
The vertical direction extension of paper.In fig. 2, as one, in the lower face side of semiconductor device 100 formed with being doped with n-type
The n of impurity+The drain region 33 of type and drain electrode 14.
The work action cell 52 of more than 1 formed with main current flow in body regions 21.In current detecting region
The current detecting unit 54 of more than 1 formed with sensed current flowing in 22.The work action cell 52 and electric current of this example
Whether detection is by the use of unit 54 as to making electric current be sent out to the depth direction transistor that switches over of flowing of semiconductor substrate 30
Wave function.Work action cell 52 and current detecting preferably have identical structure and identical impurity concentration with unit 54.
In the upper surface of semiconductor substrate 30, the area shared by current detecting region 22 is less than face shared by body regions 21
Product.Area shared by current detecting region 22 can be less than 1/the 10 or 100 of the occupied area of body regions 21
Less than/1.
Intermediate region 24 is formed in the inside of semiconductor substrate 30 between body regions 21 and current detecting region 22.In
Between region 24 there is field plate 72 etc. in a manner of surrounding current detecting region 22.
The inside of semiconductor substrate 30 in intermediate region 24 does not form groove 40, work action cell 52 and electric current inspection
Unit 54 is used in survey.In this example, the region as transistor work is not formed in intermediate region 24.In the intermediate region of this example
In 24, at least in the region adjacent with body regions 21 and the region adjacent with current detecting region 22 formed with diode portions
58。
The diode portions 58 adjacent with body regions 21 electrically connect with source electrode 11.Two poles adjacent with current detecting region 22
Pipe portion 58 electrically connects with current detecting electrode 12.In addition, each diode portions 58 have common base 34.
In the semiconductor substrate 30 of this example, in body regions 21, current detecting region 22 and intermediate region 24, from following table
Rise and be sequentially formed with n in surface side+The drain region 33 of type and n-The drift region 32 of type.In addition, drift region 32 superficial layer formed with p-type
Base 34.In addition, run through base formed with groove 40, the groove 40 in body regions 21 and current detecting region 22
34, and untill extending to from the upper surface of semiconductor substrate 30 the downside of base 34 and reach drift region 32.
The mesa region between each groove 40 is sandwiched in as in work action cell 52 and current detecting unit 54
Any one plays function.In this example, the boundary using the center of the width of the short side direction of groove 40 as each unit.
The work action cell 52 of this example and current detecting are with unit 54, in the top of base 34 formed with n+The source region 38 of type.In source
Doped with the impurity that the concentration of the impurity than drift region 32 is high in area 38.Source region 38 is one of area with high mercury.Thus, work
By the use of unit 52 and current detecting unit 54 function is played as transistor.In this example, function is being played as transistor
In unit, the unit of lower section of source electrode 11 is will be formed in as work action cell 52, will be formed in current detecting electrode 12
The unit of lower section is as current detecting unit 54.
On the other hand, in intermediate region 24, source region 38 is not formed in the top of base 34.Base in intermediate region 24
Area 34 plays a role as the pn-junction diode with drift region 32 (tubing string 62 of n-type).Using intermediate region 24, make body regions
21 and current detecting region 22 separate, can accurately detect sensed current.
In addition, the upper of semiconductor substrate 30 can be exposed to in unit 54 in work action cell 52 and current detecting
The region on surface forms p+The p of type+Region 36.In p+Doped with the impurity higher than the impurity concentration of base 34 in region 36.By
This, reduces the contact resistance between each unit and the grade electrode of source electrode 11.In addition, the base 34 in intermediate region 24, which has, is located at source
The region of the lower section of pole 11 and the region positioned at current detecting with the lower section of electrode 12.Base 34, under each electrode
P can be formed in the region of side+Region 36.Thereby, it is possible to reduce the contact resistance between base 34 and the grade of source electrode 11, and press down
The work of parasitic bipolar transistor in transistor unit processed.
The top of the base 34 in the region 24 formed between of field plate 72.Field plate 72 is by the polysilicon shape added with such as impurity
Into.Formed with the dielectric film 70 that thickness ratio gate insulating film 42 is thick between the upper surface of field plate 72 and semiconductor substrate 30.Separately
Outside, it is formed further with covering the interlayer dielectric 74 of field plate 72.
Field plate 72 can be endowed and source electrode 11 or grid (electrode portion 44) identical current potential.By the way that field plate 72 etc. is pressure-resistant
Structure is arranged on intermediate region 24 in a manner of surrounding current detecting region 22, can alleviate the electric field collection near intermediate region 24
In.
The groove 40 of this example has:The groove untill drift region 32 is reached from the upper surface of semiconductor substrate 30;Shape
Into the gate insulating film 42 on the inwall of groove;It is arranged on the electrode portion 44 covered in groove and by gate insulating film 42.
As one, gate insulating film 42 is the oxygen for forming the thermal oxide of semiconductor substrate 30 for the inwall for being exposed to groove
Change film.As one, polysilicon of the electrode portion 44 by being doped with impurity etc. is formed.The electrode portion 44 of this example and the grid shown in Fig. 1
Pole 13 electrically connects.According to the grid voltage being applied in electrode portion 44, raceway groove is formed in the base 34 opposed with electrode portion 44.By
This, has electric current flowing between the source region 38 and drift region 32 in work action cell 52 and current detecting unit 54.It is in addition, electric
Pole portion 44 and field plate 72 can be formed simultaneously.
In the case where semiconductor device 100 includes IGBT, a part of electrode portion 44 can be with (the hair in IGBT of source electrode 11
Emitter-base bandgap grading) electrical connection.The groove 40 being connected with source electrode 11 plays a role as illusory groove.Thereby, it is possible to produce carrier
Injection facilitation effect (IE effects) simultaneously reduces conducting voltage.
Work action cell 52 and current detecting of each groove 40 in the section are configured with unit 54 with identical interval.
Multiple grooves 40 can be formed in a manner of extending along the direction vertical with the section in striated.
In a part of the upper surface of semiconductor substrate 30 formed with gate insulating film 42.Wherein, the p in each unit+Area
Domain 36 and source region 38 are not covered by gate insulating film 42 at least in part.
In the upper surface of semiconductor substrate 30 and the upper surface of gate insulating film 42 formed with interlayer dielectric 26.Wherein,
So that the p in each unit+The mode that region 36 and source region 38 are exposed, in interlayer dielectric 26 formed with opening.In these openings
It is interior to be filled with source electrode 11 or current detecting electrode 12.
To be arranged alternately with equal intervals in the drift region 32 of body regions 21, current detecting region 22 and intermediate region 24
The tubing string 60 of p-type and the tubing string 62 of n-type.Tubing string 60 and tubing string 62 adjust impurity concentration and width in a manner of it can form superjunction
Degree.By such structure, because depletion layer transversely extends from the boundary of tubing string 60 and tubing string 62, even if improving n-type area
The impurity concentration in domain simultaneously declines conducting resistance, is also able to maintain that high withstand voltage.
In this example, tubing string 60 is formed as the downward side protrusion from the lower surface of the base 34 in each region.Between tubing string 60
Drift region 32 as tubing string 62 play function.The interval of each tubing string 60 is identical with the interval of each unit.Tubing string 60 is relative respectively
Formed in each work action cell 52 and each current detecting with unit 54.In addition, the downside of the base 34 in intermediate region 24
Also with body regions 21 and the identical interval of current detecting region 22 formed with tubing string 60., can be from 1 in intermediate region 24
Extend multiple tubing strings 60 in the lower surface of individual base 34.
In semiconductor device 100, in body regions 21, current detecting region 22 and intermediate region 24 with identical interval
It is configured with tubing string 60 and tubing string 62.Therefore, can be formed in body regions 21, current detecting region 22 and intermediate region 24 identical
The superjunction of structure.The impurity concentration phase of each tubing string of body regions 21, current detecting region 22 and the superjunction in intermediate region 24
Together.
Using such structure, the intermediate region 24 that body regions 21 and current detecting region 22 are separated and energy are set
Enough tubing strings 60 and tubing string 62 for configuring superjunction at uniform intervals.Therefore, the impurity of the p-type and n-type in superjunction is easily kept
Charge balance, and be able to maintain that pressure-resistant.
Fig. 3 is the figure of other for representing the A-A' sections in Fig. 1.In this example, in intermediate region 24 formed with each other
Multiple bases 34 of separation.Other structures are identical with the example shown in Fig. 2.
Each diode portions 58 being connected with the source electrode 11 and current detecting electrode 12 of the intermediate region 24 of this example have that
The base 34 of this separation.Formed with p in the base 34 of each diode portions 58+Region 36.At least a portion of each base 34 can
To form the region beyond the lower section of field plate 72.
In addition, the base 34 further separated is could be formed between the base 34 of each diode portions 58.Each base 34
It can also be formed by ion implanting and heat treatment.
Base 34 in intermediate region 24 with the identical interval of tubing string 60 to configure.In addition, in intermediate region 24, not
With source electrode 11 and current detecting p is not formed with any one base being connected 34 in electrode 12+Region 36.It is formed without p+
The base 34 in region 36 can be only fitted to the lower section of field plate 72.
Even if by such structure, the middle area that body regions 21 and current detecting region 22 are separated can be also set
Domain 24, and the tubing string 60 of superjunction and tubing string 62 are configured with the interval of equalization.Therefore, the p-type in superjunction is easily kept
With the charge balance of the impurity of n-type, it is able to maintain that pressure-resistant.
Fig. 4 is the figure of other for representing the A-A' sections in Fig. 1.In this example, it is connected with the intermediate region shown in Fig. 3
24 each base 34.By ion implanting and bumps have been diffuseed to form in the lower surface of the base 34 of this example.Wherein, intermediate region
The part that the downward side of 24 base 34 protrudes with the identical interval of tubing string 60 to be configured.
Even if by such structure, the middle area that body regions 21 and current detecting region 22 are separated can be also set
Domain 24, and the tubing string 60 of superjunction and tubing string 62 are configured with the interval of equalization.Therefore, the p-type in superjunction is easily kept
With the charge balance of the impurity of n-type, it is able to maintain that pressure-resistant.
Fig. 5 is by adjacent corner in the upper surface of the semiconductor device 100 shown in Fig. 1, current detecting electrode 12
The schematic diagram that is amplified of B portions.Fig. 5 is corresponding with the structure shown in Fig. 2.Fig. 5 represent groove 40, electrode portion 44, base 34,
Source region 38, p+Region 36, field plate 72, source electrode 11 and current detecting electrode 12, and omit other structures.
Multiple grooves 40 are in body regions 21 and current detecting region 22 along defined orientation between certain
Every configuration.The groove 40 of this example is not formed in intermediate region 24.Each groove 40 is arranged to extend along defined bearing of trend.
Mesa region between each groove 40 is formed with base 34.Wherein, in body regions 21 and electric current detection region
In domain 22, in the upper surface of semiconductor substrate 30, extend to form active area 38 and p along bearing of trend striated+Region 36.
Source region 38 and p can instead be made+Region 36 is alternatively formed along bearing of trend.
Intermediate region 24 is arranged on body regions 21 and electric current detection region in bearing of trend and the two directions of orientation
Between domain 22.The upper surface of semiconductor substrate 30 in intermediate region 24 has been formed about base 34, in semiconductor substrate 30
Upper surface top formed with field plate 72.Can be near the boundary in orientation, intermediate region 24 and other regions
Along bearing of trend formed with p+Region 36.
In addition, source region 38 is not formed in intermediate region 24.Thus, body regions 21, electric current in the direction of extension be present
In detection zone 22 and the mesa region of intermediate region 24, body regions 21 and the source region in current detecting region 22 38 are divided
From.In the mesa region that body regions 21, current detecting region 22 and intermediate region 24 be present, formed in current detecting electricity consumption
The length L1 of the intermediate region 24 of the downside of pole 12 can be more than the length L2 formed in the intermediate region 24 of the downside of source electrode 11.
Thereby, it is possible to reduce the area to be formed in the intermediate region 24 of the downside of source electrode 11.
Fig. 6 is to be put the upper surface of semiconductor device 100, current detecting with the B portions of the adjacent corner of electrode 12
Big schematic diagram.In the example of fig. 6, by field plate 72 with being embedded to work action cell 52 and electric current inspection via gate insulating film 42
The electrode portion 44 of the groove 40 of survey unit 54 is formed simultaneously.In addition, field plate 72 via gate insulating film 42 with being embedded to work
Action cell 52 and current detecting are with the electrode portion 44 of the groove 40 of unit 54 with the length direction of groove 40 (in figure
Bearing of trend) parallel side connects up.Other structures are identical with Fig. 5, can obtain the example identical effect with Fig. 5.
More than, using embodiment, the present invention is described, and protection scope of the present invention is not limited to above-mentioned embodiment party
Formula.Those skilled in the art can carry out various changes or improvement to above-mentioned embodiment.It was found from the record of claims,
Having carried out the embodiment of these changes or improvement can also be included within the scope of the present invention.
In addition, embodiments of the present invention, although describing with the He of gate insulating film 42 formed in the inwall of groove
The trench gate structure of the electrode portion 44 covered in groove 40 and by gate insulating film 42 is arranged on, but can also possess
The source region in base in the base that the superficial layer of semiconductor substrate optionally configures and optionally is configured, semiconductor-based
The surface configuration gate insulating film of plate simultaneously possesses the planar gate of electrode portion on gate insulating film.
In addition, flat shape is set to striated by base 34 and groove 40 as shown in Figure 5, Figure 6, but can also be by base
34 flat shape is set to island, and the flat shape of groove 40 is set into clathrate of the configuration between the island of base 34 simultaneously
Electrode portion 44 is set to clathrate.The flat shape of base can also be similarly arranged in above-mentioned planar gate
Island, the clathrate that the flat shape of electrode portion is arranged to configure in a manner of between the island for crossing over base.In addition, inciting somebody to action
In the case that base is formed as island, the flat shape of the tubing string of p-type is also configured as island.
Claims (9)
1. a kind of semiconductor device, it is characterised in that possess:
Semiconductor substrate;
Body regions, it includes forming the work action cell of more than 1 in the inside of the semiconductor substrate;
Current detecting region, it includes forming the current detecting unit of more than 1 in the inside of the semiconductor substrate;With
And
Intermediate region, its be arranged in the inside of the semiconductor substrate body regions and the current detecting region it
Between, and including pressure-resistance structure portion,
In the body regions, the current detecting region and the intermediate region, the tubing string and the 2nd conductivity type of the 1st conductivity type
Tubing string to be alternately arranged at equal intervals.
2. semiconductor device according to claim 1, it is characterised in that
The intermediate region has the field plate formed in the top of the semiconductor substrate.
3. semiconductor device according to claim 2, it is characterised in that the intermediate region with the body regions phase
Adjacent region and the region adjacent with the current detecting region are formed with diode portions.
4. semiconductor device according to claim 3, it is characterised in that in being internally formed for the semiconductor substrate:
The base of 1st conductivity type;And
Formed in the drift region of the 2nd conductivity type of the lower section of the base,
The body regions and the current detecting region have:
Multiple grooves, the multiple groove are formed as extending to the base from the upper surface of the semiconductor substrate
Downside, and configured with identical interval;And
The area with high mercury of 2nd conductivity type, the top of its base formed in the region between each groove,
The area with high mercury is not formed in the intermediate region.
5. semiconductor device according to claim 4, it is characterised in that the diode adjacent with the body regions
Portion and the diode portions adjacent with the current detecting region have the common base.
6. semiconductor device according to claim 4, it is characterised in that the diode adjacent with the body regions
Portion and the diode portions adjacent with the current detecting region have the base separated.
7. semiconductor device according to claim 6, it is characterised in that the intermediate region with the body regions phase
The base of the adjacent diode portions and the base of the diode portions adjacent with the current detecting region it
Between also have separation the base.
8. the semiconductor device according to any one of claim 3~7, it is characterised in that be also equipped with:
Upper surface side electrode, it is formed in the top at least one of region of the body regions;And
Current detecting electrode, it is formed in the top at least one of region in the current detecting region,
The diode portions adjacent with the body regions are connected with the upper surface side electrode,
The diode portions adjacent with the current detecting region are connected with the current detecting with electrode.
9. semiconductor device according to claim 1, it is characterised in that in the body regions, the electric current detection region
In domain and the intermediate region, the tubing string of the 1st conductivity type is identical with the impurity concentration of the tubing string of the 2nd conductivity type.
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Cited By (4)
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Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US10312710B1 (en) * | 2017-01-31 | 2019-06-04 | The United States Of America, As Represented By The Secretary Of The Navy | Energy recovery pulse forming network |
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JP7425943B2 (en) * | 2019-12-12 | 2024-02-01 | 株式会社デンソー | silicon carbide semiconductor device |
EP3863062A1 (en) * | 2020-02-07 | 2021-08-11 | Infineon Technologies Austria AG | Semiconductor transistor device and method of manufacturing the same |
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US11410990B1 (en) * | 2020-08-25 | 2022-08-09 | Semiq Incorporated | Silicon carbide MOSFET with optional asymmetric gate clamp |
EP4181212A1 (en) * | 2021-11-11 | 2023-05-17 | Infineon Technologies Dresden GmbH & Co . KG | Semiconductor device |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10326897A (en) * | 1997-03-25 | 1998-12-08 | Hitachi Ltd | Trench gate semiconductor device with current-detecting cell |
US20060289915A1 (en) * | 2005-06-20 | 2006-12-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20110297934A1 (en) * | 2009-02-17 | 2011-12-08 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
US20120211833A1 (en) * | 2011-02-17 | 2012-08-23 | Fuji Electric Co., Ltd. | Super-junction semiconductor device |
CN103650141A (en) * | 2011-07-22 | 2014-03-19 | 富士电机株式会社 | Super-junction semiconductor device |
JP2014063907A (en) * | 2012-09-21 | 2014-04-10 | Toshiba Corp | Power semiconductor device |
CN103996704A (en) * | 2014-05-13 | 2014-08-20 | 无锡新洁能股份有限公司 | IGBT with precise detection function and manufacturing method thereof |
US20150097233A1 (en) * | 2013-10-04 | 2015-04-09 | Infineon Technologies Ag | Semiconductor Device and Method of Manufacturing the Same |
US20150270387A1 (en) * | 2014-03-19 | 2015-09-24 | Fuji Electric Co., Ltd. | Trench mos semiconductor device |
CN104969348A (en) * | 2013-01-31 | 2015-10-07 | 株式会社电装 | Silicon carbide semiconductor device |
US20160056138A1 (en) * | 2014-08-19 | 2016-02-25 | Vishay-Siliconix | Vertical sense devices in vertical trench mosfet |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3338185B2 (en) | 1994-08-02 | 2002-10-28 | 株式会社東芝 | Semiconductor device |
JP4564516B2 (en) * | 2007-06-21 | 2010-10-20 | 株式会社東芝 | Semiconductor device |
DE112009000253B8 (en) | 2008-01-29 | 2020-06-10 | Denso Corporation | Semiconductor device |
JP2010219258A (en) | 2009-03-17 | 2010-09-30 | Toyota Motor Corp | Semiconductor device |
JP5447504B2 (en) | 2009-03-24 | 2014-03-19 | トヨタ自動車株式会社 | Semiconductor device |
JP5417440B2 (en) * | 2009-05-28 | 2014-02-12 | トヨタ自動車株式会社 | Semiconductor device |
JP5526849B2 (en) | 2010-02-18 | 2014-06-18 | 富士電機株式会社 | Semiconductor device |
US8411471B2 (en) * | 2010-06-18 | 2013-04-02 | Infineon Technologies Ag | Electronic circuit and semiconductor arrangement with a load, a sense and a start-up transistor |
JP5779025B2 (en) | 2010-11-08 | 2015-09-16 | 株式会社東芝 | Semiconductor device |
US9076805B2 (en) * | 2012-07-14 | 2015-07-07 | Infineon Technologies Ag | Current sense transistor with embedding of sense transistor cells |
JP5991435B2 (en) * | 2013-07-05 | 2016-09-14 | 富士電機株式会社 | Semiconductor device |
US9543858B2 (en) * | 2013-07-10 | 2017-01-10 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device and inverter using same |
-
2016
- 2016-08-10 JP JP2016157328A patent/JP6805620B2/en active Active
-
2017
- 2017-06-29 US US15/636,674 patent/US10157911B2/en active Active
- 2017-06-30 CN CN201710519874.1A patent/CN107731911B/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10326897A (en) * | 1997-03-25 | 1998-12-08 | Hitachi Ltd | Trench gate semiconductor device with current-detecting cell |
US20060289915A1 (en) * | 2005-06-20 | 2006-12-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20110297934A1 (en) * | 2009-02-17 | 2011-12-08 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
US20120211833A1 (en) * | 2011-02-17 | 2012-08-23 | Fuji Electric Co., Ltd. | Super-junction semiconductor device |
CN103650141A (en) * | 2011-07-22 | 2014-03-19 | 富士电机株式会社 | Super-junction semiconductor device |
JP2014063907A (en) * | 2012-09-21 | 2014-04-10 | Toshiba Corp | Power semiconductor device |
CN104969348A (en) * | 2013-01-31 | 2015-10-07 | 株式会社电装 | Silicon carbide semiconductor device |
US20150097233A1 (en) * | 2013-10-04 | 2015-04-09 | Infineon Technologies Ag | Semiconductor Device and Method of Manufacturing the Same |
US20150270387A1 (en) * | 2014-03-19 | 2015-09-24 | Fuji Electric Co., Ltd. | Trench mos semiconductor device |
CN103996704A (en) * | 2014-05-13 | 2014-08-20 | 无锡新洁能股份有限公司 | IGBT with precise detection function and manufacturing method thereof |
US20160056138A1 (en) * | 2014-08-19 | 2016-02-25 | Vishay-Siliconix | Vertical sense devices in vertical trench mosfet |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108878305A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | The resistance to voltage verification method of the terminal structure of superjunction devices |
CN108878305B (en) * | 2018-06-29 | 2020-09-25 | 上海华虹宏力半导体制造有限公司 | Withstand voltage verification method for terminal structure of super junction device |
CN111370477A (en) * | 2018-12-25 | 2020-07-03 | 上海新微技术研发中心有限公司 | Insulated gate bipolar transistor with overcurrent limiting function and construction method thereof |
CN111370477B (en) * | 2018-12-25 | 2022-05-17 | 上海睿驱微电子科技有限公司 | Insulated gate bipolar transistor with overcurrent limiting function and construction method thereof |
CN113130639A (en) * | 2019-12-31 | 2021-07-16 | 比亚迪半导体股份有限公司 | IGBT device of integrated current detection structure and preparation method |
CN113659011A (en) * | 2021-10-19 | 2021-11-16 | 茂睿芯(深圳)科技有限公司 | Integrated device based on super junction MOSFET and manufacturing method thereof |
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US10157911B2 (en) | 2018-12-18 |
US20180047722A1 (en) | 2018-02-15 |
JP2018026450A (en) | 2018-02-15 |
CN107731911B (en) | 2022-03-04 |
JP6805620B2 (en) | 2020-12-23 |
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