CN107707248B - exclusive-OR gate circuit, adjusting method and exclusive-OR gate circuit - Google Patents
exclusive-OR gate circuit, adjusting method and exclusive-OR gate circuit Download PDFInfo
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- CN107707248B CN107707248B CN201711060698.6A CN201711060698A CN107707248B CN 107707248 B CN107707248 B CN 107707248B CN 201711060698 A CN201711060698 A CN 201711060698A CN 107707248 B CN107707248 B CN 107707248B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors
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Abstract
The embodiment of the invention provides an exclusive-or gate circuit, an adjusting method and an exclusive-or gate circuit, and relates to the technical field of logic circuits. The exclusive-OR gate circuit comprises a first input module, a second input module, an output module and a delay module. The input end of the first input module is used for being electrically connected with the first signal source, the first output end of the first input module is electrically connected with the first end of the delay module, and the second output end of the first input module is electrically connected with one end of the output module. The input end of the second input module is used for being electrically connected with a second signal source, and the output end of the second input module is electrically connected with the second end of the delay module. The third end of the delay module is electrically connected with the other end of the output module. The delay module is used for delaying the first signal by T time when the first signal is ahead of the second signal by T time, so that the first signal after the delay T time is synchronous with the second signal, and an output signal is obtained from the other end of the output module. To overcome the problem of glitches in the output signal.
Description
Technical Field
The invention relates to the technical field of logic circuits, in particular to an exclusive or gate circuit, an adjusting method and an exclusive or gate circuit.
Background
An exclusive nor gate (XNOR gate or equivalence gate) is also called an exclusive nor gate, and is a basic unit of a digital logic circuit, and has 2 input terminals and 1 output terminal. When one and only one of the 2 inputs is low (logic 0), the output is low. I.e. when the input levels are the same, the output is high (logic 1). The current nor gate has some drawbacks, such as the ti chip SN54LS266 nor gate chip, i.e. the output signal of the nor gate chip may have a glitch phenomenon.
Disclosure of Invention
The present invention is directed to an exclusive or gate, an adjusting method and an exclusive or gate for improving the above-mentioned problems. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
in a first aspect, an embodiment of the present invention provides an exclusive or gate circuit, including a first input module, a second input module, an output module, and a delay module. The input end of the first input module is used for being electrically connected with a first signal source, the first output end of the first input module is electrically connected with the first end of the delay module, and the second output end of the first input module is electrically connected with one end of the output module. The input end of the second input module is used for being electrically connected with a second signal source, and the output end of the second input module is electrically connected with the second end of the delay module. And the third end of the delay module is electrically connected with the other end of the output module. The first signal source is used for outputting a first signal, and the second signal source is used for outputting a second signal. The delay module is used for delaying the first signal by a time T when the first signal is ahead of the second signal by the time T, so that the first signal after the time T is synchronous with the second signal, and an output signal is obtained from the other end of the output module.
Further, the first input module includes a first resistor and a first triode. One end of the first resistor is electrically connected to the first signal source, and the other end of the first resistor is electrically connected to the base electrode of the first triode. The emitter of the first triode is electrically connected with the first end of the delay module, and the collector of the first triode is electrically connected with one end of the output module.
Further, the second input module includes a second resistor and a second triode. One end of the second resistor is electrically connected to the second signal source, and the other end of the second resistor is electrically connected to the base electrode of the second triode. And the collector electrode of the second triode is grounded, and the emitter electrode of the second triode is electrically connected with the second end of the delay module.
Further, the delay module comprises a first capacitor and a third triode. One end of the first capacitor is electrically connected to the base electrode of the third triode, and the other end of the first capacitor is electrically connected to the emitter electrode of the third triode. The base electrode of the third triode is electrically connected with the emitter electrode of the first triode, the emitter electrode of the third triode is electrically connected with the emitter electrode of the second triode, and the collector electrode of the third triode is electrically connected with the other end of the output module.
Further, the first triode and the third triode are NPN triodes. The second triode is a PNP triode.
Further, the output module includes a third resistor and a fourth resistor. One end of the third resistor is electrically connected to the collector of the first triode, and the other end of the third resistor is electrically connected to one end of the fourth resistor. The other end of the fourth resistor is electrically connected to the collector electrode of the third triode, and the other end of the fourth resistor outputs an output signal.
Further, the exclusive or gate circuit further includes a power supply. The other end of the third resistor and one end of the fourth resistor are electrically connected to the power supply.
In a second aspect, an embodiment of the present invention provides an adjustment method, which is applied to the xor gate circuit, and the method includes: when the first signal is advanced by a time T from the second signal, acquiring a capacitance value of the first capacitor corresponding to the time T; when the first triode is conducted, the first capacitor corresponding to the capacitance value starts to charge so as to delay the high level of the first signal by T time, so that the first signal after the delay of T time is synchronous with the second signal, and an output signal is obtained from the other end of the output module.
Further, based on t=rc×ln [ (V1-V0)/(V1-Vt) ], a capacitance value of the first capacitor corresponding to the T time is obtained, where T is the T time, R is a resistance between the base and the emitter of the third triode, C is the capacitance value, V1 is a voltage of the emitter of the first triode, V0 is an initial voltage of the first capacitor, and Vt is a preset threshold voltage.
In a third aspect, an embodiment of the present invention provides an exclusive or gate circuit, including an not gate circuit and an exclusive or gate circuit described above. And the NOT gate circuit is electrically connected with the other end of the output module of the exclusive OR gate circuit.
The embodiment of the invention provides an exclusive-or gate circuit, an adjusting method and an exclusive-or gate circuit. The input end of the first input module is used for being electrically connected with a first signal source, the first output end of the first input module is electrically connected with the first end of the delay module, and the second output end of the first input module is electrically connected with one end of the output module. The input end of the second input module is used for being electrically connected with a second signal source, and the output end of the second input module is electrically connected with the second end of the delay module. And the third end of the delay module is electrically connected with the other end of the output module. The first signal source is used for outputting a first signal, and the second signal source is used for outputting a second signal. The delay module is used for delaying the first signal by a time T when the first signal is ahead of the second signal by the time T, so that the first signal after the time T is synchronous with the second signal, and an output signal is obtained from the other end of the output module. By setting the delay module, when the first signal is ahead of the second signal by a time T, the first signal is delayed by the time T, so that the first signal after the time T is synchronous with the second signal, and an output signal is obtained from the other end of the output module, so that the problem of burrs of the output signal is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is an application environment of an embodiment of the present invention;
FIG. 2 is a block diagram of an exclusive OR gate circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of signals with burrs according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of signals in an XOR circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an XOR gate circuit according to an embodiment of the present invention;
FIG. 6 is a truth representation of an exclusive OR gate according to an embodiment of the present invention;
fig. 7 is a block diagram of an exclusive or gate according to an embodiment of the present invention.
In the figure: a 100-exclusive-OR gate circuit; 110-a first input module; 120-a second input module; 130-an output module; 140-a delay module; a 200-exclusive-OR gate; 210-not gate.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "electrically connected," and "electrically connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically and electrically connected or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, an exclusive or gate 100 according to an embodiment of the present invention may include a first input module 110, a second input module 120, an output module 130, and a delay module 140. The input end of the first input module 110 is electrically connected to the first signal source S1, the first output end of the first input module 110 is electrically connected to the first end of the delay module 140, and the second output end of the first input module 110 is electrically connected to one end of the output module 130. An input end of the second input module 120 is electrically connected to the second signal source S2, and an output end of the second input module 120 is electrically connected to the second end of the delay module 140. A third terminal of the delay module 140 is electrically connected to the other terminal of the output module 130. The first signal source S1 is configured to output a first signal A1. The second signal source S2 is configured to output a second signal A2. The delay module 140 is configured to delay the first signal A1 by a time T when the first signal A1 is ahead of the second signal A2 by a time T, so that the first signal A1 after the time T is synchronous with the second signal A2 to obtain an output signal from the other end of the output module 130.
Further, referring to fig. 1 and 2 in combination, the first input module 110 may include a first resistor R1 and a first transistor Q1. One end of the first resistor R1 is electrically connected to the first signal source S1, and the other end of the first resistor R1 is electrically connected to the base B of the first triode Q1. The emitter E of the first triode Q1 is electrically connected to the first end of the delay module 140, and the collector C of the first triode Q1 is electrically connected to one end of the output module 130.
Further, referring to fig. 1 and 2 in combination, the second input module 120 may include a second resistor R2 and a second transistor Q2. One end of the second resistor R2 is electrically connected to the second signal source S2, and the other end of the second resistor R2 is electrically connected to the base of the second triode Q2. The collector C of the second triode Q2 is grounded, and the emitter E of the second triode Q2 is electrically connected to the second end of the delay module 140.
Further, the delay module 140 may include a first capacitor C1 and a third transistor Q3. One end of the first capacitor C1 is electrically connected to the base B of the third triode Q3, and the other end of the first capacitor C1 is electrically connected to the emitter E of the third triode Q3. The base B of the third triode Q3 is electrically connected to the emitter E of the first triode Q1, the emitter E of the third triode Q3 is electrically connected to the emitter E of the second triode Q2, and the collector C of the third triode Q3 is electrically connected to the other end of the output module 130.
Further, the output module 130 may include a third resistor R3 and a fourth resistor R4. One end of the third resistor R3 is electrically connected to the collector C of the first triode Q1, and the other end of the third resistor R3 is electrically connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is electrically connected to the collector C of the third triode Q3, and the other end of the fourth resistor R4 outputs an output signal.
Referring to fig. 2-4 in combination, A1 is a first signal and A2 is a second signal, in actual operation, the inventor uses ti chip SN54LS266 nor gate chip to realize the same or function, and finds that when two identical waves have front-to-back time differences, the output signal obtained by the ti chip will have a glitch phenomenon such as the glitch identified in the Y0 signal in fig. 3, so that the inventor improves the above problem by delaying the faster signal and synchronizing the faster signal with the slower signal. In this embodiment, when the first signal A1 is advanced by a time T from the second signal A2, a capacitance value of the first capacitor C1 corresponding to the time T is obtained; when the first triode Q1 is turned on, the first capacitor C1 corresponding to the capacitance value starts to be charged, so as to delay the high level of the first signal A1 by a time T, so that the first signal A1 after the time T is synchronous with the second signal A2, so as to obtain an output signal Y from the other end of the output module 130, as shown in fig. 4, the first signal A1 and the second signal A2 are synchronous, and no glitch phenomenon occurs in the output signal Y. Further, given a preset time delay T, calculating t=rc×ln [ (V1-V0)/(V1-Vt) ], and obtaining a capacitance value of the first capacitor corresponding to the T time, where T is the T time, R is a resistance between the base and the emitter of the third triode, C is the capacitance value, V1 is a voltage of the emitter of the first triode, V0 is an initial voltage of the first capacitor, and Vt is a preset threshold voltage. The preset threshold voltage may be 0.8V. Ln represents taking the logarithm. Therefore, different time delay T times are realized, and the first capacitors corresponding to different capacitance values are selected to realize different time delay.
Referring to fig. 2, the second signal A2 includes a first signal A1 and an output signal Y, so as to filter the A1 signal in the A2 signal to obtain a pure Y signal. The detailed steps are as follows:
1) The signals A1 and A2 are at high level at the same time, Q1 is conducted, Q2 and Q3 are cut off, and Y outputs high level;
2) The signals A1 and A2 are simultaneously low level, Q2 is conducted, Q1 and Q3 are cut off, and Y outputs high level;
3) A1 is high level, A2 is low level, Q1, Q2 and Q3 are conducted, and Y outputs low level;
4) Since A2 contains the signal in A1, it does not occur that A1 is low and A2 is high. Thus, the exclusive nor circuit 100 implements the exclusive nor function without the glitch phenomenon, as shown in the symbol diagram of fig. 5, y=a+.b, a and B are two INPUTS respectively, Y is an OUTPUT, the logic function corresponds to the truth table of fig. 6, input is A, B, OUTPUT is Y, L is low, and H is high.
Further, the first triode Q1 and the third triode Q3 may be NPN triodes. The second transistors Q2 may be PNP transistors.
In an embodiment of the present invention, the types of the first transistor Q1 and the third transistor Q3 may be, but are not limited to, 8050. The second transistor Q2 may be, but is not limited to, 8550. The resistance value of the first resistor R1 may be, but is not limited to, 1.5mΩ. The resistance of the second resistor R2 may be, but is not limited to, 12kΩ. The resistance of the third resistor R3 may be, but is not limited to, 2.2kΩ. The resistance of the fourth resistor R4 may be, but is not limited to, 5.1kΩ. For example, the capacitance value of the first capacitor C1 may be 10nF for the time delay T.
Further, referring to fig. 2, the or gate 100 may further include a power supply VCC. The other end of the third resistor R3 and one end of the fourth resistor R4 are electrically connected to the power supply VCC. For example, the power supply VCC may be a 5V power supply.
The working principle of the exclusive or gate circuit 100 provided in the embodiment of the present invention is as follows:
the first signal source S1 outputs a first signal. The second signal source S2 outputs a second signal. When the first signal A1 is advanced by a time T from the second signal A2, acquiring a capacitance value of the first capacitor C1 corresponding to the time T; when the first triode Q1 is turned on, the first capacitor C1 corresponding to the capacitance value starts to be charged, so as to delay the high level of the first signal A1 by a time T, so that the first signal A1 after the time T is synchronous with the second signal A2, and an output signal Y is obtained from the other end of the output module 130.
An embodiment of the present invention provides an exclusive or gate 100, which may include a first input module 110, a second input module 120, an output module 130, and a delay module 140. The input end of the first input module 110 is electrically connected to the first signal source S1, the first output end of the first input module 110 is electrically connected to the first end of the delay module 140, and the second output end of the first input module 110 is electrically connected to one end of the output module 130. An input end of the second input module 120 is electrically connected to the second signal source S2, and an output end of the second input module 120 is electrically connected to the second end of the delay module 140. A third terminal of the delay module 140 is electrically connected to the other terminal of the output module 130. The first signal source S1 is configured to output a first signal. The second signal source S2 is configured to output a second signal. The delay module 140 is configured to delay the first signal by a time T when the first signal is ahead of the second signal by a time T, so that the first signal after the time T is synchronized with the second signal to obtain an output signal from the other end of the output module 130. By setting the delay module, when the first signal is ahead of the second signal by a time T, the first signal is delayed by the time T, so that the first signal after the time T is synchronous with the second signal, and an output signal is obtained from the other end of the output module, so that the problem of burrs of the output signal is solved.
The embodiment of the invention provides an adjusting method which is applied to an exclusive-or gate circuit, and the method can comprise the following steps: when the first signal is advanced by a time T from the second signal, acquiring a capacitance value of the first capacitor corresponding to the time T; when the first triode is conducted, the first capacitor corresponding to the capacitance value starts to charge so as to delay the high level of the first signal by T time, so that the first signal after the delay of T time is synchronous with the second signal, and an output signal is obtained from the other end of the output module.
Further, based on t=rc×ln [ (V1-V0)/(V1-Vt) ], a capacitance value of the first capacitor corresponding to the T time is obtained, where T is the T time, R is a resistance between the base and the emitter of the third triode, C is the capacitance value, V1 is a voltage of the emitter of the first triode, V0 is an initial voltage of the first capacitor, and Vt is a preset threshold voltage.
It will be clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the adjusting method described above may refer to the corresponding process in the embodiment of the xor gate, which is not described herein again.
The adjusting method provided by the embodiment of the invention is applied to the exclusive-or gate circuit, and comprises the following steps: when the first signal is advanced by a time T from the second signal, acquiring a capacitance value of the first capacitor corresponding to the time T; when the first triode is conducted, the first capacitor corresponding to the capacitance value starts to charge so as to delay the high level of the first signal by T time, so that the first signal after the delay of T time is synchronous with the second signal, and an output signal is obtained from the other end of the output module.
Referring to fig. 7, an exclusive or gate 200 according to an embodiment of the present invention may include a nor gate 210 and the exclusive or gate 100. The not gate 210 is electrically connected to the other end of the output module 130 of the nor gate 100.
It will be clear to those skilled in the art that, for convenience and brevity of description, the specific operation of the xor circuit described above may refer to the corresponding process in the embodiment of the xor circuit described above, and will not be described in detail herein.
An exclusive or gate 200 according to an embodiment of the present invention may include an nor gate 210 and the exclusive or gate 100. The not circuit 210 is electrically connected to the other end of the output module 130 of the nor circuit 100, so as to overcome the problem of glitch occurring in the output signal.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The exclusive-or gate circuit is characterized by comprising a first input module, a second input module, an output module and a delay module, wherein the input end of the first input module is electrically connected with a first signal source, the first output end of the first input module is electrically connected with the first end of the delay module, the second output end of the first input module is electrically connected with one end of the output module, the input end of the second input module is electrically connected with a second signal source, the output end of the second input module is electrically connected with the second end of the delay module, and the third end of the delay module is electrically connected with the other end of the output module;
the first signal source is used for outputting a first signal, and the second signal source is used for outputting a second signal;
the delay module is used for delaying the first signal by a time T when the first signal is ahead of the second signal by the time T, so that the first signal after the time T is synchronous with the second signal, and an output signal is obtained from the other end of the output module.
2. The nor gate circuit of claim 1 wherein said first input module includes a first resistor and a first transistor, one end of said first resistor being electrically connected to said first signal source, the other end of said first resistor being electrically connected to a base of said first transistor, an emitter of said first transistor being electrically connected to a first end of said delay module, and a collector of said first transistor being electrically connected to an end of said output module.
3. The nor gate circuit of claim 2 wherein said second input module includes a second resistor and a second transistor, one end of said second resistor being electrically connected to said second signal source, the other end of said second resistor being electrically connected to the base of said second transistor, the collector of said second transistor being grounded, and the emitter of said second transistor being electrically connected to the second end of said delay module.
4. The nor gate circuit of claim 3 wherein the delay module includes a first capacitor and a third transistor, one end of the first capacitor is electrically connected to a base of the third transistor, the other end of the first capacitor is electrically connected to an emitter of the third transistor, the base of the third transistor is electrically connected to the emitter of the first transistor, the emitter of the third transistor is electrically connected to the emitter of the second transistor, and a collector of the third transistor is electrically connected to the other end of the output module.
5. The nor gate circuit of claim 4 wherein said first transistor and said third transistor are NPN transistors and said second transistor is a PNP transistor.
6. The nor gate circuit of claim 4 wherein said output module includes a third resistor and a fourth resistor, one end of said third resistor being electrically connected to the collector of said first transistor, the other end of said third resistor being electrically connected to one end of said fourth resistor, the other end of said fourth resistor being electrically connected to the collector of said third transistor, the other end of said fourth resistor outputting an output signal.
7. The exclusive-or gate of claim 6, further comprising a power supply, wherein the other end of the third resistor and the one end of the fourth resistor are electrically connected to the power supply.
8. A method of regulation applied to an exclusive or gate circuit as claimed in any one of claims 4 to 7, the method comprising:
when the first signal is advanced by a time T from the second signal, acquiring a capacitance value of the first capacitor corresponding to the time T;
when the first triode is conducted, the first capacitor corresponding to the capacitance value starts to charge so as to delay the high level of the first signal by T time, so that the first signal after the delay of T time is synchronous with the second signal, and an output signal is obtained from the other end of the output module.
9. The method of claim 8, wherein the obtaining the capacitance value of the first capacitor corresponding to the T time comprises:
based on t=rc×ln [ (V1-V0)/(V1-Vt) ], obtaining a capacitance value of the first capacitor corresponding to the T time, where T is the T time, R is a resistance between the base and the emitter of the third triode, C is the capacitance value, V1 is a voltage of the emitter of the first triode, V0 is an initial voltage of the first capacitor, and Vt is a preset threshold voltage.
10. An exclusive or gate circuit comprising an nor gate circuit and an exclusive or gate circuit as claimed in any one of claims 1 to 7, the nor gate circuit being electrically connected to the other end of an output module of the exclusive or gate circuit.
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| CN108900181B (en) * | 2018-07-02 | 2022-07-29 | 天津芯海创科技有限公司 | Clock delay adjusting device and clock delay adjusting system |
| CN110176926B (en) * | 2019-06-25 | 2023-01-10 | 京东方科技集团股份有限公司 | OR gate circuit, gate drive circuit and display panel |
| CN112491411B (en) * | 2020-12-01 | 2023-07-04 | 电子科技大学 | exclusive-OR gate circuit for reducing delay of NAND gate input signal |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201796589U (en) * | 2010-08-27 | 2011-04-13 | 青岛海信电器股份有限公司 | Time sequence conversion circuit and television |
| CN202931272U (en) * | 2012-10-29 | 2013-05-08 | Tcl通力电子（惠州）有限公司 | Electronic device and signal one-out-of-two circuit thereof |
| CN203027519U (en) * | 2012-12-03 | 2013-06-26 | 美的集团股份有限公司 | IGBT (Insulated Gate Bipolar Transistor) driving device for electromagnetic heating system |
| CN105739662A (en) * | 2014-12-11 | 2016-07-06 | 鸿富锦精密工业（深圳）有限公司 | Power control circuit |
| CN106375690A (en) * | 2016-11-18 | 2017-02-01 | 歌尔科技有限公司 | Pop sound elimination circuit |
| CN106877851A (en) * | 2017-04-14 | 2017-06-20 | 深圳怡化电脑股份有限公司 | A kind of sensor delay control circuit |
| CN207603610U (en) * | 2017-11-01 | 2018-07-10 | 成都声立德克技术有限公司 | With OR circuit and NOR gate circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7092474B2 (en) * | 2001-09-18 | 2006-08-15 | Broadcom Corporation | Linear phase detector for high-speed clock and data recovery |
| US20140218084A1 (en) * | 2013-02-06 | 2014-08-07 | Nvidia Corporation | Approach to clock frequency modulation of a fixed frequency clock source |
-
2017
- 2017-11-01 CN CN201711060698.6A patent/CN107707248B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201796589U (en) * | 2010-08-27 | 2011-04-13 | 青岛海信电器股份有限公司 | Time sequence conversion circuit and television |
| CN202931272U (en) * | 2012-10-29 | 2013-05-08 | Tcl通力电子（惠州）有限公司 | Electronic device and signal one-out-of-two circuit thereof |
| CN203027519U (en) * | 2012-12-03 | 2013-06-26 | 美的集团股份有限公司 | IGBT (Insulated Gate Bipolar Transistor) driving device for electromagnetic heating system |
| CN105739662A (en) * | 2014-12-11 | 2016-07-06 | 鸿富锦精密工业（深圳）有限公司 | Power control circuit |
| CN106375690A (en) * | 2016-11-18 | 2017-02-01 | 歌尔科技有限公司 | Pop sound elimination circuit |
| CN106877851A (en) * | 2017-04-14 | 2017-06-20 | 深圳怡化电脑股份有限公司 | A kind of sensor delay control circuit |
| CN207603610U (en) * | 2017-11-01 | 2018-07-10 | 成都声立德克技术有限公司 | With OR circuit and NOR gate circuit |
Non-Patent Citations (2)
| Title |
|---|
| Controllable all-optical stochastic logic gates and their delay storages based on the cascaded VCSELs with optical-injection;钟东洲;罗伟;许葛亮;;Chinese Physics B(第09期);251-256 * |
| 基于单个半导体光放大器的高速多功能逻辑门;董建绩;张新亮;王阳;黄德修;;物理学报(04);195-201 * |
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