CN107706192B - A kind of preparation method and its structure of three-dimensional storage - Google Patents

A kind of preparation method and its structure of three-dimensional storage Download PDF

Info

Publication number
CN107706192B
CN107706192B CN201710724653.8A CN201710724653A CN107706192B CN 107706192 B CN107706192 B CN 107706192B CN 201710724653 A CN201710724653 A CN 201710724653A CN 107706192 B CN107706192 B CN 107706192B
Authority
CN
China
Prior art keywords
dimensional storage
preparation
etching
silicon nitride
lamination structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710724653.8A
Other languages
Chinese (zh)
Other versions
CN107706192A (en
Inventor
李广济
徐强
邵明
宋豪杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN201710724653.8A priority Critical patent/CN107706192B/en
Publication of CN107706192A publication Critical patent/CN107706192A/en
Application granted granted Critical
Publication of CN107706192B publication Critical patent/CN107706192B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

Landscapes

  • Semiconductor Memories (AREA)

Abstract

The preparation method and its structure of a kind of three-dimensional storage provided by the invention, using be etched back to technique by etches both silicon nitride layer in former silicon dioxide layer inverse growth silica membrane remove, to expose the surface of the silicon dioxide layer in former multilayer lamination structure, enough spaces are provided for subsequent deposition metal gate.The thickness of metal gate can achieve expected thickness, effectively improve the resistance of metal gate, improve the performance and stability of device.

Description

A kind of preparation method and its structure of three-dimensional storage
Technical field
The present invention relates to the preparation method of semiconductor devices and its manufacturing field more particularly to a kind of three-dimensional storage and its Structure.
Background technique
Continuous improvement with the market demand to memory capacity, traditional memory based on plane or two-dimensional structure exist Available number of memory cells is already close to the limit in unit area, can not further satisfaction market to larger capacity memory Demand.Just as the several one-storey houses established in one piece of limited plane, these one-storey house proper alignments, but with demand Be continuously increased, the continuous blowout of the quantity of one-storey house, can the plane of this final block limited area can only accommodate a certain number of one-storey houses And it can not continue growing.The memory of planar structure has been approached its practical extended limit, brings sternly to semiconductor memory industry High challenge.
In order to solve the above difficulties, industry proposes the concept of three-dimensional storage (3D NAND), is a kind of emerging sudden strain of a muscle Type is deposited, 2D or the limitation of plane nand flash memory bring are solved by the way that memory grain is stacked.Different from that will deposit Storage chip is placed on single side, new 3D NAND technology, and vertical stacking multi-layer data storage unit has brilliant precision.Base In the technology, the storage equipment that memory capacity is up to several times than similar NAND technology can be created.The technology can be supported smaller Space content receive more high storage capacity, and then very big cost savings, energy consumption is brought to reduce, and significantly performance boost with Meet numerous consumer mobile devices comprehensively and requires the demand of most harsh enterprise's deployment.Enable particle using new technology Enough carry out three-dimensional stacking, thus solve due to wafer physics limit and can not further expansion single-chip active volume Limitation, in the case where same volume size, is greatly improved the content volume of memory particle single-chip, further pushes Storage particle population size rises violently.
Formed three-dimensional storage storage array vertical stack, as shown in Figure 1-3, need first on the substrate 10 according to The secondary repetition laminated construction 13 for forming multilayer silicon nitride 11 and silica 12, then removes silicon nitride layer by wet etching 11, metal is filled to form 15 structure of metal gate in the vacancy 14 then left after getting rid of silicon nitride layer.
The technique of wet etching silicon nitride layer generally uses the phosphoric acid solution of high etching selectivity, and this phosphoric acid solution is to nitrogen The etch-rate of SiClx is very high, and is almost zero to the etch-rate of silica.This mainly passes through the erosion to silica Carve what reaction was realized with inverse growth reaction holding balance.Presently, there are some technical problems, such as the phosphorus of high etching selectivity Acid solution will appear the inverse growth of silica in etching reaction, and the silica of this inverse growth is liable to stick to former dioxy The surface of SiClx layer, makes silicon dioxide layer thicken.Although board has compensation concentration function immediately, due to the lag of compensation Property, it still will appear the excessive inverse growth of silica.
Since wet etching process is a reversible chemical reaction, the etch rate and inverse growth rate of silica are protected Maintain an equal level weighing apparatus, and as the silicon ion concentration of reaction carried out in solution rises, the rate of inverse growth rises, silicon ion and oxonium ion knot Conjunction forms silica, and this silica is attached in original silicon dioxide layer, increases the thickness of dioxide layer, thus Cause the thickness for leaving metal gate for reduce, reduces the electric property of metal gate.As shown in figure 3, in figure arrow meaning position For the silica of inverse growth, the thickness of former silicon dioxide layer is increased, thus to the space for the metal gate being subsequently formed Become smaller, cause the thickness of metal gate to reduce than expected, and then increase the resistance of metal gate, influences the performance of device and steady It is qualitative.
Summary of the invention
The object of the invention is to, provide how to eliminate dioxy in silicon nitride wet etch process in order to solve problem above The excessive inverse growth of SiClx provides enough spaces for subsequent deposition metal gate.The purpose of the present invention is pass through following technical side What case was realized.
A kind of preparation method of three-dimensional storage, which comprises the steps of:
One substrate is provided, forms the array memory block of three-dimensional storage on the substrate;
The display memory block includes the multiple-level stack that silicon nitride layer and silicon dioxide layer are alternatively formed on the substrate Structure;
The silicon nitride layer in the multilayer lamination structure is removed using wet-etching technology;
In the silicon nitride layer in the removal multilayer lamination structure the step of, in the titanium dioxide of multilayer lamination structure The surface of silicon layer is formed with the silica membrane of inverse growth;
The silica membrane of the inverse growth is removed using technique is etched back to, to expose in former multilayer lamination structure The surface of silicon dioxide layer;
It deposits to form metal-gate structures in the empty place that the silicon nitride layer being removed leaves.
Preferably, the etching solution that the wet-etching technology selects is phosphoric acid solution, and the phosphoric acid solution has high carve Erosion selection ratio, it is very high to the etch-rate of silicon nitride, and be almost zero to the etch-rate of silica.
Preferably, the silica membrane of the inverse growth is attached to the silicon dioxide layer of the multilayer lamination structure extremely Few one of upper and lower surfaces and side.
Preferably, the thickness of the silica membrane of the inverse growth is about 10 angstroms to 100 angstroms.
Preferably, the technique that is etched back to is specially dry etch process or wet-etching technology.
Preferably, etching gas used in the dry etch process is NH3, C4F8, C4F6, SiCONi.
Preferably, the etching solution that the wet-etching technology being etched back in technique uses is HF.
Preferably, further include following steps after the multilayer lamination structure for forming silicon nitride layer and silicon dioxide layer: Contact through hole, substrate described in the bottom-exposed of the through-hole, in the contact through hole are formed in the multilayer lamination structure Form the channel structure of three-dimensional storage.
The present invention also provides a kind of three-dimensional memory structures, which is characterized in that the three-dimensional memory structure is by as above State what method described in any one was prepared.
The present invention has the advantages that the preparation method and its structure of a kind of three-dimensional storage provided by the invention, using returning Etching technics is former more to expose by etches both silicon nitride layer, the silica membrane of inverse growth is removed in former silicon dioxide layer The surface of silicon dioxide layer in layer heap stack structure provides enough spaces for subsequent deposition metal gate.The thickness of metal gate can To reach expected thickness, the resistance of metal gate is effectively improved, improves the performance and stability of device.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 shows the schematic diagram of the storage array stacked structure of three-dimensional storage in background technique according to the present invention.
Fig. 2 shows the stacked structures of the storage array of three-dimensional storage in background technique according to the present invention to remove silicon nitride Structural schematic diagram after layer.
Fig. 3 show in background technique according to the present invention in the storage array of three bit memories silica inverse growth and The structural schematic diagram of metal gate.
Fig. 4-6 shows the process flow knot that metal gate is formed in the storage array of the three-dimensional storage of the embodiment of the present invention Structure schematic diagram.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs The range opened is fully disclosed to those skilled in the art.
Embodiment one
With reference to shown in Fig. 4-6, the embodiment of the present invention one proposes that a kind of preparation method of three-dimensional storage, feature exist In, comprising the following steps:
As shown in figure 4, providing a substrate (not shown), the array storage of three-dimensional storage is formed on the substrate Area 20;
The display memory block 20 includes silicon nitride layer 21 and silicon dioxide layer 22 are alternatively formed on the substrate more Layer heap stack structure 23;
As shown in figure 5, removing the silicon nitride layer 21 in the multilayer lamination structure 23 using wet-etching technology;It is described wet The etching solution that method etching technics selects is phosphoric acid solution, and the phosphoric acid solution has high etching selection ratio, to silicon nitride Etch-rate is very high, and is almost zero to the etch-rate of silica, in this way can be definitely in etching process by multilayer heap Silicon nitride layer in stack structure completely removes, and retains the silicon dioxide layer for not needing etching.
In silicon nitride layer 21 in the removal multilayer lamination structure 23 the step of, in multilayer lamination structure 23 The surface of silicon dioxide layer 22 is formed with the silica membrane 25 of inverse growth;The generation of the silica membrane of the inverse growth Mainly since wet etching process is a reversible chemical reaction, the etch rate and inverse growth rate of silica are kept Balance, as the silicon ion concentration of reaction carried out in solution rises, the rate of inverse growth rises, and silicon ion and oxonium ion combine Silica is formed, this silica is attached in original silicon dioxide layer, increases the thickness of dioxide layer.Although machine Platform has compensation concentration function immediately, but due to the hysteresis quality of compensation, still will appear the excessive inverse growth of silica.It is described The silica membrane of inverse growth is attached at least upper and lower surfaces and the side of the silicon dioxide layer of the multilayer lamination structure One of.The thickness of the silica membrane of the inverse growth is about 10 angstroms to 100 angstroms.
As shown in fig. 6, the silica membrane 25 of the inverse growth is removed using technique is etched back to, to expose former multilayer The surface of silicon dioxide layer 22 in stacked structure;The consistency of the silica of this inverse growth and original silica is not Equally, it can be removed by dry or wet etch, without influencing original silica.The technique that is etched back to is specially Dry etch process or wet-etching technology.Preferably, etching gas used in the dry etch process is NH3, C4F8, C4F6, SiCONi.Preferably, the etching solution that the wet-etching technology being etched back in technique uses is HF.
It deposits to form metal-gate structures (not shown) at the vacancy that the silicon nitride layer being removed leaves 24.
Embodiment two
With reference to shown in Fig. 4-6, the embodiment of the present invention two proposes that a kind of preparation method of three-dimensional storage, feature exist In, comprising the following steps:
As shown in figure 4, providing a substrate (not shown), the array storage of three-dimensional storage is formed on the substrate Area 20;
The display memory block 20 includes silicon nitride layer 21 and silicon dioxide layer 22 are alternatively formed on the substrate more Layer heap stack structure 23;
Contact through hole, substrate described in the bottom-exposed of the through-hole, described are formed in the multilayer lamination structure 23 The channel structure 26 of three-dimensional storage is formed in contact through hole, as shown in Figure 4.
As shown in figure 5, removing the silicon nitride layer 21 in the multilayer lamination structure 23 using wet-etching technology;It is described wet The etching solution that method etching technics selects is phosphoric acid solution, and the phosphoric acid solution has high etching selection ratio, to silicon nitride Etch-rate is very high, and is almost zero to the etch-rate of silica, in this way can be definitely in etching process by multilayer heap Silicon nitride layer in stack structure completely removes, and retains the silicon dioxide layer for not needing etching.
In silicon nitride layer 21 in the removal multilayer lamination structure 23 the step of, in multilayer lamination structure 23 The surface of silicon dioxide layer 22 is formed with the silica membrane 25 of inverse growth;The generation of the silica membrane of the inverse growth Mainly since wet etching process is a reversible chemical reaction, the etch rate and inverse growth rate of silica are kept Balance, as the silicon ion concentration of reaction carried out in solution rises, the rate of inverse growth rises, and silicon ion and oxonium ion combine Silica is formed, this silica is attached in original silicon dioxide layer, increases the thickness of dioxide layer.Although machine Platform has compensation concentration function immediately, but due to the hysteresis quality of compensation, still will appear the excessive inverse growth of silica.It is described The silica membrane of inverse growth is attached at least upper and lower surfaces and the side of the silicon dioxide layer of the multilayer lamination structure One of.The thickness of the silica membrane of the inverse growth is about 10 angstroms to 100 angstroms.
As shown in fig. 6, the silica membrane 25 of the inverse growth is removed using technique is etched back to, to expose former multilayer The surface of silicon dioxide layer 22 in stacked structure;The technique that is etched back to is specially dry etch process or wet etching work Skill.Preferably, etching gas used in the dry etch process is NH3, C4F8, C4F6, SiCONi.Preferably, described time The etching solution that wet-etching technology in etching technics uses is HF.
It deposits to form metal-gate structures (not shown) at the vacancy that the silicon nitride layer being removed leaves 24.
Embodiment three
The embodiment of the present invention three proposes a kind of preparation method of three-dimensional storage, in this embodiment, will description with The different part of upper embodiment, same section will not be described in great detail.
In the step of removing silicon nitride layer 21 in the multilayer lamination structure 23 using wet-etching technology, the wet process The etching solution that etching technics selects is phosphoric acid solution, and the concentration of phosphoric acid solution is preferably 15% to 35% (percent by volume), Etch period is 30 seconds to 90 seconds, and operation temperature is 26 degrees Celsius to 49 degrees Celsius.Specific etching condition is preferred are as follows:
The concentration of phosphoric acid solution is 20% (percent by volume), and etch period 35 seconds, operation temperature was 30 degrees Celsius;
The concentration of phosphoric acid solution is 25% (percent by volume), and etch period 30 seconds, operation temperature was 35 degrees Celsius;
The concentration of phosphoric acid solution is 30% (percent by volume), and etch period 60 seconds, operation temperature was 40 degrees Celsius.
By the optimum selecting of above-mentioned technological parameter, the result of good removal silicon nitride layer can achieve.
Example IV
The embodiment of the present invention four proposes a kind of preparation method of three-dimensional storage, in this embodiment, will description with The different part of upper embodiment, same section will not be described in great detail.
The technique that is etched back to is specially dry etch process or wet-etching technology.Preferably, the dry etching Etching gas used in technique is NH3, C4F8, C4F6, SiCONi.Preferably, the wet etching work being etched back in technique The etching solution that skill uses is HF.The above-mentioned etching condition for being etched back to technique can be according to the thickness of the silicon dioxide layer of inverse growth And it specifically determines.
When selecting wet-etching technology, specific etching condition is preferred are as follows:
The concentration of HF solution is 18% (percent by volume), and etch period 20 seconds, operation temperature was 40 degrees Celsius;
The concentration of HF solution is 26% (percent by volume), and etch period 18 seconds, operation temperature was 32 degrees Celsius;
The concentration of HF solution is 21% (percent by volume), and etch period 50 seconds, operation temperature was 26 degrees Celsius.
By the optimum selecting of above-mentioned technological parameter, the knot of the silicon dioxide layer of good removal inverse growth can achieve Fruit.
Embodiment five
The embodiment of the present invention five proposes that a kind of three-dimensional memory structure, the three-dimensional memory structure are by such as above-mentioned reality Apply what method described in one to four any one of example was prepared.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto, In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art, It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim Subject to enclosing.

Claims (9)

1. a kind of preparation method of three-dimensional storage, which comprises the steps of:
One substrate is provided, forms the array memory block of three-dimensional storage on the substrate;
The array memory block includes the multilayer lamination structure that silicon nitride layer and silicon dioxide layer are alternatively formed on the substrate;
The silicon nitride layer in the multilayer lamination structure is removed using wet-etching technology;
In the silicon nitride layer in the removal multilayer lamination structure the step of, in the silicon dioxide layer of multilayer lamination structure Surface be formed with the silica membrane of inverse growth, the silica membrane of the inverse growth and the consistency of silicon dioxide layer It is different;
The silica membrane of the inverse growth is removed using technique is etched back to, to expose the dioxy in former multilayer lamination structure The surface of SiClx layer;
It deposits to form metal-gate structures in the empty place that the silicon nitride layer being removed leaves.
2. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that:
The etching solution that the wet-etching technology selects is phosphoric acid solution, and the phosphoric acid solution has high etching selection ratio, It is very high to the etch-rate of silicon nitride, and be almost zero to the etch-rate of silica.
3. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that:
The silica membrane of the inverse growth is attached at least upper and lower surfaces of the silicon dioxide layer of the multilayer lamination structure And one of side.
4. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: the titanium dioxide of the inverse growth Silicon thin film with a thickness of 10 angstroms to 100 angstroms.
5. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: described to be etched back to technique specific For dry etch process or wet-etching technology.
6. a kind of preparation method of three-dimensional storage as claimed in claim 5, it is characterised in that: in the dry etch process The etching gas used is NH3, C4F8, C4F6, SiCONi.
7. a kind of preparation method of three-dimensional storage as claimed in claim 5, it is characterised in that: described to be etched back in technique The etching solution that wet-etching technology uses is HF.
8. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: the is formationed silicon nitride layer with Further include following steps after the multilayer lamination structure of silicon dioxide layer: forming contact through hole in the multilayer lamination structure, Substrate described in the bottom-exposed of the through-hole forms the channel structure of three-dimensional storage in the contact through hole.
9. a kind of three-dimensional memory structure, which is characterized in that the three-dimensional memory structure is any one by such as claim 1-8 What the method described in was prepared.
CN201710724653.8A 2017-08-22 2017-08-22 A kind of preparation method and its structure of three-dimensional storage Active CN107706192B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710724653.8A CN107706192B (en) 2017-08-22 2017-08-22 A kind of preparation method and its structure of three-dimensional storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710724653.8A CN107706192B (en) 2017-08-22 2017-08-22 A kind of preparation method and its structure of three-dimensional storage

Publications (2)

Publication Number Publication Date
CN107706192A CN107706192A (en) 2018-02-16
CN107706192B true CN107706192B (en) 2019-02-22

Family

ID=61169688

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710724653.8A Active CN107706192B (en) 2017-08-22 2017-08-22 A kind of preparation method and its structure of three-dimensional storage

Country Status (1)

Country Link
CN (1) CN107706192B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112368835B (en) * 2018-07-20 2024-09-10 东京毅力科创株式会社 Etching of silicon nitride and deposition control of silicon dioxide in 3D NAND structures
CN110993499B (en) * 2019-11-05 2022-08-16 北京北方华创微电子装备有限公司 Etching method, air gap type dielectric layer and dynamic random access memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101465273B (en) * 2007-12-18 2011-04-20 中芯国际集成电路制造(上海)有限公司 Wet-type etching method for reducing wafer surface blemish and device thereof
CN104157654B (en) * 2014-08-15 2017-06-06 中国科学院微电子研究所 Three-dimensional memory and manufacturing method thereof
CN105575762B (en) * 2014-10-14 2018-07-06 中芯国际集成电路制造(上海)有限公司 A kind of method that wafer surface defects are removed in wet etching
US9524977B2 (en) * 2015-04-15 2016-12-20 Sandisk Technologies Llc Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure

Also Published As

Publication number Publication date
CN107706192A (en) 2018-02-16

Similar Documents

Publication Publication Date Title
US12010838B2 (en) Staircase structure for memory device
JP7192121B2 (en) Formation of staircase structures in three-dimensional memory devices
TWI674665B (en) Semiconductor structure and method of forming the same
JP6190193B2 (en) Integrated circuit device having TSV structure and method of manufacturing the same
JP2021523577A (en) Formation of stairs in 3D memory devices
CN108831887A (en) The preparation method of three-dimensional storage and the preparation method of semiconductor structure
US11527716B2 (en) Memory device with boron nitride liner
CN109983577A (en) The hierarchic structure with Multiple division for three-dimensional storage
CN107706192B (en) A kind of preparation method and its structure of three-dimensional storage
CN107482015B (en) A kind of preparation method and its structure of three-dimensional storage
CN107706182A (en) The preparation method and its structure of a kind of three-dimensional storage
CN107706191A (en) A kind of 3D nand flash memories raceway groove hole polysilicon articulamentum forming method
CN107658222B (en) Planarization process of 3D NAND flash memory channel hole
CN107579073B (en) A kind of preparation method and its structure of three-dimensional storage
CN107731821B (en) A kind of manufacturing method and its device architecture of three-dimensional storage part
CN104143527A (en) Conductive plug and TSV forming method
CN107706183A (en) A kind of manufacture method and its device architecture of three-dimensional storage part
CN107731822B (en) A kind of preparation method and its structure of three-dimensional storage
CN109887916A (en) Two-way gate electrode of nonvolatile three-dimensional semiconductor memory and preparation method thereof
CN107706186A (en) The preparation method and its structure of a kind of three-dimensional storage
CN106558533A (en) The forming method of conductive plunger structure
CN110085514A (en) The Double exposure method of NAND flash memory structure
CN114823688A (en) Semiconductor device and method for manufacturing the same
CN104078419A (en) Method for manufacturing overlapped-hole metal layer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant