CN109887916A - Two-way gate electrode of nonvolatile three-dimensional semiconductor memory and preparation method thereof - Google Patents
Two-way gate electrode of nonvolatile three-dimensional semiconductor memory and preparation method thereof Download PDFInfo
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Abstract
The invention discloses two-way gate electrodes of a kind of nonvolatile three-dimensional semiconductor memory and preparation method thereof, the two-way gate electrode includes: that the m row n in ladder distribution positioned at lower part arranges downward individual gate electrode unit array and the superposed upward individual gate electrode unit array of m row n column in ladder distribution, and each individual gate electrode unit and upward individual gate electrode unit downwards are column structure；The downward individual gate electrode unit upper surface of same row is deleted layer with same control and is connect, and lower surface is connect with same lower wordline；The upward individual gate electrode unit lower surface of same row is deleted layer with same control and is connect, and upper surface is connect with same upper wordline；Two-way gate electrode structure of the invention deletes layer by the control for stacking Super High and gate electrode is divided into two parts up and down, reduces the hole depth for needing to etch, reduces the technology difficulty of superdeep holes etching；Chip area is reduced simultaneously, enhances the heat dissipation effect of nonvolatile three-dimensional semiconductor memory.
Description
Technical field
The invention belongs to technical field of microelectronic devices, store more particularly, to a kind of nonvolatile three-dimensional semiconductor
Two-way gate electrode of device and preparation method thereof.
Background technique
In order to meet the development of efficient and cheap microelectronic industry, semiconductor memory need to have it is higher integrate it is close
Degree.High density is most important for the reduction of semiconductor product cost, for traditional two dimension and planar semiconductor memory, it
Integration density depend primarily on unit area shared by single memory device, integrated level is highly dependent on the good of masking process
It is bad.But even if constantly improving masking process precision with expensive process equipment, the promotion of integration density remains to be had very much
Limit, especially with the development of Moore's Law, in 22nm process node hereinafter, planar semiconductor memory faces needles of various sizes
The problems such as effect and heat dissipation.
As the substitution for overcoming this two-dimentional limit, three-dimensional semiconductor memory is suggested.Three-dimensional semiconductor memory, can
To obtain the device performance of high reliability using the technique of lower manufacturing cost.In the storage of three dimensional NAND (not and, non-simultaneously) type
In device, BiCS (Bit Cost Scalable) is considered as a kind of three dimensional nonvolatile that can reduce each unit area
Memory technology.Technique is realized by the design of through-hole and hitching post, and issues the VLSI technology in 2007 for the first time
In abstract annual meeting.After nonvolatile semiconductor memory uses BiCS technology, not only make this memory that there is three-dimensional structure,
So that the reduction of data storage position is directly proportional to the stacking number of layer frame.But with the continuous rising of stacking number, device design
In still need to solve there are many problem.
Its problem of, is mainly reflected in how to be mutually compatible with storage unit with driving circuit.In the memory of BiCS
In, although memory cell array is designed to three-dimensional structure, the design of peripheral circuit still maintains traditional two-dimensional structure
Design, therefore in the three dimensional NAND memory with BiCS, need to by design step-like control grid layer connect gate electrode and
The storage unit of stacking, then prepare the gate electrode structure of connection grid layer and wordline.And as stacking number constantly increases, this ladder
Shape grid layer can expend a large amount of areas, and existing improvement vertical gate electrode continues growing in stacking number and meets afterwards to a certain extent
Face more severe superdeep holes etching and filling problem.Furthermore vertical gate structure is during being written and read, the string of storage unit
Disturb that problem is relatively serious, and as the increase cross-interference issue of the storage number of plies and cell density is more significant thus existing each
Kind gate electrode is not particularly suited for the three dimensional NAND memory that there is Super High to stack.
Summary of the invention
In view of the drawbacks of the prior art, the purpose of the present invention is to provide a kind of nonvolatile three-dimensional semiconductor memories
Two-way gate electrode and preparation method thereof, it is intended to which solving stacking number in the prior art increases to the area consumption occurred after certain amount
It dissipates, superdeep holes etch and fill and hot cross-interference issue.
To achieve the above object, one aspect of the present invention provides a kind of two-way grid of nonvolatile three-dimensional semiconductor memory
The preparation method of electrode, comprising:
(1) downward individual gate electrode unit array is prepared；
(1.1) by electrochemistry form technology, the porous of single-pass is formed on the substrate for having prepared wordline and bit line
Alumina formwork；
(1.2) by deposition conductive material, downward individual gate electrode unit is formed between the hole wall of the porous alumina formwork；
(1.3) remove the porous alumina formwork, formed from short and arrange downward gate electrode to the high m row n being distributed in ladder
Cell array, and individual gate electrode unit height is identical downwards by m in same wordline；N is the number of wordline, and m is in same wordline
The hole count of the corresponding porous alumina formwork, m, n are for positive integer, i=1,2 ... ..., n-1；
(2) it prepares first layer control grid layer and is connect with most short downward individual gate electrode unit；
(2.1) on the downward individual gate electrode unit array, by deposition of insulative material until covering highest downward
Insulating layer is formed after individual gate electrode unit, passes through the smooth insulating layer upper surface CMP；
(2.2) in the top of the insulating layer and the position that is aligned with the first wordline, insulating layer described in lithography and etching is straight
To exposing the downward individual gate electrode unit of first row；
(2.3) identical as the metal electrode column by depositing in the upper surface of the downward individual gate electrode unit of the first row
Conductive material, form and the first layer that with the first row downward individual gate electrode unit connect parallel with the substrate surface and control
Grid layer；
(3) the downward gate electrode of nonvolatile three-dimensional semiconductor memory is prepared；
It is sequentially formed with the second layer that individual gate electrode unit is connect corresponding downwards, i-th layer of third layer ... ... until n-th layer control
After grid layer processed, the m row n arranges downward individual gate electrode unit array and forms the downward of the nonvolatile three-dimensional semiconductor memory
Gate electrode；
(4) the upward individual gate electrode unit array of nonvolatile three-dimensional semiconductor memory is prepared；
(4.1) on the n-th layer control grid layer, sequential deposition insulating materials and the conductive material form insulating layer
Layer is deleted with the longest control of upward gate electrode；
(4.2) it is deleted on layer in the longest control, alternating deposit insulating layer and sacrificial layer form (n-1) group by sacrificing
The stacked structure of layer and insulating layer composition；
(4.3) above the insulating layer and alignment from the n-th layer control delete on the right of layer along to (n-1) layer control delete
The position on layer the right edge performs etching until encounter the conductive material, and alignment is deleted on the right of layer from the control of (n-i) layer along to the
(n-i-1) position on edge on the right of layer is deleted in layer control, is performed etching up to encountering insulating materials, is formed platform on the stacked structure
Rank；
(4.4) insulating layer is formed after depositing the insulating materials on the step until covering highest step, is utilized
The smooth insulating layer upper surface CMP；
(4.5) the layer identical conductive material replacement sacrificial layer is deleted with control by filling, forms upward gate electrode
Layer is deleted in control；
(4.6) position being aligned above the insulating layer and with the wordline is etched described exhausted using self-aligned technology
Edge layer forms upper port and is located at arranging from short to the high m row n being distributed in ladder for same level up to encountering the conductive material
Hole；
(4.7) hole is filled using the conductive material, form that upper port is located at same level is in height from short
The m row n of ladder distribution arranges upward individual gate electrode unit array；
(5) the upward gate electrode of nonvolatile three-dimensional semiconductor memory is prepared；
Using self-aligned technology above the upward individual gate electrode unit array alignment wordline figure, lead described in sputtering sedimentation
Electric material is formed with after the upper wordline that individual gate electrode unit is connect corresponding upwards, and the upward individual gate electrode unit array forms institute
State the upward gate electrode of nonvolatile three-dimensional semiconductor memory.
Another aspect provides a kind of two-way gate electrodes of nonvolatile three-dimensional semiconductor memory, including position
In lower part in the m row n of ladder distribution arrange downward individual gate electrode unit array and the superposed m row n in ladder distribution arrange to
Upper individual gate electrode unit array, each individual gate electrode unit and upward individual gate electrode unit downwards are column structure；The downward grid of same row
Electrode unit upper surface is deleted layer with same control and is connect, and lower surface is connect with same lower wordline；The upward individual gate electrode unit of same row
Lower surface is deleted layer with same control and is connect, and upper surface is connect with same upper wordline.
Contemplated above technical scheme through the invention, compared with prior art, can obtain it is following the utility model has the advantages that
Two-way gate electrode structure of the invention deletes layer by the control for stacking Super High and gate electrode is divided into two up and down
Part reduces the hole depth for needing to etch, and reduces the technology difficulty of superdeep holes etching；And the two-way grid being superimposed up and down
Electrode structure reduces the wordline number that individual gate electrode unit connects in single plane, reduces chip area, while enhancing non-
The heat dissipation effect of volatibility three-dimensional semiconductor memory.
Detailed description of the invention
Fig. 1 is that the nonvolatile three-dimensional semiconductor memory construction provided in an embodiment of the present invention with two-way gate electrode is shown
It is intended to；
Fig. 2 (a) is the nonvolatile three-dimensional semiconductor memory provided in an embodiment of the present invention with two-way gate electrode
Structure top view；
Fig. 2 (b) is the nonvolatile three-dimensional semiconductor memory provided in an embodiment of the present invention with two-way gate electrode
Substrate cross-section figure；
Fig. 3-Figure 24 is the diagrammatic cross-section in two-way gate electrode preparation method implementation procedure provided in an embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Such as Fig. 1, shown in Fig. 2 (a), the embodiment of the invention provides a kind of the two-way of nonvolatile three-dimensional semiconductor memory
Gate electrode arranges downward individual gate electrode unit array including the m row n in ladder distribution positioned at lower part and superposed in ladder point
The m row n of cloth arranges upward individual gate electrode unit array, and each individual gate electrode unit and upward individual gate electrode unit downwards are column structure；
The downward individual gate electrode unit upper surface of same row is deleted layer with same control and is connect, and lower surface is connect with same lower wordline (LWL)；It is same
It arranges upward individual gate electrode unit lower surface to delete layer with same control and connect, upper surface is connect with same upper wordline (HWL).
Wherein, the material of metal electrode column includes one or more conductors or semiconductor material, for example DOPOS doped polycrystalline silicon,
Tungsten, copper, aluminium, tantalum, titanium, cobalt, titanium nitride or their alloy.
The embodiment of the invention also provides a kind of preparation methods of two-way gate electrode as described above, in order to the present embodiment
In method understand the description of system, Fig. 2 (b)-Figure 24 gives the diagrammatic cross-section formed in embodiment implementation procedure,
In conjunction with specifically manufacture craft, above-mentioned two-way gate electrode can be prepared via a method which:
(1) downward individual gate electrode unit array is prepared；
Specifically, step (1) includes:
(1.1) by electrochemistry form technology, the porous of single-pass is formed on the substrate for having prepared wordline and bit line
Alumina formwork；
Specifically, shown in the substrate cross-section such as Fig. 2 (b) for preparing wordline and bit line, wordline LWL0, LWL1, LWL2, mark
Note 100 is substrate, and the diagrammatic cross-section after executing step (1.1) is as shown in figure 3, label 200 is porous alumina formwork.
(1.2) by deposited metal material, metal electrode column is formed between the hole wall of porous alumina formwork 200；
Specifically, substrate 100 and porous alumina formwork 200 are placed in metallic solution, graphite built in solution is as sun
Pole, wordline LWL0-2 is as the external different constant-current source of cathode, and by regulating and controlling depositional environment, such as each current source of connection is big
Small and sedimentation time, come regulate and control deposition metal electrode column height, formed metal electrode column 110b, 111b as shown in Figure 5,
112b, the metal electrode column are downward individual gate electrode unit.
Wherein the material of metal electrode column includes one or more conductors or semiconductor material, for example DOPOS doped polycrystalline silicon, tungsten,
Copper, aluminium, tantalum, titanium, cobalt, titanium nitride or their alloy.
(1.3) it by porous alumina formwork (200) described in etching away, is formed from short to the high m row n being distributed in ladder
Downward individual gate electrode unit array is arranged, and the m in same wordline downward individual gate electrode unit height are identical；N is the number of wordline, m
For the hole count of the porous alumina formwork corresponding in same wordline, m, n are for positive integer, i=1,2 ... ..., n-1；
Specifically, the thorough etching away porous alumina formwork 200 of suitable acid solution is selected, after executing the step
Diagrammatic cross-section as shown in figure 5, as can be seen from the figure on same wordline LWL downward individual gate electrode unit height it is identical, 3 arrange to
Lower individual gate electrode unit is distributed to height in ladder from short
(2) it prepares first layer control grid layer and is connect with most short downward individual gate electrode unit；
Specifically, step (2) includes:
(2.1) on the downward individual gate electrode unit array, by deposition of insulative material until covering highest downward
Insulating layer is formed after individual gate electrode unit, passes through the smooth insulating layer upper surface CMP；
Specifically, chemical vapour deposition technique or magnetron sputtering are used on the two-way gate electrode array above-mentioned from short to high
Method depositing insulating layer until cover highest gate electrode post, then using insulating layer upper surface in CMP planarizing；It executes
Diagrammatic cross-section after the step is as shown in fig. 6, label 300 is insulating layer.
(2.2) the top of the insulating layer and with the position that wordline LWL0 is aligned under first, described in lithography and etching absolutely
Edge layer (300) is until expose the downward individual gate electrode unit of first row；
Specifically, 300 surface of insulating layer after planarizing is coated with photoresist, passes through alignment and masking process Partial exposure
Until developing after photoresist denaturation above the first wordline above first lower wordline LWL0, then etch above the first lower wordline LWL0
Insulating layer, until exposing the upper surface of the downward individual gate electrode unit 110b of first row；Diagrammatic cross-section after executing the step is such as
Shown in Fig. 7, label 400 is photoresist.
(2.3) identical as the metal electrode column by depositing in the upper surface of the downward individual gate electrode unit of the first row
Conductive material, form and the first layer that with the first row downward individual gate electrode unit connect parallel with the substrate surface and control
Grid layer；
Specifically, the sectional view after executing the step is as shown in figure 8, label 110a is that layer is deleted in first layer control.
(3) the downward gate electrode of nonvolatile three-dimensional semiconductor memory is prepared；
Specifically, it repeats the above steps, second of depositing insulating layer simultaneously polishes upper surface, and sectional view is as shown in Figure 9；From
The place LWL0 to LWL1 carries out lithography and etching until exposing the downward individual gate electrode unit 111b of secondary series, and section is illustrated such as Figure 10 institute
Show；It deposits the made of metal and deletes a layer 111a for second layer control, diagrammatic cross-section is as shown in figure 11；
Third time depositing insulating layer simultaneously polishes upper surface, and diagrammatic cross-section is as shown in figure 12；From from LWL0 to LWL2 directly
Etching arranges downward individual gate electrode unit 112b until exposing third, and diagrammatic cross-section is as shown in figure 13；It is standby to deposit the made of metal
A layer 112a is deleted in third layer control, and diagrammatic cross-section is as shown in figure 14.
(4) the upward individual gate electrode unit array of non-easy real three-dimensional semiconductor memory is prepared specifically, step (4) includes:
(4.1) on the n-th layer control grid layer, sequential deposition insulating materials and the conductive material form insulating layer
Layer is deleted with the longest control of upward gate electrode；
(4.2) it is deleted on layer in the longest control, alternating deposit insulating layer and sacrificial layer form sacrificial layer and insulating layer
(300) stacked structure formed；
Specifically, certain thickness insulating layer is formed in the disposed thereon insulating materials that layer 112a is deleted in third layer control, then
Deposition conductive material forms control and deletes a layer 113a, replaces depositing insulating layer and sacrificial layer 114c, 115c on 113a, is formed as schemed
Stacked structure shown in 15.
(4.3) above the insulating layer and alignment on the right of 11 (i-1) a along the position to the right 11ia edge, carved
Until encountering conductive material, alignment edge on the right of 11 (i-2) a is performed etching to the 11 right edge placements of (i-1) a until encountering for erosion
Insulating materials forms step on the stacked structure；
Specifically, above top layer's insulating layer and be aligned on the right of 111a along to edge on the right of 112a position, carved
Until encounter conductive material, the cross-section structure of formation is as shown in figure 16 for erosion, then above top layer's insulating layer and alignment from
Along the position to edge on the right of 111a on the right of 110a, performs etching up to encountering insulating materials, form Step-edge Junction as shown in figure 17
Structure.
(4.4) insulating layer is formed after depositing insulating layer is until cover highest step on the step, it is smooth using CMP
The insulating layer upper surface；
Specifically, the cross-section structure after executing the step is as shown in figure 18.
(4.5) the layer identical conductive material replacement sacrificial layer is deleted with control by filling, forms upward gate electrode
Layer is deleted in control；
Specifically, it is etched using chemical gas after etching sacrificial layer completely, it is heavy using vapor deposition, sputtering or chemical vapor
Product to fill conductive material identical with gate electrode, execute formed after the step control as shown in figure 19 delete a layer 113a, 114a,
115a。
(4.6) position being aligned above the insulating layer and with the wordline is etched described exhausted using self-aligned technology
Edge layer forms upper port and is located at arranging from short to the high m row n being distributed in ladder for same level up to encountering the conductive material
Hole；
Specifically, 300 surface of insulating layer after planarizing is coated with photoresist 400, passes through alignment and masking process part
Exposure LWL0, LWL1, LWL2 above until exposure at photoresist denaturation after develop, as shown in figure 20, then etch LWL0,
LWL1, LWL2 overlying insulating layer are formed as shown in figure 21 until encounter conductive material, upper port be located at same level from short
To high hole 115d, 114d, 113d in ladder distribution.
(4.7) layer identical conductive material filling hole is deleted using with control, forms upper port and is located at same level
Arrange upward individual gate electrode unit array to the high m row n being distributed in ladder from short；
Specifically, after executing the step, upward individual gate electrode unit array 115b, 114b, 113b as shown in figure 22 are formed.
(5) the upward gate electrode of nonvolatile three-dimensional semiconductor memory is prepared；
Using self-aligned technology above upward individual gate electrode unit array alignment wordline figure, sputtering sedimentation and gate electrode phase
Same metal electrode material forms the upper wordline HWL3-HWL5 connecting with corresponding upward individual gate electrode unit after removing, described upward
Individual gate electrode unit array forms the upward gate electrode of the nonvolatile three-dimensional semiconductor memory.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (3)
1. a kind of two-way gate electrode preparation method of nonvolatile three-dimensional semiconductor memory, which is characterized in that including following step
It is rapid: to include:
(1) downward individual gate electrode unit array is prepared；
(1.1) by electrochemistry form technology, the porous of single-pass is formed on the substrate (100) for having prepared wordline and bit line
Alumina formwork (200)；
(1.2) by deposition conductive material, downward gate electrode list is formed between the hole wall of the porous alumina formwork (200)
Member；
(1.3) remove the porous alumina formwork (200), formed from short and arrange downward gate electrode to the high m row n being distributed in ladder
Cell array (110b-11ib), and individual gate electrode unit height is identical downwards by m in same wordline；N is the number of wordline, and m is
The hole count of the corresponding porous alumina formwork in same wordline, m, n are for positive integer, i=1,2 ... ..., n-1；
(2) it prepares first layer control grid layer and is connect with most short downward individual gate electrode unit；
(2.1) on the downward individual gate electrode unit array, by deposition of insulative material until covering highest downward grid electricity
Insulating layer (300) are formed after pole unit, pass through smooth insulating layer (300) upper surface CMP；
(2.2) it in the top of the insulating layer (300) and the position that is aligned with the first wordline WL0, insulate described in lithography and etching
Layer (300) is until expose the downward individual gate electrode unit of first row；
(2.3) in the upper surface of the downward individual gate electrode unit of the first row, by depositing lead identical with the metal electrode column
Electric material forms first layer control grid layer that is parallel with the substrate surface and connecting with the downward individual gate electrode unit of the first row
110a；
(3) the downward gate electrode of nonvolatile three-dimensional semiconductor memory is prepared；
It is sequentially formed with the second layer that individual gate electrode unit is connect corresponding downwards, i-th layer of third layer ... ... until n-th layer control gate
After layer (111a-11ia), the m row n arranges downward individual gate electrode unit array and forms the nonvolatile three-dimensional semiconductor storage
The downward gate electrode of device；
(4) the upward individual gate electrode unit array of nonvolatile three-dimensional semiconductor memory is prepared；
(4.1) on the n-th layer control grid layer, sequential deposition insulating materials and the conductive material, formed insulating layer and to
Layer is deleted in the upper longest control of gate electrode；
(4.2) deleted on layer in the longest control, alternating deposit insulating layer and sacrificial layer, formed (n-1) group by sacrificial layer and
The stacked structure of insulating layer composition；
(4.3) above the insulating layer and alignment from the n-th layer control delete on the right of layer along to (n-1) layer control delete layer the right side
The position at edge performs etching until encountering the conductive material, and alignment deletes layer the right edge to (n- from the control of (n-i) layer
I-1) position on edge on the right of layer is deleted in layer control, is performed etching up to encountering insulating materials, is formed step on the stacked structure；
(4.4) insulating layer is formed after depositing the insulating materials on the step until covering highest step, it is flat using CMP
The whole insulating layer upper surface；
(4.5) the layer identical conductive material replacement sacrificial layer is deleted with control by filling, forms the control of upward gate electrode
Delete layer；
(4.6) position being aligned above the insulating layer and with the wordline etches the insulating layer using self-aligned technology
Until encounter the conductive material, formed upper port be located at same level from short to the high m row n column hole in ladder distribution
Hole；
(4.7) hole is filled using the conductive material, form upper port be located at same level from it is short to it is high be in ladder
The m row n of distribution arranges upward individual gate electrode unit array；
(5) the upward gate electrode of nonvolatile three-dimensional semiconductor memory is prepared；
Using self-aligned technology above the upward individual gate electrode unit array alignment wordline figure, conduction material described in sputtering sedimentation
Material is formed with after the upper wordline that individual gate electrode unit is connect corresponding upwards, and the upward individual gate electrode unit array forms described non-
The upward gate electrode of volatibility three-dimensional semiconductor memory.
2. a kind of two-way gate electrode preparation method of nonvolatile three-dimensional semiconductor memory according to claim 1,
It is characterized in that, the insulating materials is silica, silicon nitride or silicon oxynitride；The conductive material includes one or more leads
Body or semiconductor material, for example DOPOS doped polycrystalline silicon, tungsten, copper, aluminium, tantalum, titanium, cobalt, titanium nitride or their alloy.
3. a kind of a kind of two-way grid of nonvolatile three-dimensional semiconductor memory using method as claimed in claim 1 or 2 preparation
Electrode arranges downward individual gate electrode unit array including the m row n in ladder distribution positioned at lower part and superposed in ladder distribution
M row n arrange upward individual gate electrode unit array, each individual gate electrode unit and upward individual gate electrode unit downwards are column structure；Together
The one downward individual gate electrode unit upper surface of column is deleted layer with same control and is connect, and lower surface is connect with same lower wordline；Same row is upward
Individual gate electrode unit lower surface is deleted layer with same control and is connect, and upper surface is connect with same upper wordline.
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| CN113725219A (en) * | 2020-05-25 | 2021-11-30 | 爱思开海力士有限公司 | Three-dimensional memory device and method of manufacturing the same |
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