CN107704421B

CN107704421B - Multi-core processor and message processing method

Info

Publication number: CN107704421B
Application number: CN201710818602.1A
Authority: CN
Inventors: 马宏源; 郭永亮; 程爱爽; 王�锋
Original assignee: New H3C Security Technologies Co Ltd
Current assignee: New H3C Security Technologies Co Ltd
Priority date: 2017-09-12
Filing date: 2017-09-12
Publication date: 2021-04-27
Anticipated expiration: 2037-09-12
Also published as: CN107704421A

Abstract

The invention provides a multi-core processor and a message processing method, wherein the multi-core processor comprises the following components: an SSO module, an interrupt controller and a plurality of cores; the SSO module is used for counting the number of WQEs belonging to the same Group; when the number of the counted WQEs reaches a preset number threshold, informing the interrupt controller to send a first interrupt request to a first Core bound with the Group in the plurality of cores, wherein the preset number threshold is larger than 1; and the first Core is used for acquiring WQE belonging to a Group bound with the first Core from the SSO module after receiving the first interrupt request, and reading a message from a memory for processing based on the acquired WQE. The invention can effectively reduce the frequency of interruption and the frequency of Core starting and stopping the packet receiving thread, and saves the resources of the processor.

Description

Multi-core processor and message processing method

Technical Field

The present invention relates to the field of network communication technologies, and in particular, to a multi-core processor and a packet processing method.

Background

The multi-Core processor generally includes a PKI (Packet Input) module, an SSO (Schedule/synchronization/Order) module, and a plurality of cores (cores), and based on parallel processing capabilities of the plurality of cores, the message processing capability of the network device is greatly improved.

At present, a multi-Core processor mainly adopts an interrupt trigger mechanism to trigger a packet receiving thread in Core to perform message processing, and the method specifically comprises the following steps: the PKI module is responsible for receiving and analyzing the message, adding the analyzed result to a WQE (Work Queue Entry) corresponding to the message, then storing the WQE into the SSO module, and storing the message into a memory; when WQE exists in the SSO module, interrupting and triggering the Core to acquire the WQE from the SSO module, and reading a message corresponding to the WQE from the memory by the Core for processing based on the acquired WQE; and when the Core does not acquire the WQE continuously for multiple times, exiting the packet receiving thread. And when the SSO module has WQE again, interrupting the triggering Core again to process the message.

When the data traffic is small and the time interval for the packet to reach the processor is very uneven, frequent interrupts, frequent awakening and packet receiving threads exit, which results in a small amount of traffic and consumes more processor resources.

Disclosure of Invention

The invention aims to provide a multi-core processor and a message processing method, which are used for reducing the occupation of processor resources when the data flow is small.

In order to achieve the purpose, the invention provides the following technical scheme:

in one aspect, the present disclosure provides a multi-core processor, comprising: an SSO module, an interrupt controller and a plurality of cores;

the SSO module is used for counting the number of WQEs belonging to the same Group; when the number of the counted WQEs reaches a preset number threshold, informing the interrupt controller to send a first interrupt request to a first Core bound with the Group in the plurality of cores, wherein the preset number threshold is larger than 1;

and the first Core is used for acquiring WQE belonging to a Group bound with the first Core from the SSO module after receiving the first interrupt request, and reading a message from a memory for processing based on the acquired WQE.

On the other hand, the invention provides a message processing method, which is applied to an SSO module included in a multi-core processor, wherein the multi-core processor further comprises the following steps: an interrupt controller and a plurality of cores, the method comprising:

counting the number of WQEs belonging to the same Group;

when the number of the counted WQEs reaches a preset number threshold, informing the interrupt controller to send a first interrupt request to a first Core bound with the Group in the cores, so that the first Core obtains the WQE belonging to the Group bound with the first Core from the SSO module after receiving the first interrupt request, and reading a message from a memory for processing based on the obtained WQE, wherein the preset number threshold is larger than 1.

As can be seen from the above description, the number threshold of WQEs is preset for each Group, and the number threshold is greater than 1, when the number of WQEs of a Group counted by the SSO module does not reach the preset number threshold, the SSO module does not notify the interrupt controller to trigger the Core bound to the Group to perform message processing, and compared with the prior art in which the SSO module notifies the interrupt controller to trigger the Core to perform message processing as long as there is a WQE, the present invention reduces the frequency of interruption and the frequency of the Core starting and stopping a packet receiving thread for processing a message, and saves the resources of the processor.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a multi-core processor according to an embodiment of the present invention;

fig. 2 is a flowchart of a message processing method according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

The embodiment of the invention provides a multi-Core processor which comprises a PKI module, an SSO module, an interrupt controller and a plurality of cores. Referring to fig. 1, a schematic structural diagram of a multi-Core processor according to an embodiment of the present invention is shown, where the multi-Core processor includes cores 1-5, and 5 cores in total. The number of cores shown in fig. 1 is only an exemplary illustration, and the present invention does not limit the number of cores.

The various modules that a multi-core processor includes will be described below:

a PKI module: the system is used for allocating a Group to the message, filling the Group identification of the allocated Group into the WQE corresponding to the message, storing the message into a memory outside the multi-core processor, and sending the WQE corresponding to the message to the SSO module.

An SSO module: counting the number of WQEs belonging to the same Group; when the number of the counted WQEs reaches a preset number threshold, informing the interrupt controller to send a first interrupt request to a first Core bound with the Group in the plurality of cores.

Specifically, the SSO module respectively counts the number of WQEs belonging to each Group for each Group, and when the counted number of WQEs of a certain Group reaches a preset number threshold, the SSO module notifies the interrupt controller to send a first interrupt request to a Core (denoted as a first Core) bound to the Group, where the preset number threshold is greater than 1.

Referring to table 1, a binding relationship between a Group and a Core preconfigured in an SSO module shown in the embodiment of the present invention is shown, and the table is only an exemplary illustration, and the present invention does not limit a specific binding relationship between the Group and the Core.

Group	Core
		Group0～Group7	Core1
Group8～Group15	Core2
		Group16～Group30	Core3
Group31～Group54	Core4
		Group55～Group63	Core5

TABLE 1

For example, if the preset number threshold is 2, if the number of WQEs of Group0 counted by the SSO module is 1 and is smaller than the preset number threshold, the SSO module does not notify the interrupt controller to send an interrupt request to the Core1 bound to Group 0; if the number of Group0 counted by the SSO module is 2 and reaches a preset number threshold, the SSO module notifies the interrupt controller to send an interrupt request to the Core1 bound to Group 0.

A first Core: and the WQE module is used for acquiring the WQE belonging to the Group bound with the first Core from the SSO module after receiving the first interrupt request, and reading a message from a memory for processing based on the acquired WQE.

Specifically, after receiving a first interrupt request, a first Core sends a command for acquiring WQE to an SSO module, the SSO module sends existing WQE belonging to a Group bound to the first Core, and the first Core reads a message from a memory for processing based on a storage address of the message included in the acquired WQE.

For example, after receiving an interrupt request, the Core1 starts a packet receiving thread, the packet receiving thread sends an instruction for acquiring WQE to the SSO module, the SSO module sends locally existing WQE belonging to groups 0 to 7 to the Core1 according to the pre-configured binding relationship between the Core1 and groups 0 to 7, and the Core1 reads a corresponding message from the memory for processing based on the acquired WQE. When the Core1 does not acquire WQE from the SSO module for a plurality of times, it indicates that no message needing Core1 processing exists currently, and therefore, the packet receiving thread exits. And after the next interrupt is triggered, the packet receiving thread is started again for processing.

As can be seen from the above description, the number threshold of WQEs is preset for each Group, and the number threshold is greater than 1, when the number of WQEs of a Group counted by the SSO module does not reach the preset number threshold, the SSO module does not notify the interrupt controller to trigger a Core bound to the Group to perform message processing, and compared with the prior art in which the SSO module notifies the interrupt controller to trigger the Core to perform message processing as long as there is a WQE, the present invention reduces the frequency of interrupts and the frequency of cores starting and stopping packet receiving threads, and saves the resources of the processor.

In addition, the invention sets a timer for each Group, and preferably, the timer can directly adopt a hardware timer inside the SSO module. Specifically, the SSO module is further configured to configure timeout time of a timer corresponding to the Group, and when the timer expires, notify the interrupt controller to send a second interrupt request to a Core (denoted as a second Core) bound to the Group corresponding to the timeout timer; the second Core is used for acquiring the WQEs belonging to the Group bound with the second Core from the SSO module after receiving the second interrupt request, so that the phenomenon that the Core bound with the Group cannot be triggered to process in time due to the fact that the number of the WQEs belonging to a certain Group is too small (the number of the WQEs cannot reach a preset number threshold) is avoided, and message delay or message discarding is caused.

An embodiment of the present invention further provides a message processing method, which is a flowchart of the message processing method shown in the embodiment of the present invention, referring to fig. 2, and the embodiment describes a message processing process from the side of the SSO module.

Step 201, counting the number of WQEs belonging to the same Group.

Step 202, when the counted number of WQEs reaches a preset number threshold, notifying the interrupt controller to send a first interrupt request to a first Core bound with the Group in the plurality of cores, so that the first Core obtains the WQEs belonging to the Group bound with the first Core from the SSO module after receiving the first interrupt request, and reading a message from a memory for processing based on the obtained WQEs, wherein the preset number threshold is greater than 1.

Further, the SSO module includes timers, where each Group corresponds to one timer, and the method further includes:

configuring the overtime of a timer;

when the timer is overtime, the interrupt controller is informed to send a second interrupt request to a second Core bound with the Group corresponding to the overtime timer, so that the second Core obtains the WQE belonging to the Group bound with the second Core from the SSO module after receiving the second interrupt request.

Further, the timer is a hardware timer.

The implementation process of the message processing method is described in detail in the above description of each module in the multi-core processor, and is not described herein again.

Now, the multi-core processor shown in fig. 1 is taken as an example, and the multi-core processor and the message processing process are described.

As shown in table 1, configuring a binding relationship between Group and Core in the SSO module; presetting the number threshold of WQEs belonging to each Group to be 2; and configuring the timeout time of the timer corresponding to each Group to be 100 ms.

When the message Packet1 reaches the multicore processor, the PKI module allocates Group0 to Packet1, acquires the storage Address (denoted as Address1) of Packet1 in the memory, fills Group0 and Address1 in the WQE (denoted as WQE1) corresponding to Packet1, sends WQE1 to the SSO module, and stores Packet1 in the storage space with the memory Address of Address 1.

And the SSO module counts the number of WQEs belonging to each Group, at this time, the number of WQEs belonging to the Group0 is 1 and is smaller than the number threshold value 2, and the SSO module does not inform the interrupt controller to send an interrupt request to the Core1 bound with the Group 0.

When the message Packet2 reaches the multicore processor, the PKI module allocates Group8 to Packet2, acquires the storage Address (denoted as Address2) of Packet2 in the memory, fills Group8 and Address2 in the WQE (denoted as WQE2) corresponding to Packet2, sends WQE2 to the SSO module, and stores Packet2 in the storage space with the memory Address of Address 2.

And the SSO module counts the number of WQEs belonging to each Group, at the moment, the number of WQEs belonging to Group0 is 1, the number of WQEs belonging to Group8 is 1, and the number of WQEs is smaller than a number threshold value 2, and the SSO module does not inform the interrupt controller of sending an interrupt request to a Core1 bound with Group0 or inform the interrupt controller of sending an interrupt request to a Core2 bound with Group 8.

When the message Packet3 reaches the multicore processor, the PKI module allocates Group0 to Packet3, acquires the storage Address (denoted as Address3) of Packet3 in the memory, fills Group0 and Address3 in the WQE (denoted as WQE3) corresponding to Packet3, sends WQE3 to the SSO module, and stores Packet3 in the storage space with the memory Address of Address 3.

The SSO module counts the number of WQEs belonging to each Group, at this time, the number of WQEs belonging to the Group0 is 2, a preset number threshold is reached, the SSO module informs the interrupt controller to send an interrupt request to a Core1 bound with the Group0, the Core1 starts a Packet receiving thread after receiving the interrupt request, and sends an instruction for acquiring the WQEs to the SSO module, the SSO module sends WQEs 1 belonging to the Group0 to the Core1 according to the locally recorded binding relationship between the groups 0-7 and the Core1, and the Core1 reads a Packet1 from a memory according to the Address1 included in the WQEs 1. After processing, the Core1 sends an instruction for acquiring WQE to the SSO module again, the SSO module sends WQE3 belonging to Group0 to the Core1, and the Core1 reads the Packet3 from the memory according to Address3 included in the WQE3 for processing. When the Core1 sends a command for acquiring WQE to the SSO module again, if no WQE belonging to Group 0-Group 7 bound with the Core1 exists in the SSO module, the Core1 cannot acquire the WQE, and after the WQE is not acquired for a plurality of times continuously, the Core1 exits the packet receiving thread.

If the number of WQEs belonging to Group8 counted by the SSO module is always 1, when the timeout time (100ms) of a timer corresponding to Group8 reaches, the SSO module informs the interrupt controller to send an interrupt request to a Core2 bound with Group8, the Core2 starts a Packet receiving thread after receiving the interrupt request, and sends an instruction for acquiring the WQEs to the SSO module, the SSO module sends WQEs 2 belonging to Group8 to the Core2 according to locally recorded binding relations between groups 8-15 and the Core2, and the Core2 reads Pat 2 from a memory according to an Address2 included in WQE2 for processing.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A multi-core processor, comprising: the system comprises a message scheduling SSO module, an interrupt controller and a plurality of Core cores;

2. The processor of claim 1, wherein the SSO module comprises a timer, wherein one timer is for each Group;

the SSO module is also used for configuring the overtime time of the timer; when the timer is overtime, informing the interrupt controller to send a second interrupt request to a second Core bound with the Group corresponding to the overtime timer;

and the second Core is used for acquiring WQEs belonging to a Group bound with the second Core from the SSO module after the second interrupt request is received.

3. The processor of claim 2, wherein the timer is a hardware timer.

4. A message processing method is applied to a message scheduling SSO module included in a multi-core processor, and is characterized in that the multi-core processor further comprises: an interrupt controller and a plurality of Core cores, the method comprising:

counting the number of WQEs belonging to the same Group;

5. The method of claim 4, wherein the SSO module comprises timers, one for each Group, the method further comprising:

configuring the overtime of a timer;

6. The method of claim 5, wherein the timer is a hardware timer.