CN106557358A - A kind of date storage method and device based on dual core processor - Google Patents
A kind of date storage method and device based on dual core processor Download PDFInfo
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- CN106557358A CN106557358A CN201510634222.3A CN201510634222A CN106557358A CN 106557358 A CN106557358 A CN 106557358A CN 201510634222 A CN201510634222 A CN 201510634222A CN 106557358 A CN106557358 A CN 106557358A
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Abstract
Embodiments provide a kind of date storage method based on dual core processor and device, the method is suitable for inclusion in the switching equipment of dual core processor, in the method, by receiving port receiving data message, the data message is sent to into the first core processor；First core processor receives the data message and produces interruption, and by data message storage to packet receiving buffer queue；Second core processor takes out data message from packet receiving buffer queue and parses, and the data message storage after parsing is realized the storage of the data message to data buffer storage queue.As in embodiments of the present invention data receiver and data parsing being processed in different core processors respectively, therefore, it can the interruption for effectively avoiding data receiver from producing, the impact to data storage, so as to improve storage efficiency, it is ensured that the reliability of system.
Description
Technical field
The present invention relates to technical field of data storage, more particularly to a kind of data storage based on dual core processor
Method and device.
Background technology
Conventional memory method is to complete data storage in User space and kernel state interaction at present, first, in application
Start DMA in program, driving is received during DMA is completed has no progeny, drive interrupt processing function to discharge letter again
Number notify application program, then, application call read methods call copy_to_user by driving
Mass data is copied in user's space buffer area, finally by function by kernel spacing, and application program is by data
In write hard disk, then restart next DMA.
But, whole process palpus application program and driving collaboration are completed, while mass data need to also be empty from kernel
Between copy to user's space, this needs frequently switches between system model and user model, takes a large amount of
System resource, operating system response speed decline, and a large amount of operations in addition need to be completed in the application, these
Factor necessarily causes storage speed not high and fluctuates larger.
With the development of memory technology, it is possible to achieve storage is completed in kernel spacing, it is to avoid between pattern
The system resource that switching is caused takes excessive problem, improves storage speed, but system resource is disappeared
Consumption is still very big, and double-core memory technology brings more system resources, when data message is received, root
Data message is assigned in a kernel according to the load balancing rule of setting carries out parsing storage, therefore, enter
One step improves storage efficiency.
In actual data storage procedure, about 20% system resource of processor is used for data receiver and interruption,
About 50% system resource is used to process the data parsing to buffer queue, therefore, even at double-core data
The method of reason, when the kernel being allocated completes the parsing of data when being stored, receives new data message
When will interrupt current write operation, affect storage efficiency.
Therefore, even if the method for carrying out data storage using dual core processor in prior art, due to being assigned to
The data of each kernel are performed locally the operation for receiving parsing and storing, and when receiving new data, will produce
It is raw to interrupt, storage efficiency is affected, when especially running into the massive dataflows such as gigabit networking, kernel frequency will be caused
Numerous interruption, causes CPU without normal work is sent out, so as to reduce data storage efficiency, it is impossible to ensure system
The reliability of system.
The content of the invention
In view of the above problems, it is proposed that the present invention overcomes the problems referred to above or at least in part to provide one kind
A kind of date storage method and device based on dual core processor for solving the above problems.
A kind of date storage method based on dual core processor is embodiments provided, the method is applied to
Switching equipment comprising dual core processor, the method include：
By receiving port receiving data message, the data message is sent to into the first core processor；
First core processor receives the data message and produces interruption, and by data message storage to receipts
Bag buffer queue；
Second core processor takes out the data message from packet receiving buffer queue and parses, after parsing
The storage of the data message is realized in data message storage to data buffer storage queue.
Interruption is produced frequently in order to reduce short data message, the impact to data storage improves storage efficiency,
The reliability of system is further ensured that, it is described in embodiments of the present invention that the data message is sent to into first
Before core processor, the method also includes：
The data message is sent to into FPGA；
The quantity of data messages of the FPGA to receiving is updated, and the data message after judging to update
Whether quantity reaches the first amount threshold of setting；
When it is determined that the quantity of data message after updating reaches the first amount threshold of setting, by the number
The first core processor, and the zeroing number of the data message to receiving are sent to according to message；
Otherwise, the data message is stored in locally.
In order to reduce packet receiving interruption times, the impact frequently interrupted to storage efficiency is reduced, is further improved
The reliability of system, during the first core processor reception data message is produced in embodiments of the present invention
It is disconnected to include：
After first core processor receives the data message, the quantity of the data message to receiving is carried out
Update；Whether the quantity of the data message that judgement is received reaches the second amount threshold of setting；When it is determined that connecing
When the quantity of the data message for receiving reaches the second amount threshold of setting, interruption is produced, and will be received
The zeroing number of data message；Or
After first core processor receives the data message, judge whether connect in the time span for setting
Receive other data messages；When it is determined that not receiving other data messages in the time span of setting, produce
Interrupt, and by the zeroing number of the data message for receiving.
In order to reduce impact of the data parsing to data receiver, the reliability of system is further improved, at this
The data message storage after parsing is realized into the data message to data buffer storage queue described in inventive embodiments
Storage include：
Data message storage after parsing is arrived data buffer storage queue by second core processor, and to described
Data message is stored；Or,
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described first
Core processor is stored to the data message.
In order to make full use of the system resource of double-core, data storage efficiency is improved, further improve system
Reliability, in embodiments of the present invention the data message storage by after parsing are realized to data buffer storage queue
The storage of the data message also includes：
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described second
Core processor obtains the current resource utilization of first core processor, judges that the current resource of itself is used
Whether current more than the first core processor resource utilization of rate, when it is determined that the current resource utilization of itself in
During the current resource utilization of the first core processor, then notify that the first core processor stores the data message,
Otherwise, itself is stored to the data message；Or,
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described first
Core processor obtains the current resource utilization of second core processor, judges that the current resource of itself is used
Whether current more than the second core processor resource utilization of rate, when it is determined that currently the resource utilization of itself is big
When the first core processor current resource utilization, then notify that the second core processor stores the datagram
Text, otherwise, itself is stored to the data message.
A kind of data storage device based on dual core processor is embodiments provided, the device includes：
The data message for by receiving port receiving data message, is sent to the by receiver module
One core processor；
First core processor, produces interruption for receiving the data message, and the data message is deposited
Store up packet receiving buffer queue；
Second core processor, for the data message being taken out from packet receiving buffer queue and being parsed, will solution
The storage of the data message is realized in data message storage after analysis to data buffer storage queue.
Interruption frequently being produced in order to reduce short packages, improving storage efficiency, be further ensured that system can
By property, it is described the data message is sent to into the first core processor before, described device also includes：
FPGA, for receiving the data message；The quantity of the data message to receiving is updated,
And whether the quantity of the data message after judging to update reaches the first amount threshold of setting；After it is determined that updating
The quantity of data message when reaching the first amount threshold of setting, the data message is sent to into the first core
Processor, and the zeroing number of the data message to receiving；Otherwise, the data message is stored in into this
Ground.
In order to reduce packet receiving interruption times, the impact frequently interrupted to storage efficiency is reduced, is further improved
The reliability of system, first core processor in embodiments of the present invention, specifically for receiving the number
After according to message, the quantity of the data message to receiving is updated；The number of the data message that judgement is received
Whether amount reaches the second amount threshold of setting；When it is determined that the quantity of the data message for receiving reaches setting
During the second amount threshold, interruption is produced, and by the zeroing number of the data message for receiving；Or, receiving institute
After stating data message, judge other data messages whether are received in the time span for setting；When it is determined that setting
Time span in when not receiving other data messages, produce interruption, and by the data message for receiving
Zeroing number.
In order to reduce impact of the data parsing to data receiver, the reliability of system is further improved, at this
Second core processor described in inventive embodiments, specifically for the data message storage after parsing is delayed to data
Queue is deposited, and the data message is stored；Or,
First core processor, specifically for data message after second core processor is by parsing
After storing data buffer storage queue, the data message is stored.
In order to make full use of the system resource of double-core, data storage efficiency is improved, further improve system
Reliability, second core processor, is specifically additionally operable to the datagram after parsing in embodiments of the present invention
Text storage obtains the current resource utilization of first core processor to data buffer storage queue, judges current
Whether current more than the first core processor resource utilization of the resource utilization of itself, when it is determined that it is current itself
Resource utilization when the first core processor current resource utilization, then notify the first core processor store
The data message, otherwise, itself is stored to the data message；Or,
First core processor, the data message being specifically additionally operable to after second core processor is by parsing
After storing data buffer storage queue, the current resource utilization of second core processor is obtained, judge current
Whether current more than the second core processor resource utilization of the resource utilization of itself, when it is determined that it is current itself
Resource utilization more than the first core processor current resource utilization when, then notify that the second core processor is deposited
The data message is stored up, otherwise, itself is stored to the data message.
Embodiments provide a kind of date storage method based on dual core processor and device, the method
The switching equipment of dual core processor is suitable for inclusion in, in the method, by receiving port receiving data message,
The data message is sent to into the first core processor；First core processor is received in the data message generation
It is disconnected, and by data message storage to packet receiving buffer queue；Second core processor is from packet receiving buffer queue
Take out data message and parse, the data message storage after parsing is realized into the datagram to data buffer storage queue
The storage of text.Due in embodiments of the present invention by data receiver and data parsing respectively at different kernels
Processed in reason device, therefore, it can the interruption for effectively avoiding data receiver from producing, to data storage
Affect, so as to improve storage efficiency, it is ensured that the reliability of system.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technology of the present invention
Means, and being practiced according to the content of specification, and in order to allow above and other objects of the present invention,
Feature and advantage can become apparent, below especially exemplified by the specific embodiment of the present invention.
Description of the drawings
By the detailed description for reading hereafter preferred embodiment, various other advantages and benefit are for ability
Domain those of ordinary skill will be clear from understanding.Accompanying drawing is only used for the purpose for illustrating preferred embodiment, and and
It is not considered as limitation of the present invention.And in whole accompanying drawing, it is denoted by the same reference numerals identical
Part.In the accompanying drawings：
Fig. 1 is a kind of data storage procedure based on dual core processor provided in an embodiment of the present invention；
Fig. 2 is a kind of detailed process of data storage based on dual core processor provided in an embodiment of the present invention；
Fig. 3 is another concrete mistake based on the data storage of dual core processor provided in an embodiment of the present invention
Journey：
Fig. 4 is that a kind of structure of data storage device based on dual core processor provided in an embodiment of the present invention is shown
It is intended to.
Specific embodiment
In order to avoid in data storage is overweight because receiving the interruption that new data is produced, and affect currently to enter
Capable data storage operations, so as to improve data storage efficiency, it is ensured that system reliability, the embodiment of the present invention
There is provided a kind of date storage method based on dual core processor and device.
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing in accompanying drawing
The exemplary embodiment of the disclosure, it being understood, however, that may be realized in various forms the disclosure and should not be by
Embodiments set forth here is limited.On the contrary, there is provided these embodiments are able to be best understood from this
It is open, and the scope of the present disclosure complete can be conveyed to those skilled in the art.
With reference to explanation accompanying drawing, the embodiment of the present invention is illustrated.
Fig. 1 is a kind of data storage procedure based on dual core processor provided in an embodiment of the present invention, the process
Comprise the following steps：
S101：The data message is sent to first by receiving port receiving data message by switching equipment
Core processor.
In the embodiment of the present invention, switching equipment adopts dual core processor, for when the number for receiving network side transmission
During according to message, packet receiving is produced according to the data message for receiving and is interrupted, the data message storage is cached to packet receiving
In queue, and the data message in buffer queue is parsed, the data message after parsing is stored
To local, wherein, in dual core processor arbitrarily select a kernel to be used for receiving data message, this is chosen
Kernel be the first core processor.
S102：First core processor receives the data message and produces interruption, and the data message is stored
To packet receiving buffer queue.
Switching equipment determines one of kernel as the first core processor of responsible receiving data message,
After first core processor receives the data message of receiving port transmission, interrupted to the datagram by packet receiving
Text carries out packet receiving process, and the data message is stored into packet receiving buffer queue to wait the data message is entered
Row parsing.
S103：Second core processor takes out the data message from packet receiving buffer queue and parses, will parsing
The storage of the data message is realized in data message storage afterwards to data buffer storage queue.
Another kernel outside switching equipment the first core processor of selection is used as responsible parsing data message
Second core processor, second core processor obtain the data message in packet receiving buffer queue, and this is counted
Parsed according to message, the data message after parsing is stored into data buffer storage queue, and deposited according to data
Storage rule, selects different processors to carry out the storage operation of the data message.
In embodiments of the present invention by the switching equipment using dual core processor, by data receiver and data
Parsing is processed in different core processors respectively, therefore, it can effectively avoid data receiver from producing
Raw interruption, the impact to data storage, so as to improve storage efficiency, it is ensured that the reliability of system.
In addition, frequently producing interruption to reduce short data message, the impact to data storage, raising are deposited
Storage efficiency, is further ensured that the reliability of system, described in embodiments of the present invention to send out the data message
Before being sent to the first core processor, the method also includes：
The data message is sent to into FPGA；
The quantity of data messages of the FPGA to receiving is updated, and the data message after judging to update
Whether quantity reaches the first amount threshold of setting；
When it is determined that the quantity of data message after updating reaches the first amount threshold of setting, by the number
The first core processor, and the zeroing number of the data message to receiving are sent to according to message；
Otherwise, the data message is stored in locally.
Specifically, when the receiving port of switching equipment receives the data message of network side, by the datagram
Text is sent to FPGA, and FPGA is responsible for carrying out the data message long encapsulation, and judges the length after encapsulating
Whether the quantity of the data message included in bag reaches the threshold value of setting, includes in long bag after it is determined that encapsulating
The quantity of data message when reaching the threshold value of setting, then the long bag after encapsulating is sent to into the process of the first core
Device, and by the zeroing number of the data message for receiving, re-start the long encapsulation process of a new round；When
It is determined that the quantity of the data message included in long bag after encapsulation not up to set threshold value when, by the datagram
The data of text are saved in the long bag, wherein, the packet structure of long encapsulation process is：Package Magic number
(0xaabbccdd), package total length, comprising in message number, first message length, first message
Appearance, second message length, second message content ..., until package terminates.
The above-mentioned judgement that end whether is encapsulated to long bag in embodiments of the present invention, it is also possible to total according to package
Whether length reaches the threshold value for setting as basis for estimation.
The long encapsulation of data message is processed by FPGA in embodiments of the present invention, reduce first
The encapsulation interruption times of core processor, therefore, the impact frequently interrupted to data storage is reduced, further
Improve storage efficiency, it is ensured that the reliability of system.
Fig. 2 is a kind of detailed process of data storage based on dual core processor provided in an embodiment of the present invention,
The process is comprised the following steps：
S201：Switching equipment is by receiving port receiving data message, and the data message is sent to
FPGA。
S202：The quantity of data messages of the FPGA to receiving is updated, and judges the number after updating
The first amount threshold of setting whether is reached according to the quantity of message, when result of determination is to be, carry out step
S204, otherwise, carries out step S203.
S203：The data message is stored in locally.
S204：When it is determined that the quantity of data message after updating reaches the first amount threshold of setting, will
The data message is sent to the first core processor, and the zeroing number of the data message to receiving.
S205：First core processor receives the data message and produces interruption, and the data message is deposited
Store up packet receiving buffer queue.
S206：Second core processor takes out the data message from packet receiving buffer queue and parses, will solution
The storage of the data message is realized in data message storage after analysis to data buffer storage queue.
In addition, reducing to reduce packet receiving interruption times in embodiments of the present invention
The impact of efficiency, further improves the reliability of system, and first core processor receives the data message
Producing interruption includes：
After first core processor receives the data message, the quantity of the data message to receiving is carried out
Update；Whether the quantity of the data message that judgement is received reaches the second amount threshold of setting；When it is determined that connecing
When the quantity of the data message for receiving reaches the second amount threshold of setting, interruption is produced, and will be received
The zeroing number of data message；Or
After first core processor receives the data message, judge whether connect in the time span for setting
Receive other data messages；When it is determined that not receiving other data messages in the time span of setting, produce
Interrupt, and by the zeroing number of the data message for receiving.
Specifically, the first core processor of switching equipment interrupts to itself packet receiving and is configured, according to setting
Fixed second amount threshold further reduces the number of times of packet receiving interruption, when the first core processor receives data message
When, the data message is carried out interrupting polymerization process, the receiving data packet accouter of itself is added one, is sentenced
Whether the numerical value of the counter after Jia one that breaks reaches the second amount threshold of setting, when it is determined that the number of the counter
When value reaches the second amount threshold of setting, it is determined that meeting down trigger condition, producing interruption carries out data receipts
Bag process, and by the counter O reset.
In order to prevent long-time from not receiving new data message, lead to not the datagram in time to receiving
Text carries out packet receiving process, after the first core processor receives data message, will update timer, and judge timing
Whether device receives new data message in the duration of regulation, when it is determined that receiving new number in the duration of regulation
During according to message, the timer reclocking is updated, otherwise, it determines meeting down trigger condition, produce interruption
Data packet receiving process is carried out, and updates the timer reclocking.
In addition, in embodiments of the present invention in order to reduce impact of the data parsing to data receiver, further
The reliability of raising system, the data message storage by after parsing realize the data to data buffer storage queue
The storage of message includes：
Data message storage after parsing is arrived data buffer storage queue by second core processor, and to described
Data message is stored；Or,
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described first
Core processor is stored to the data message.
Specifically, the second core processor is responsible for carrying out dissection process to the data message for receiving, after parsing
The data message will be stored and wait write operation in data buffer storage queue, to data message in data buffer queue
Write operation is carried out, any one that can select in the first core processor and the second core processor is individually completed,
Can also be completed in the first core processor and the second core processor jointly.
Fig. 3 is a kind of detailed process of data storage based on dual core processor provided in an embodiment of the present invention,
The process is comprised the following steps：
S301：Switching equipment is by receiving port receiving data message, and the data message is sent to
FPGA。
S302：The quantity of data messages of the FPGA to receiving is updated, and judges the number after updating
The first amount threshold of setting whether is reached according to the quantity of message, when result of determination is to be, carry out step
S304, otherwise, carries out step S303.
S303：The data message is stored in locally.
S304：When it is determined that the quantity of data message after updating reaches the first amount threshold of setting, will
The data message is sent to the first core processor, and the zeroing number of the data message to receiving.
S305：After first core processor receives the data message, the number of the data message to receiving
Amount is updated.
S306：Whether the quantity of the data message that judgement is received reaches the second amount threshold of setting, when
When result of determination is to be, step S307 is carried out, otherwise, step S305 is carried out.
S307：When it is determined that the quantity of the data message for receiving reaches the second amount threshold of setting, produce
It is raw to interrupt, by data message storage to packet receiving buffer queue, and by the quantity of the data message for receiving
Reset.
S308：Second core processor takes out data message from packet receiving buffer queue and parses, after parsing
Data message storage to data buffer storage team, and the data message is stored, or at first core
Reason device is stored to the data message.
In embodiments of the present invention by adopting dual core processor, by the reception of data message and data storage
Processed in different kernels respectively, it is to avoid the impact to data storage is interrupted in packet receiving, and by receiving
The long bag of bag processes and interrupts converging operation, further reduces packet receiving interruption times, so as to improve number
According to storage efficiency, it is ensured that the reliability of system.
In addition, improving data storage to make full use of the system resource of double-core in embodiments of the present invention
Efficiency, further improves the reliability of system, in embodiments of the present invention the data message by after parsing
Store data buffer storage queue and realize that the storage of the data message includes：
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described second
Core processor obtains the current resource utilization of first core processor, judges that the current resource of itself is used
Whether current more than the first core processor resource utilization of rate, when it is determined that currently the resource utilization of itself is big
When the first core processor current resource utilization, then notify that the first core processor stores the datagram
Text, otherwise, itself is stored to the data message；Or,
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described first
Core processor obtains the current resource utilization of second core processor, judges that the current resource of itself is used
Whether current more than the second core processor resource utilization of rate, when it is determined that currently the resource utilization of itself is big
When the first core processor current resource utilization, then notify that the second core processor stores the datagram
Text, otherwise, itself is stored to the data message.
Specifically, the second core processor stores the data message after parsing in data buffer storage queue, etc.
Pending write operation, in order to make full use of system resource, by periodically comparing the first core processor and
The current resource utilization of two core processors, the low core processor of prioritizing selection resource utilization carry out data
Write operation, the current resource utilization of each core processor of above-mentioned acquisition is simultaneously compared, both can be
Carry out in first core processor, it is also possible to carry out in the second core processor.
Frequently compare the system that the current resource utilization of each core processor brings and open to save
Pin, the method that the optimal core processor of above-mentioned selection carries out data storage can also pass through set in advance
Weighted value counts the resource utilization of two core processors, according to system within the setting time cycle completing
Meter result is that two core processors distribute data storage weight, and according to the storage weighted value of the distribution, will
The data message preserved in data buffer storage queue is assigned to corresponding core processor and completes write operation.
By taking the data storage for completing 100M bytes for 1 second in dual core processor as an example, the process of the first core
The storage weighted value of device and the distribution of the second core processor is respectively 60% and 40%, preserves in data buffer storage queue
The front 60M data of data, be sent to the first core processor write hard disk buffer queue 1, and rear 40M data are sent
Hard disk buffer queue 2 is write to the second core processor, successively repeatedly, wherein, each data message can only be
Complete is stored in a core processor.
In order to further improve storage efficiency, the weighted value of above-mentioned setting can be according to each core processor
Average resource utilization rate enter Mobile state adjustment, periodically compare each core processor average resource use
Rate, when the difference of the average resource utilization rate of two core processors reaches the threshold value of setting, proportionally
The storage weighted value of two core processors of adjustment, still by taking above-mentioned weight distribution as an example, in the detection of 10 seconds
The average resource utilization rate of the first core processor and the second core processor is obtained in cycle, when the first core processor
Average resource utilization rate be more than the second core processor average resource utilization rate, and difference exceed setting threshold value
When, according to the Dynamic gene (5M) of setting, by the storage weight of the first core processor and the second core processor
Value is adjusted to 55% and 45% respectively, so as to pass through to realize dynamic adjustment, improves data storage efficiency.
Fig. 4 is a kind of data storage device based on dual core processor provided in an embodiment of the present invention, the device
Including：
Receiver module 41, for by receiving port receiving data message, the data message being sent to
First core processor；
First core processor 42, produces interruption for receiving the data message, and by the data message
Store packet receiving buffer queue；
Second core processor 43, for the data message being taken out from packet receiving buffer queue and being parsed, will
The storage of the data message is realized in data message storage after parsing to data buffer storage queue.
Interruption is produced frequently in order to reduce short packages, the impact to data storage improves storage efficiency,
Be further ensured that the reliability of system, it is described the data message is sent to into the first core processor before, institute
Stating device also includes：
FPGA 44, for receiving the data message；The quantity of the data message to receiving is updated,
And whether the quantity of the data message after judging to update reaches the first amount threshold of setting；After it is determined that updating
The quantity of data message when reaching the first amount threshold of setting, the data message is sent to into the first core
Processor, and the zeroing number of the data message to receiving；Otherwise, the data message is stored in into this
Ground.
In order to reduce packet receiving interruption times, the impact frequently interrupted to storage efficiency is reduced, is further improved
The reliability of system, first core processor 42, described specifically for receiving in embodiments of the present invention
After data message, the quantity of the data message to receiving is updated；The data message that judgement is received
Whether quantity reaches the second amount threshold of setting；When it is determined that the quantity of the data message for receiving reaches setting
The second amount threshold when, produce interruption, and by the zeroing number of the data message for receiving；Or, receiving
After the data message, judge other data messages whether are received in the time span for setting；When it is determined that setting
When other data messages are not received in fixed time span, produce interruption, and by the data message for receiving
Zeroing number.
In order to reduce impact of the data parsing to data receiver, the reliability of system is further improved, at this
Second core processor 43 described in inventive embodiments, specifically for the data message storage after parsing is arrived data
Buffer queue, and the data message is stored；Or,
First core processor 42, specifically for datagram after second core processor is by parsing
Text storage is stored to the data message to after data buffer storage queue.
In order to make full use of the system resource of double-core, data storage efficiency is improved, further improve system
Reliability, second core processor 43, is specifically additionally operable to the data after parsing in embodiments of the present invention
Packet storage obtains the current resource utilization of first core processor to data buffer storage queue, judges to work as
Whether current more than the first core processor resource utilization of the front resource utilization of itself, when it is determined that currently certainly
The resource utilization of body then notifies that the first core processor is deposited when the first core processor current resource utilization
The data message is stored up, otherwise, itself is stored to the data message；Or,
First core processor 42, the datagram being specifically additionally operable to after second core processor is by parsing
Text storage obtains the current resource utilization of second core processor to after data buffer storage queue, judges to work as
Whether current more than the second core processor resource utilization of the front resource utilization of itself, when it is determined that currently certainly
When the resource utilization of body is more than the first core processor current resource utilization, then the second core processor is notified
The data message is stored, otherwise, itself is stored to the data message.
Embodiments provide a kind of date storage method based on dual core processor and device, the method
The switching equipment of dual core processor is suitable for inclusion in, in the method, by receiving port receiving data message,
The data message is sent to into the first core processor；First core processor is received in the data message generation
It is disconnected, and by data message storage to packet receiving buffer queue；Second core processor is from packet receiving buffer queue
Take out the data message and parse, the data message storage after parsing is realized into the number to data buffer storage queue
According to the storage of message.Due in embodiments of the present invention by data receiver and data parsing respectively in different
Processed in core processor, therefore, it can the interruption for effectively avoiding data receiver from producing, data are deposited
The impact of storage, so as to improve storage efficiency, it is ensured that the reliability of system.
Algorithm and display be not intrinsic with any certain computer, virtual system or miscellaneous equipment provided herein
It is related.Various general-purpose systems can also be used together based on teaching in this.As described above, structure
It is obvious to make the structure required by this kind of system.Additionally, the present invention is also not for any certain programmed
Language.It is understood that, it is possible to use various programming languages realize the content of invention described herein, and
The description done to language-specific above is for the preferred forms for disclosing the present invention.
In specification mentioned herein, a large amount of details are illustrated.It is to be appreciated, however, that this
Bright embodiment can be put into practice in the case where not having these details.In some instances, not in detail
Known method, structure and technology are shown, so as not to obscure the understanding of this description.
Similarly, it will be appreciated that in order to simplify the disclosure helping understand one in each inventive aspect or
It is multiple, above to, in the description of the exemplary embodiment of the present invention, each feature of the present invention is sometimes by one
Rise and be grouped in single embodiment, figure or descriptions thereof.However, should not be by the method for the disclosure
It is construed to reflect following intention：I.e. the present invention for required protection is required than the institute in each claim clearly
The more features of feature of record.More precisely, as the following claims reflect, sending out
Bright aspect is less than all features of single embodiment disclosed above.Therefore, it then follows specific embodiment
Claims be thus expressly incorporated in the specific embodiment, wherein each claim conduct itself
The separate embodiments of the present invention.
Those skilled in the art be appreciated that the module in the equipment in embodiment can be carried out it is adaptive
Change to answering property and they are arranged in one or more different from embodiment equipment.Can be reality
Apply module or unit or component in example and be combined into a module or unit or component, and in addition can be it
Be divided into multiple submodule or subelement or sub-component.Except in such feature and/or process or unit
Outside at least some excludes each other, (adjoint right will can be included to this specification using any combinations
Ask, make a summary and accompanying drawing) disclosed in all features and so disclosed any method or equipment it is all
Process or unit are combined.Unless expressly stated otherwise, this specification (include adjoint claim,
Summary and accompanying drawing) disclosed in each feature can it is identical by offers, be equal to or similar purpose alternative features
To replace.
Although additionally, it will be appreciated by those of skill in the art that some embodiments described herein include other
Some included features rather than further feature in embodiment, but the combination meaning of the feature of different embodiments
Taste and is within the scope of the present invention and is formed different embodiments.For example, in following claim
In book, embodiment required for protection one of arbitrarily can in any combination mode using.
The all parts embodiment of the present invention can be realized with hardware, or with one or more processor
The software module of upper operation is realized, or is realized with combinations thereof.It will be understood by those of skill in the art that
Can be realized using microprocessor or digital signal processor (DSP) in practice according to of the invention real
Apply some of some or all parts in the data storage device based on dual core processor of example or complete
Portion's function.The present invention is also implemented as performing some or all of method as described herein
Equipment or program of device (for example, computer program and computer program).It is such to realize this
Bright program can be stored on a computer-readable medium, or can have the shape of one or more signal
Formula.Such signal can be downloaded from internet website and be obtained, or provide on carrier signal, or
There is provided with any other form.
It should be noted that above-described embodiment the present invention will be described rather than limits the invention, and
And those skilled in the art can design replacement enforcement without departing from the scope of the appended claims
Example.In the claims, any reference symbol between bracket should not be configured to claim
Limit.Word "comprising" does not exclude the presence of element not listed in the claims or step.Positioned at element it
Front word "a" or "an" does not exclude the presence of multiple such elements.The present invention can be by means of bag
Include the hardware of some different elements and by means of properly programmed computer realizing.It is some listing
In the unit claim of device, several in these devices can be come concrete by same hardware branch
Embody.The use of word first, second, and third does not indicate that any order.Can be by these word solutions
It is interpreted as title.
Obviously, those skilled in the art can carry out various changes and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these modification and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of date storage method based on dual core processor, it is characterised in that the method is applied to bag
Switching equipment containing dual core processor, the method include：
By receiving port receiving data message, the data message is sent to into the first core processor；
First core processor receives the data message and produces interruption, and by data message storage to receipts
Bag buffer queue；
Second core processor takes out the data message from packet receiving buffer queue and parses, after parsing
The storage of the data message is realized in data message storage to data buffer storage queue.
2. method according to claim 1, it is characterised in that described that the data message is sent
To before the first core processor, methods described also includes：
The data message is sent to into FPGA；
The quantity of data messages of the FPGA to receiving is updated, and the data message after judging to update
Whether quantity reaches the first amount threshold of setting；
When it is determined that the quantity of data message after updating reaches the first amount threshold of setting, by the number
The first core processor, and the zeroing number of the data message to receiving are sent to according to message；
Otherwise, the data message is stored in locally.
3. method according to claim 1, it is characterised in that first core processor receives institute
Stating data message generation interruption includes：
After first core processor receives the data message, the quantity of the data message to receiving is carried out
Update；Whether the quantity of the data message that judgement is received reaches the second amount threshold of setting；When it is determined that connecing
When the quantity of the data message for receiving reaches the second amount threshold of setting, interruption is produced, and will be received
The zeroing number of data message；Or
After first core processor receives the data message, judge whether connect in the time span for setting
Receive other data messages；When it is determined that not receiving other data messages in the time span of setting, produce
Interrupt, and by the zeroing number of the data message for receiving.
4. method according to claim 1, it is characterised in that the data message by after parsing
Store data buffer storage queue and realize that the storage of the data message includes：
Data message storage after parsing is arrived data buffer storage queue by second core processor, and to described
Data message is stored；Or,
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described first
Core processor is stored to the data message.
5. method according to claim 1, it is characterised in that the data message by after parsing
The storage that the data message is realized in data buffer storage queue is stored, is also included：
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described second
Core processor obtains the current resource utilization of first core processor, judges that the current resource of itself is used
Whether current more than the first core processor resource utilization of rate, when it is determined that currently the resource utilization of itself is big
When the first core processor current resource utilization, then notify that the first core processor stores the datagram
Text, otherwise, itself is stored to the data message；Or,
Data message after parsing is stored and arrives data buffer storage queue by second core processor, and described first
Core processor obtains the current resource utilization of second core processor, judges that the current resource of itself is used
Whether current more than the second core processor resource utilization of rate, when it is determined that currently the resource utilization of itself is big
When the first core processor current resource utilization, then notify that the second core processor stores the datagram
Text, otherwise, itself is stored to the data message.
6. a kind of data storage device based on dual core processor, it is characterised in that the device includes：
The data message for by receiving port receiving data message, is sent to the by receiver module
One core processor；
First core processor, produces interruption for receiving the data message, and the data message is deposited
Store up packet receiving buffer queue；
Second core processor, for the data message being taken out from packet receiving buffer queue and being parsed, will solution
The storage of the data message is realized in data message storage after analysis to data buffer storage queue.
7. device according to claim 6, it is characterised in that described that the data message is sent
To before the first core processor, described device also includes：
FPGA, for receiving the data message；The quantity of the data message to receiving is updated,
And whether the quantity of the data message after judging to update reaches the first amount threshold of setting；After it is determined that updating
The quantity of data message when reaching the first amount threshold of setting, the data message is sent to into the first core
Processor, and the zeroing number of the data message to receiving；Otherwise, the data message is stored in into this
Ground.
8. device according to claim 6, it is characterised in that first core processor, specifically
For receiving after the data message, the quantity of the data message to receiving is updated；Judge to receive
To the quantity of data message whether reach the second amount threshold of setting；When it is determined that the data message for receiving
Quantity when reaching the second amount threshold of setting, produce interruption, and by the quantity of the data message for receiving
Reset；Or, after receiving the data message, judging whether receive other data in the time span for setting
Message；When it is determined that other data messages are not received in the time span of setting, produce interruption, and will connect
The zeroing number of the data message for receiving.
9. device according to claim 6, it is characterised in that second core processor, specifically
For the data message storage after parsing is arrived data buffer storage queue, and the data message is stored；
Or,
First core processor, specifically for data message after second core processor is by parsing
After storing data buffer storage queue, the data message is stored.
10. device according to claim 6, it is characterised in that second core processor, tool
Body is additionally operable to the data message storage after parsing to data buffer storage queue, is obtained first core processor and is worked as
Front resource utilization, judges whether current more than the first core processor money of the current resource utilization of itself
Source utilization rate, when it is determined that the current resource utilization of itself is in the current resource utilization of the first core processor
When, then notify that the first core processor stores the data message, otherwise, itself is deposited to the data message
Storage；Or,
First core processor, the datagram being specifically additionally operable to after second core processor is by parsing
Text storage obtains the current resource utilization of second core processor to after data buffer storage queue, judges to work as
Whether current more than the second core processor resource utilization of the front resource utilization of itself, when it is determined that currently certainly
When the resource utilization of body is more than the first core processor current resource utilization, then the second core processor is notified
The data message is stored, otherwise, itself is stored to the data message.
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