CN107680954A - Semiconductor test unit and semi-conductor test structure - Google Patents
Semiconductor test unit and semi-conductor test structure Download PDFInfo
- Publication number
- CN107680954A CN107680954A CN201610620291.3A CN201610620291A CN107680954A CN 107680954 A CN107680954 A CN 107680954A CN 201610620291 A CN201610620291 A CN 201610620291A CN 107680954 A CN107680954 A CN 107680954A
- Authority
- CN
- China
- Prior art keywords
- chamfering
- weld pad
- metal level
- semiconductor test
- test unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The present invention provides a kind of semiconductor test unit and semi-conductor test structure, and the semiconductor test unit includes the metal level stacked gradually and the weld pad above top layer metallic layer, wherein, the metal level and the weld pad are equipped with chamfering.The present invention on weld pad and the metal level being disposed below by setting chamfering; can in laser raceway groove technique by the initial point position of caused micro-damage or micro-crack to Cutting Road off-centring; chip protection structure and chip are made it away from; probability or the order of severity that chip edge layering occurs are reduced, so as to improve the reliability of product.
Description
Technical field
The present invention relates to field of semiconductor structures, more particularly to a kind of semiconductor test unit and semiconductor test knot
Structure.
Background technology
The purpose of laser trench technique (Laser groove process) in semiconductor packaging process is to remove
Whole circuit structure layers in cutting zone are needed inside wafer Cutting Road (wafer scribe lane), so as to be follow-up
Technique (for example, mechanicalness is cut) reserved working space, avoids direct mechanicalness from cutting the destruction to chip edge.
The common recognition of industry is at present：Inappropriate laser trench processing parameter setting can cause Cutting Road internal structure layer
Heavy damage, this is one of the main reason for initiation chip edge is layered (die edge delamination) problem.This be by
During laser is quickly burnt in Cutting Road region, different structure sheafs (such as test structure (Test is necessarily passed
Key) and with respect to depletion region etc.), and especially in boundary area, local trickle explosion may be triggered；Such a explosion is easy
Occur in passivation layer or low-k dielectric layers, if its scope is excessive or beyond control, it will the risk for bringing chip edge to be layered.
Because the structure design of Cutting Road occurred in the fabrication stage of wafer, and laser raceway groove technique occurs in encapsulation rank
Section, and the parameter device condition of each encapsulation factory differs, simultaneously as laser cutting is as a rule, will be inevitable
Test structure (including laminated metal layer and Al weld pads positioned at surface) region is touched, so as to bring the wind that chip edge is layered
Danger.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of semiconductor test unit and half
Conductor test structure, the chip side brought when being cut in the prior art using laser raceway groove technique to Cutting Road for reducing
The problem of fate layer.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor test unit, the semiconductor
Test cell includes the metal level that stacks gradually and the weld pad above top layer metallic layer, wherein, the metal level and described
Weld pad is equipped with chamfering.
As a kind of preferred scheme of the semiconductor test unit of the present invention, the chamfering is 45 ° of chamferings.
As a kind of preferred scheme of the semiconductor test unit of the present invention, the projection of chamfering hypotenuse and institute on the weld pad
The projection for stating chamfering hypotenuse on metal level coincides.
As a kind of preferred scheme of the semiconductor test unit of the present invention, the size of the weld pad is more than or equal to described
The size of metal level, the length of the chamfering right-angle side is the weld pad Breadth Maximum
As a kind of preferred scheme of the semiconductor test unit of the present invention, the chamfering is located at the metal level and described
Four vertex of weld pad.
As a kind of preferred scheme of the semiconductor test unit of the present invention, the chamfering is located at the metal level and described
Two vertex of weld pad the same side.
The present invention also provides a kind of semi-conductor test structure, and the semi-conductor test structure is located at the Cutting Road of chip periphery
Interior, including multiple first semiconductor test units, the first semiconductor test unit includes metal level and the position stacked gradually
Weld pad above top layer metallic layer, wherein, the metal level and the weld pad are equipped with chamfering.
As a kind of preferred scheme of the semi-conductor test structure of the present invention, the chamfering is 45 ° of chamferings.
As a kind of preferred scheme of the semi-conductor test structure of the present invention, the projection of chamfering hypotenuse and institute on the weld pad
The projection for stating chamfering hypotenuse on metal level coincides.
As a kind of preferred scheme of the semi-conductor test structure of the present invention, the size of the weld pad is more than or equal to described
The size of metal level, the length of the chamfering right-angle side is the weld pad Breadth Maximum
As a kind of preferred scheme of the semi-conductor test structure of the present invention, the first semiconductor test unit is described
It is located at four vertex of the metal level and the weld pad in single file, duplicate rows or multirow distribution, the chamfering in Cutting Road.
As a kind of preferred scheme of the semi-conductor test structure of the present invention, the first semiconductor test unit is described
It is distributed in Cutting Road in duplicate rows, the chamfering is located at two drift angles of the metal level and the weld pad close to the chip-side
Place.
As a kind of preferred scheme of the semi-conductor test structure of the present invention, the semi-conductor test structure also includes second
Semiconductor test unit, the second semiconductor test unit are located in the middle part of the Cutting Road, in single in the middle part of the Cutting Road
Row, duplicate rows or multirow distribution, the second semiconductor test unit include the metal level that stacks gradually of multilayer and positioned at top layer gold
Belong to the weld pad above layer；
The first semiconductor test unit is distributed in the Cutting Road in duplicate rows, and is surveyed positioned at second semiconductor
The outside of unit is tried, the chamfering is located at two vertex of the metal level and the weld pad close to the chip-side.
As described above, the semiconductor test unit and semi-conductor test structure of the present invention, have the advantages that：This hair
It is bright by setting chamfering on weld pad and the metal level being disposed below, can be in laser raceway groove technique by caused micro-damage
Or the initial point position of micro-crack has made it away from chip protection structure and chip, has reduced chip to Cutting Road off-centring
The probability or the order of severity that edge delamination occurs, so as to improve the reliability of product.
Brief description of the drawings
Fig. 1 and Fig. 2 is shown as the overlooking the structure diagram of the semiconductor test unit provided in the embodiment of the present invention one.
Fig. 3 to Fig. 5 is shown as the overlooking the structure diagram of the semi-conductor test structure provided in the embodiment of the present invention two.
Component label instructions
1 semiconductor test unit
11st, 211 metal level
12nd, 212 weld pad
13rd, 213 chamfering
2 semi-conductor test structures
21 first semiconductor test units
22 second semiconductor test units
3 Cutting Roads
4 chips
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Fig. 5.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only showing the component relevant with the present invention in diagram rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
Fig. 1 to Fig. 2 is referred to, the present invention provides a kind of semiconductor test unit 1, and the semiconductor test unit 1 is at least
Including：The metal level 11 and the weld pad 12 above the metal level 11 of top layer stacked gradually, wherein, the metal level 11 and institute
State weld pad 12 and be equipped with chamfering 13.
As an example, the chamfering 13 is 45 ° of chamferings.
As an example, on the weld pad 12 hypotenuse of chamfering 13 projection with the metal level 11 on the hypotenuse of chamfering 13 projection
Coincide.If it should be noted that the size of the metal level 11 relatively under, its width be less than the weld pad 12 on it is described fall
During the width of the weld pad 12 between angle 13, the chamfering 13 can be not provided with the metal level 11.
As an example, the size of the weld pad 12 is more than or equal to the size of the metal level 11, i.e., such as Fig. 1 and Fig. 2 institutes
In the top view shown, the length and width of the weld pad 12 are more than or equal to the length and width of the metal level 11.
The design rule of the chamfering is：Assuming that be not provided with the weld pad 12 of the chamfering 13 is shaped as rectangle,
Its length is more than its width, chooses its Breadth Maximum and is drawn as diameter and is justified；Certainly, it is assumed that be not provided with the described of the chamfering 13
When being shaped as square of weld pad 12, choose any maximal side and drawn as diameter and justified；Using 45 ° of chamferings as principle, drawn circle is done
The part intercepted between the intersection point of the weld pad 12 of the tangent line of shape, the tangent line and rectangular or square is the chamfering
13.Above-mentioned design may insure to design optimal chamfering on the premise of effective usable floor area of the weld pad 12 is not reduced.
Maximum length by the right-angle side of the chamfering 13 of above-mentioned design rule design is the weld pad Breadth MaximumWith
Be not provided with the weld pad 12 of the chamfering 13 size be 50umx50um shape exemplified by, the right-angle side of chamfering 13
Maximum length is 14.6um.But in view of the presence of design tolerance, in the rational margin of tolerance, the right-angle side of chamfering 13
Minimum length can be 0.2 times of the weld pad Breadth Maximum, i.e., the length of the described right-angle side of chamfering 13 is the weld pad 12
Breadth MaximumThat is, equally using be not provided with the chamfering 13 the weld pad 12 size as
Exemplified by 50umx50um shape, the minimum length of the right-angle side of chamfering 13 is 10um.
As an example, the chamfering 13 can be located at four vertex of the metal level 11 and the weld pad 12, such as Fig. 1
It is shown；Equally, the chamfering 13 can also be located at two vertex of the metal level 11 and the same side of the weld pad 12, such as scheme
Shown in 2.
The present invention, can be with by setting the chamfering 13 on the weld pad 12 and the metal level 11 being disposed below
By the initial point position of caused micro-damage or micro-crack, (what i.e. laser contacted with the chamfering 13 rises in laser raceway groove technique
Initial point position) to Cutting Road off-centring, chip protection structure and chip have been made it away from, chip edge layering has been reduced and occurs
Probability or the order of severity, so as to improve the reliability of product.
Embodiment two
Fig. 3 to Fig. 5 is referred to, the present invention also provides a kind of semi-conductor test structure 2, the semi-conductor test structure 2
In in the Cutting Road 3 of the periphery of chip 4, including multiple first semiconductor test units 21, the first semiconductor test unit 21
Including the metal level 211 stacked gradually and the weld pad 212 above the metal level 211 of top layer, wherein, the metal level 211
And the weld pad 212 is equipped with chamfering 213.
As an example, the chamfering 213 is 45 ° of chamferings.
As an example, the projection of the hypotenuse of chamfering 213 and the hypotenuse of chamfering 213 on the metal level 211 on the weld pad 212
Projection coincides.If it should be noted that the size of the metal level 211 relatively under, its width be less than the weld pad 212 on
During the width of the weld pad 212 between the chamfering 213, the chamfering 213 can be not provided with the metal level 211.
As an example, the size of the weld pad 212 is more than or equal to the size of the metal level 211, i.e., such as Fig. 3 to Fig. 5
In shown top view, the length and width of the weld pad 212 are more than or equal to the length and width of the metal level 211.
The design rule of the chamfering is：Assuming that be not provided with the weld pad 212 of the chamfering 213 is shaped as square
Shape, its length are more than its width, choose its Breadth Maximum and are drawn as diameter and are justified；Certainly, it is assumed that be not provided with the chamfering 213
When being shaped as square of the weld pad 212, choose any maximal side and drawn as diameter and justified；Using 45 ° of chamferings as principle, institute is done
The part intercepted between the intersection point of the weld pad 212 of the circular tangent line of picture, the tangent line and rectangular or square is described
Chamfering 213.Above-mentioned design may insure to design on the premise of effective usable floor area of the weld pad 212 is not reduced optimal
Chamfering.Maximum length by the right-angle side of the chamfering 213 of above-mentioned design rule design is the weld pad Breadth MaximumExemplified by being not provided with the size of the weld pad 212 of the chamfering 213 as 50umx50um shape, it is described fall
The maximum length of the right-angle side of angle 213 is 14.6um.But in view of the presence of design tolerance, in the rational margin of tolerance, institute
The minimum length for stating the right-angle side of chamfering 213 can be 0.2 times of the weld pad Breadth Maximum, i.e., the described right-angle side of chamfering 213
Length is the Breadth Maximum of weld pad 212That is, equally to be not provided with described in the chamfering 213
Exemplified by the size of weld pad 212 is 50umx50um shape, the minimum length of the right-angle side of chamfering 213 is 10um.
It is distributed as an example, the first semiconductor test unit 21 can be in single file in the Cutting Road 3, can also
It is distributed in duplicate rows, can also is in that multirow is distributed, the chamfering 213 is located at four tops of the metal level 211 and the weld pad 212
At angle；The example that Fig. 3 is distributed with the first semiconductor test unit 21 in the Cutting Road 3 in single file.
As an example, the first semiconductor test unit 21 is distributed in the Cutting Road 3 in duplicate rows, the chamfering
213 are located at two vertex of the metal level 211 and the weld pad 212 close to the side of chip 4, as shown in Figure 4.
As an example, the semi-conductor test structure 2 also includes the second semiconductor test unit 22, second semiconductor
Test cell 22 is distributed, described second positioned at the middle part of Cutting Road 3 at the middle part of Cutting Road 3 in single file, duplicate rows or multirow
Semiconductor test unit 22 includes metal level 211 and the weld pad above the metal level 211 of top layer that multilayer stacks gradually
212；The first semiconductor test unit 21 is distributed in the Cutting Road 3 in duplicate rows, and is surveyed positioned at second semiconductor
The outside of unit 22 is tried, the chamfering 213 is located at the metal level 211 and the weld pad 212 close to the two of the side of chip 4
Individual vertex；In Fig. 5, the example with the second semiconductor test unit 2 at the middle part of Cutting Road 3 in single file distribution.
The present invention by setting the chamfering 213 on the weld pad 212 and the metal level 211 being disposed below,
Can by the initial point position of caused micro-damage or micro-crack, (i.e. laser connects with the chamfering 213 in laser raceway groove technique
Tactile initial point position) to Cutting Road off-centring, chip protection structure and chip have been made it away from, has reduced chip edge point
The probability or the order of severity that layer occurs, so as to improve the reliability of product.
In summary, semiconductor test unit and semi-conductor test structure of the invention, the semiconductor test unit bag
The metal level stacked gradually and the weld pad above top layer metallic layer are included, wherein, the metal level and the weld pad are equipped with
Chamfering.The present invention be able to will be produced by setting chamfering on weld pad and the metal level being disposed below in laser raceway groove technique
Raw micro-damage or the initial point position of micro-crack have made it away from chip protection structure and chip to Cutting Road off-centring,
Probability or the order of severity that chip edge layering occurs are reduced, so as to improve the reliability of product.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (13)
- A kind of 1. semiconductor test unit, it is characterised in that the semiconductor test unit include the metal level that stacks gradually and Weld pad above top layer metallic layer, wherein, the metal level and the weld pad are equipped with chamfering.
- 2. semiconductor test unit according to claim 1, it is characterised in that：The chamfering is 45 ° of chamferings.
- 3. semiconductor test unit according to claim 1, it is characterised in that：On the weld pad projection of chamfering hypotenuse with The projection of chamfering hypotenuse coincides on the metal level.
- 4. semiconductor test unit according to claim 1, it is characterised in that：The size of the weld pad is more than or equal to institute The size of metal level is stated, the length of the chamfering right-angle side is the weld pad Breadth Maximum
- 5. semiconductor test unit according to claim 1, it is characterised in that：The chamfering is located at the metal level and institute State four vertex of weld pad.
- 6. semiconductor test unit according to claim 1, it is characterised in that：The chamfering is located at the metal level and institute State two vertex of weld pad the same side.
- A kind of 7. semi-conductor test structure, in the Cutting Road of chip periphery, it is characterised in that the semi-conductor test structure Including multiple first semiconductor test units, the first semiconductor test unit includes the metal level stacked gradually and positioned at top The weld pad of layer metal layer, wherein, the metal level and the weld pad are equipped with chamfering.
- 8. semi-conductor test structure according to claim 7, it is characterised in that：The chamfering is 45 ° of chamferings.
- 9. semi-conductor test structure according to claim 7, it is characterised in that：On the weld pad projection of chamfering hypotenuse with The projection of chamfering hypotenuse coincides on the metal level.
- 10. semi-conductor test structure according to claim 7, it is characterised in that：The size of the weld pad is more than or equal to The size of the metal level, the length of the chamfering right-angle side is the weld pad Breadth Maximum
- 11. semi-conductor test structure according to claim 7, it is characterised in that：The first semiconductor test unit exists It is located at four drift angles of the metal level and the weld pad in single file, duplicate rows or multirow distribution, the chamfering in the Cutting Road Place.
- 12. semi-conductor test structure according to claim 7, it is characterised in that：The first semiconductor test unit exists It is distributed in duplicate rows in the Cutting Road, the chamfering is located at the metal level and the weld pad close to two of the chip-side Vertex.
- 13. semi-conductor test structure according to claim 7, it is characterised in that：The semi-conductor test structure also includes the second semiconductor test unit, and the second semiconductor test unit is positioned at described In the middle part of Cutting Road, include more in single file, duplicate rows or multirow distribution, the second semiconductor test unit in the middle part of the Cutting Road The metal level and the weld pad above top layer metallic layer that layer stacks gradually；The first semiconductor test unit is distributed in the Cutting Road in duplicate rows, and is located at the second semiconductor test list The outside of member, the chamfering are located at two vertex of the metal level and the weld pad close to the chip-side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620291.3A CN107680954B (en) | 2016-08-01 | 2016-08-01 | Semiconductor test unit and semiconductor test structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620291.3A CN107680954B (en) | 2016-08-01 | 2016-08-01 | Semiconductor test unit and semiconductor test structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107680954A true CN107680954A (en) | 2018-02-09 |
| CN107680954B CN107680954B (en) | 2019-12-10 |
Family
ID=61133869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610620291.3A Active CN107680954B (en) | 2016-08-01 | 2016-08-01 | Semiconductor test unit and semiconductor test structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107680954B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11710706B2 (en) | 2018-11-22 | 2023-07-25 | Samsung Electronics Co., Ltd. | Method of dicing a semiconductor substrate having a scribe lane defined therein |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334720C (en) * | 2003-10-29 | 2007-08-29 | 台湾积体电路制造股份有限公司 | Bonding pad structure |
| CN101093824A (en) * | 2006-06-20 | 2007-12-26 | 台湾积体电路制造股份有限公司 | Interconnected lines structure and wafer |
| TW200807622A (en) * | 2006-07-19 | 2008-02-01 | Taiwan Semiconductor Mfg | An interconnect structure, a method for fabricating the same and a wafer |
| CN101740544A (en) * | 2008-11-07 | 2010-06-16 | 台湾积体电路制造股份有限公司 | Semiconductor test pad structures |
| CN102779792A (en) * | 2011-05-13 | 2012-11-14 | 格罗方德半导体公司 | Die seal for integrated circuit device |
-
2016
- 2016-08-01 CN CN201610620291.3A patent/CN107680954B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334720C (en) * | 2003-10-29 | 2007-08-29 | 台湾积体电路制造股份有限公司 | Bonding pad structure |
| CN101093824A (en) * | 2006-06-20 | 2007-12-26 | 台湾积体电路制造股份有限公司 | Interconnected lines structure and wafer |
| TW200807622A (en) * | 2006-07-19 | 2008-02-01 | Taiwan Semiconductor Mfg | An interconnect structure, a method for fabricating the same and a wafer |
| CN101740544A (en) * | 2008-11-07 | 2010-06-16 | 台湾积体电路制造股份有限公司 | Semiconductor test pad structures |
| CN102779792A (en) * | 2011-05-13 | 2012-11-14 | 格罗方德半导体公司 | Die seal for integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11710706B2 (en) | 2018-11-22 | 2023-07-25 | Samsung Electronics Co., Ltd. | Method of dicing a semiconductor substrate having a scribe lane defined therein |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107680954B (en) | 2019-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10438903B2 (en) | Crack stop barrier and method of manufacturing thereof | |
| US8749027B2 (en) | Robust TSV structure | |
| US20200395279A1 (en) | Pad Design for Reliability Enhancement in Packages | |
| US20190259744A1 (en) | Method for fabricating substrate structure and substrate structure fabricated by using the method | |
| TW201917835A (en) | Semiconductor structure and method for manufacturing the same | |
| US20200350261A1 (en) | Electronic package and substrate structure having chamfers | |
| US9947644B2 (en) | Semiconductor package | |
| US20070102787A1 (en) | Capacitor integrated in a structure surrounding a die | |
| US20080220220A1 (en) | Semiconductor die having increased usable area | |
| CN107680954A (en) | Semiconductor test unit and semi-conductor test structure | |
| US20210296261A1 (en) | Method for fabricating substrate structure | |
| TWI621237B (en) | Semiconductor package and its semiconductor wiring substrate | |
| CN104795385A (en) | System-in-package module and manufacture method for a system-in-package module | |
| US20140131840A1 (en) | Wafer and method of manufacturing the same | |
| US9711478B2 (en) | Semiconductor device with an anti-pad peeling structure and associated method | |
| TW201528473A (en) | Wafer-level chip stacked assembly without MICRO-CONTACT between the chips and its fabricating method | |
| US20150001714A1 (en) | Stress-resilient chip structure and dicing process | |
| CN203800038U (en) | Chip protection structure | |
| US8314501B2 (en) | Semiconductor chip package structure, semiconductor chip and semiconductor chip group | |
| US10622314B2 (en) | Chip package structure | |
| TWI766054B (en) | Semiconductor packages including die over-shift indicating patterns | |
| CN117352461A (en) | Semiconductor chip with crack-stop ring structure | |
| CN203733789U (en) | Chip protective structure | |
| TW201606958A (en) | Integrated circuit package | |
| CN105470242A (en) | Sealing ring and semiconductor structure with same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |