TWI766054B - Semiconductor packages including die over-shift indicating patterns - Google Patents

Abstract

A semiconductor package includes a package substrate including a die attachment region, a semiconductor die attached to the die attachment region, and a die over-shift indicating pattern disposed on or in the package substrate and spaced apart from the die attachment region. The die over-shift indicating pattern is used as a reference pattern for obtaining a shifted distance of the semiconductor die.

Description

Semiconductor package including pattern indicating excessive die displacement

The present disclosure relates to semiconductor packaging technology, and more particularly, to semiconductor packaging including a die excessive displacement indicating pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean Patent Application No. 10-2017-0148848 filed on November 9, 2017, the entire contents of which are incorporated herein by reference.

Various semiconductor packages have been employed in electronic products. For example, various types of semiconductor packages have been employed in mobile systems such as smartphones or tablet computers. In particular, mobile systems require compact semiconductor packages, eg, thin and light semiconductor packages with large memory capacity and small form factor.

According to one embodiment, a semiconductor package includes: a package substrate including a die attach area; a semiconductor die attached to the die attach area; and a die excessive displacement indication pattern, The die excessive displacement indicating pattern is disposed on or in the package substrate and is spaced apart from the die attach area. The die excessive displacement indicating pattern is used as a reference pattern for obtaining the displacement distance of the semiconductor die.

According to another embodiment, a semiconductor package includes: a package substrate including a die attach region; a first semiconductor die attached to the die attach region; a second semiconductor die a die, the second semiconductor die is stacked on the first semiconductor die and deviated from the first semiconductor die; and a die excessive displacement indication pattern is provided on the package substrate on or in the package substrate and separated from the die attach area. The die excessive displacement indicating pattern is used as a reference pattern for obtaining the displacement distance of the second semiconductor die.

10‧‧‧Semiconductor Packaging

10A‧‧‧Semiconductor Package

10S‧‧‧Side Surface

12‧‧‧Semiconductor Packaging

20‧‧‧Semiconductor Packaging

21‧‧‧Packaging substrate

22‧‧‧Semiconductor Die

23‧‧‧Die Attachment Area

24‧‧‧Side Surface

24O‧‧‧Scheduled cutting area

24S‧‧‧Sawing position

25‧‧‧Side surface

40‧‧‧Semiconductor Packaging

100‧‧‧Packaging substrate

100E‧‧‧Edge Region

100R‧‧‧Package area

100S‧‧‧Stripe substrate

101‧‧‧Saw cut side surface

103‧‧‧First surface

105‧‧‧Second surface

110‧‧‧Main Layer

120‧‧‧First Dielectric Layer

130‧‧‧Second dielectric layer

140‧‧‧Sawing area

150‧‧‧Conductive Interconnection Pattern

151‧‧‧First Interconnect Pattern

153‧‧‧Internal interconnection pattern

155‧‧‧Second interconnect pattern

170‧‧‧External Connectors

200‧‧‧Semiconductor Die

200B‧‧‧Semiconductor Die Stacking

200E‧‧‧Edge

200S‧‧‧Semiconductor Die

201‧‧‧Side surface

203‧‧‧Die attach area

210‧‧‧First semiconductor die

230‧‧‧Second semiconductor die

300‧‧‧Die Excessive Displacement Indication Pattern

300A‧‧‧Die Excessive Displacement Indication Pattern

300B‧‧‧Die Excessive Displacement Indication Pattern

301‧‧‧First Die Excessive Displacement Indication Pattern/Die Excessive Displacement Indication Pattern

301A‧‧‧First Die Excessive Displacement Indication Pattern

301B‧‧‧First Die Excessive Displacement Indication Pattern

303‧‧‧The second die excessive displacement indication pattern/die excessive displacement indication pattern

303A‧‧‧Excessive displacement of the second die pattern

303B‧‧‧Excessive displacement of the second die pattern

Part 303S‧‧‧

400‧‧‧Sawing area

500‧‧‧adhesive layer

510‧‧‧First Adhesive Layer

530‧‧‧Second adhesive layer

600‧‧‧Encapsulation

601‧‧‧Saw cut side surface

700‧‧‧Inspection Tools

7800‧‧‧Memory Card

7810‧‧‧Memory

7820‧‧‧Memory Controller

7830‧‧‧Host

8710‧‧‧Electronic systems

8711‧‧‧Controller

8712‧‧‧Input/Output Devices

8713‧‧‧Memory

8714‧‧‧Interface

8715‧‧‧Busbar

A-A’‧‧‧line

B-B’‧‧‧line

D1‧‧‧First distance

D2‧‧‧Second distance

D3‧‧‧Third distance

D4‧‧‧The fourth distance

M‧‧‧ side allowance

Various embodiments of the present disclosure will become more apparent from the accompanying drawings and the accompanying detailed description, in which: FIG. 1 is a plan view illustrating a semiconductor package according to an embodiment; FIG. 2 is along line AA' of FIG. 1 FIG. 3 is a plan view illustrating a method for detecting an excessive die shift phenomenon occurring in a semiconductor package according to an embodiment; FIG. 4 is a cross-sectional view taken along line BB' of FIG. 3 ; 5 is a cross-sectional view illustrating a die excessive displacement indicating pattern of a semiconductor package according to another embodiment; FIG. 6 is a cross-sectional view illustrating a die excessive displacement indicating pattern of a semiconductor package according to still another embodiment; A cross-sectional view of a semiconductor package according to still another embodiment; FIG. 8 is a plan view illustrating a phenomenon of excessive die shift occurring in a semiconductor package according to an embodiment; FIG. 9 is an electronic device illustrating a memory card including the semiconductor package according to the embodiment. block diagram of the system; and FIG. 10 is a block diagram illustrating another electronic system including a semiconductor package according to an embodiment.

Terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to those of ordinary skill in the art to which the embodiments belong. If defined in detail, terms can be interpreted according to the definition. Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and are not used to limit only the elements themselves or to imply a particular order.

Semiconductor packages may include electronic devices such as semiconductor wafers or semiconductor dies. A semiconductor wafer or semiconductor die can be obtained by dividing a semiconductor substrate, such as a wafer, into a plurality of pieces using a die sawing process. The semiconductor die may correspond to a memory die, a logic die (including an application specific integrated circuit (ASIC) die), or a system on a chip (SoC). Memory chips may include dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, NAND type flash memory circuits, NOR type flash memory circuits, magnetic Random Access Memory (MRAM) circuits, Resistive Random Access Memory (ReRAM) circuits, Ferroelectric Random Access Memory (FeRAM) circuits, or Phase Change Random Access Memory (PcRAM) circuits. A logic wafer may include logic circuits integrated on a semiconductor substrate. Semiconductor packaging may be employed in communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems.

As the size of the semiconductor package has decreased, the distance between the side surface of the semiconductor package and the semiconductor die built in the semiconductor package has decreased. In this case, cracks may be formed in the package substrate of the semiconductor package, or semiconductor dies built in the semiconductor package may be seen through the sidewall of the semiconductor package. To prevent the above failed configurations, it may be desirable that the semiconductor die be separated from the sidewalls of the semiconductor package by at least a certain distance.

In order to manufacture a semiconductor package such that the semiconductor dies in the semiconductor package are separated from the sidewalls of the semiconductor package by at least a certain distance, it may be necessary to detect or verify the location of the semiconductor dies disposed in the semiconductor package. Accordingly, the following embodiments of the present disclosure provide solutions for determining whether to place conductor dies in an allowed displacement region after attaching a semiconductor die to a package substrate.

Throughout the specification, the same reference numerals refer to the same elements. Thus, even if a reference number is not mentioned or described with reference to one figure, the reference number may be referenced or described with reference to another figure. In addition, even if a reference numeral is not shown in one figure, the reference numeral may be referred to or described with reference to another figure.

FIG. 1 is a plan view illustrating a semiconductor package 10 according to an embodiment. Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1 .

1 and 2 , the semiconductor package 10 may include a package substrate 100 , a semiconductor die 200 disposed on the package substrate 100 , and an encapsulant 600 covering and protecting the semiconductor die 200 . Encapsulation 600 is omitted from FIG. 1 for the purpose of simplicity of illustration. The semiconductor die 200 may be attached to the package substrate 100 using the adhesive layer 500 . The semiconductor package 10 may also include a die excessive displacement indicating pattern 300 . The die excessive displacement indication pattern 300 may be used as an indicator that provides information as to whether the semiconductor die 200 is excessively displaced from the die attach region 203 . The package substrate 100 may include a die attach region 203 . If the semiconductor die 200 is attached to the package substrate 100 to extend beyond the allowable attachment tolerance area during the attachment process, the semiconductor die 200 may be considered to be in a die over-displacement state. The die excessive displacement indication pattern 300 may be used as an indication pattern for determining whether the semiconductor die 200 is in a die excessive displacement state.

The die excessive displacement indicating pattern 300 may be disposed in the edge region 100E of the package substrate 100 adjacent to the sawed side surface 101 of the package substrate 100 . The die excessive displacement indicating pattern 300 may be disposed on the first surface 103 of the package substrate 100 . The first surface 103 of the package substrate 100 may correspond to the surface to which the semiconductor die 200 is attached. The edge region 100E of the package substrate 100 may correspond to the region between the die attach region 203 and the sawed side surface 101 of the package substrate 100 . Therefore, the die excessive displacement indicating pattern 300 may be disposed between the side surface 101 of the package substrate 100 and the die attaching region 203 .

The die excessive displacement indicating pattern 300 may be formed on the first surface 103 of the package substrate 100 when viewed from the plan view of FIG. 1 . The excessive grain displacement indicating pattern 300 may be formed to be recognized by the human eye without any tools or with an optical microscope. The excessive grain displacement indicating pattern 300 can be visually recognized by the human eye without any tools or with a relatively low magnification optical microscope. Therefore, even without the use of high performance equipment (eg, a relatively high magnification electron microscope or an inspection tool using X-rays), it can be more easily determined whether the semiconductor die 200 is in a state of excessive grain displacement.

The die excessive displacement indicating pattern 300 may be formed on the first surface 103 of the package substrate 100 to be exposed at the first surface 103 , or may be formed in the package substrate 100 to be seen through a portion of the package substrate 100 . For example, the die excessive displacement indicating pattern 300 may be formed by engraving a portion of the first surface 103 of the package substrate 100 to have a groove shape. More specifically, the die excessive displacement indicating pattern 300 may be formed by engraving a portion of the first surface 103 of the package substrate 100 to have a groove shape using a laser. In an embodiment, the die excessive displacement indicating pattern 300 may be formed by etching or patterning the first dielectric layer 120 of the package substrate 100 using an etching process.

The first dielectric layer 120 may be one of many layers constituting the package substrate 100 . For example, the first dielectric layer 120 may be a solder resist layer disposed on the surface of the body layer 110 included in the package substrate 100 .

The package substrate 100 may have an interconnect structure that electrically connects the semiconductor die 200 with an external device or an external system. The interconnect structure may include conductive interconnect patterns 150 . The package substrate 100 may include a body layer 110 including a dielectric layer, a first dielectric layer 120 disposed on a surface of the body layer 110 , and a first dielectric layer 120 disposed on another surface of the body layer 110 opposite to the first dielectric layer 120 . The second dielectric layer 130 . The conductive interconnection patterns 150 may include first interconnection patterns 151 disposed on the surface of the body layer 110 and covered by the first dielectric layer 120 . The conductive interconnection pattern 150 may further include a second interconnection pattern 155 disposed on the other surface of the body layer 110 and covered by the second dielectric layer 130 . The surface of the second dielectric layer 130 opposite the body layer 110 may provide the second surface 105 of the package substrate 100 .

The conductive interconnection patterns 150 may further include inner interconnection patterns 153 that substantially penetrate the body layer 110 to electrically connect the first interconnection patterns 151 with the second interconnection patterns 155 . The internal interconnection patterns 153 may include conductive vias substantially penetrating the body layer 110 . The second dielectric layer 130 may be formed to expose a portion of each of the second interconnect patterns 155 . External connectors 170 (eg, solder balls) may be attached to the exposed portions of the second interconnection patterns 155 , respectively. The second dielectric layer 130 may contain solder resist material.

Referring again to FIG. 1 , the die excessive displacement indicating pattern 300 may be formed to have a line shape extending in a direction substantially parallel to the sawing region 400 that physically separates the plurality of semiconductor packages 10 from each other. The sawing area 400 may correspond to the area along which the sawing process is performed.

The semiconductor package 10 may be manufactured through a batch manufacturing process. Specifically, a plurality of semiconductor dies 200 may be attached to a strip substrate composed of a plurality of package substrates 100 connected to each other, and a protective layer (corresponding to the encapsulant 600 shown in FIG. 2 ) may be molded to cover Semiconductor die 200, thereby forming a molded product. Subsequently, the strip substrate and the protective layer may be cut along the sawing area 400 with a saw blade to physically separate the package substrates 100 from each other. The sawing area 400 may be provided when designing the strip substrate. The die excessive displacement indicating pattern 300 may be formed to include a pattern of horizontal stripes extending in a direction substantially parallel to the sawing region 400 .

If the sawing process for cutting the strip substrate along the sawing area 400 is normally performed, the sawing side surface 101 of the package substrate 100 may be substantially parallel to the sawing area 400 . Accordingly, the die excessive displacement indicating pattern 300 may be formed to include a horizontal bar pattern extending in a direction substantially parallel to the sawing side surface 101 of the package substrate 100 .

The side surface 10S of the semiconductor package 10 may include a sawn side surface 101 of the package substrate 100 and a sawn side surface 601 of the encapsulant 600 , as illustrated in FIG. 2 . The die excessive displacement indicating pattern 300 may include a line-shaped pattern extending in a direction parallel to the sawed side surface 101 of the package substrate 100 . Therefore, the die excessive displacement indicating pattern 300 may be parallel to the sawed side surface 101 of the package substrate 100 and the sawed side surface 601 of the encapsulant 600 when viewed from a plan view.

If the semiconductor die 200 is normally attached to the die attach region 203 , the die excessive displacement indicating pattern 300 may be parallel to the line at the side surface 201 of the semiconductor die 200 or the side of the die attach region 203 . The die excessive displacement indication pattern 300 may be provided separately from the die attach area 203 . The die excessive displacement indicating pattern 300 may be disposed between the sawing region 400 and the die attaching region 203 . The die excessive displacement indication pattern 300 may include a first die excessive displacement indication pattern 301 and a second die excessive displacement indication pattern 303 . The second die excessive displacement indicating pattern 303 may be disposed between the first die excessive displacement indicating pattern 301 and the die attaching region 203 .

Still referring to FIG. 1 , if the semiconductor die 200 is normally attached to the die attach region 203 , the side surface 201 of the semiconductor die 200 may be separated from the sawing region 400 by a first distance D1 . If the sawing process is normally performed along the sawing area 400, the sawing side surface 101 of the package substrate 100 may be separated from the line at the side of the die attach area 203 by the first distance D1. The first die over-displacement indicating pattern 301 may be disposed to be spaced apart from the sawing region 400 by a second distance D2. The first die excessive displacement indicating pattern 301 may extend in parallel with the sawed side surface 101 of the package substrate 100 . The second die excessive displacement indication pattern 303 may be disposed apart from the first die excessive displacement indication pattern 301 by a third distance D3. The second die excessive displacement indication pattern 303 may be disposed to be separated from the line at the side of the die attach area 203 by a fourth distance D4. The second die excessive displacement indicating pattern 303 may be spaced apart from the first die excessive displacement indicating pattern 301 and may be parallel to the first die excessive displacement indicating pattern 301 .

The fourth distance D4 may be equal to the third distance D3. The third distance D3 and the fourth distance D4 may be equal to the second distance D2. Therefore, the degree of displacement of the semiconductor die 200 can be easily obtained by inspecting the semiconductor die 200 together with the first die excessive displacement indicating pattern 301 or the second die excessive displacement indicating pattern 303 . That is, the amount of displacement of the semiconductor die 200 can be found using a relatively low magnification inspection tool by determining the first die excessive displacement indicating pattern 301 and the second die excessive displacement indicating pattern 303 .

Even though FIG. 1 illustrates that the die excessive displacement indicating pattern 300 includes only two parallel line-shaped patterns as the first die excessive displacement indicating pattern 301 and the second die excessive displacement indicating pattern 303 that are parallel to and spaced apart from each other example, the present disclosure is not limited thereto. For example, in some other embodiments, the die excessive displacement indicating pattern 300 may include three or more linear patterns that are parallel to each other.

Although FIG. 1 illustrates an example in which the die excessive displacement indication pattern 300 is disposed at one edge region 100E of the package substrate 100 , the present disclosure is not limited thereto. For example, in some other embodiments, the die excessive displacement indicating pattern 300 may be disposed at two or more edges of the package substrate 100 . More specifically, the die excessive displacement indicating patterns 300 may be disposed at four edges of the package substrate 100 .

3 is a plan view illustrating a method of detecting an excessive die shift phenomenon occurring in a semiconductor package according to an embodiment. Fig. 4 is a cross-sectional view taken along line B-B' of Fig. 3 .

Referring to FIGS. 3 and 4 , the semiconductor package 10A may include a semiconductor die 200S that is attached to the strip substrate 100S prior to forming the encapsulation ( 600 of FIG. 2 ). The strip substrate 100S may include a plurality of package regions 100R (corresponding to the package substrate 100 of FIG. 1 ) separated from each other by a sawing process. The package regions 100R of the strip substrate 100S may be connected to each other by the sawing region 140 . The sawing area 140 may include a scribe lane area. Each of the package regions 100R may include the die attach region 203 illustrated in FIG. 1 .

The semiconductor die 200S may be attached to the package region 100R using a die attach process. Ideally, the semiconductor die 200S must be attached to the package area 100R in perfect alignment with the die attach area 203 . However, due to processing tolerances of the die attach process, the semiconductor die 200S may be laterally displaced from the die attach region 203 . In this case, if the amount of displacement of the semiconductor die 200S exceeds the allowable range, an excessive grain displacement phenomenon occurs.

3 and 4 illustrate an example in which the phenomenon of excessive grain displacement occurs. For example, if a die excessive displacement phenomenon occurs, the semiconductor die 200S may cover at least a portion 303S of the die excessive displacement indicating pattern 300 when viewed from a plan view. That is, the portion 303S of the die excessive displacement indicating pattern 300 may be covered by the edge portion 200E of the semiconductor die 200S. The die excessive displacement indicating pattern 300 may be arranged such that when the semiconductor die 200S is displaced from the die attach region 203 by more than a distance greater than the allowable range, at least a portion (eg, the portion 303S) of the die excessive displacement indicating pattern 300 Covered with semiconductor die 200S.

As illustrated in FIG. 4 , the portion 303S of the die excessive displacement indication pattern 300 may be covered by the semiconductor die 200S. Therefore, the portion 303S of the die excessive displacement indicating pattern 300 cannot be seen from the top view due to the presence of the semiconductor die 200S over the portion 303S of the die excessive displacement indicating pattern 300 . In this case, visual inspection can be performed through the examiner's eye (i.e., human eye) or by using an inspection tool 700 such as an optical microscope with relatively low magnification. Because the grain over-displacement indicating pattern 300 is formed to have a sufficiently large size so that the shape of the grain over-displacement indicating pattern 300 can be identified using only a relatively low-magnification optical microscope, relatively high magnification can be unnecessary The inspection tool is used to observe the die excessive displacement indicating pattern 300 . For example, if the excessive grain displacement indicating pattern 300 is formed to have a width and a thickness (or depth) of at least several tens of microns and a length of at least several hundreds of microns, it is possible to avoid using an inspection tool with a relatively high magnification. The die excessive displacement indication pattern 300 is identified below.

If the portion 303S of the die over-displacement indicating pattern 300 is not visible when viewed from the top view due to the semiconductor die 200S, the semiconductor die 200S may be considered to be over-displaced. In this case, the die attach process can be regarded as abnormally performed, and other processes cannot be performed.

If the sawing process is subsequently performed despite the excessive grain displacement phenomenon, the side margin M of the protective layer (corresponding to the encapsulation 600 of FIG. 2 ) is reduced, as illustrated in FIG. 8 . The semiconductor package 12 illustrated in FIG. 8 corresponds to a comparative example. 8 , if the semiconductor die 22 is laterally displaced from the die attach region 23 of the package substrate 21 toward the side surface 24 of the semiconductor package 12 , the side surface 25 of the semiconductor die 22 may become closer to the side of the semiconductor package 12 surface 24 to reduce the side margin M corresponding to the distance between the semiconductor die 22 and the side surface 24 of the semiconductor package 12 .

If the side margin M is decreased, the width of the sidewall portion of the protective layer covering the semiconductor die 22 is also decreased, thereby causing failure to see the semiconductor die 22 built in the semiconductor package 12 through the sidewall portion of the protective layer. configuration. In this case, moisture may easily penetrate into the semiconductor package 12 through the interface between the protective layer and the package substrate 21 , thereby reducing the reliability of the semiconductor package 12 or causing the semiconductor die 22 to fail. In addition, if moisture penetrates into the semiconductor package 12 , the semiconductor die 22 may be lifted off the package substrate 21 or delaminated from the package substrate 100 . In addition, if moisture penetrates into the semiconductor package 12, the adhesive strength between the protective layer and the package substrate 21 may decrease, resulting in a delamination phenomenon of the protective layer.

Furthermore, the sawing process may be performed with a saw blade aligned with the displaced sawing position 24S displaced from the predetermined sawing region 24O due to the process tolerance of the sawing process. In this case, the side surfaces 24 of the semiconductor package 12 may become closer to the semiconductor die 22, resulting in a shortage of the side margin M.

As the semiconductor packages employed in electronic systems have become smaller and smaller, the positional margin for semiconductor dies disposed in the semiconductor packages has decreased. According to the embodiments of the present disclosure, it is possible to easily inspect a semiconductor package in which an excessive grain displacement phenomenon occurs to sort out a semiconductor package having a poor margin on the protective layer side. As a result, the processing yield and reliability of the semiconductor package can be prevented from deteriorating due to die attach failure. Whether the phenomenon of excessive grain displacement occurs can be verified by checking the excessive grain displacement indicating pattern ( 300 in FIG. 4 ) before forming the protective layer. In addition, the degree of displacement of the semiconductor die 22 can also be confirmed by examining the excessive grain displacement indicating pattern ( 300 of FIG. 4 ) before the formation of the protective layer.

Referring again to FIGS. 3 and 4 , if the portion 303S of the die excessive displacement indicating pattern 300 is not visible due to the semiconductor die 200S when viewed from the top view, the strip substrate can be selectively sorted out in subsequent processing A portion of the semiconductor package 10A including the semiconductor die 200S is fabricated thereon. In this way, since the die attach failure is detected in the intermediate processing step, it is possible to prevent the semiconductor package having the insufficient side margin from being delivered to the customer after the sawing process. If the die excessive displacement indicating pattern 300 is normally observed when viewed from a top view, a subsequent molding process may be performed to form a protective layer covering the semiconductor die, and a sawing process may be used to cut the strip substrate 100S to A plurality of semiconductor packages are provided separated from each other.

Referring again to FIG. 3 , if the die excessive displacement indicating pattern 300 includes a plurality of patterns, eg, the first die excessive displacement indicating pattern 301 and the second die excessive displacement indicating pattern 303 that are parallel to each other, the semiconductor die 200S can be inspected degree of displacement. For example, if the portion 303S of the first die excessive displacement indicating pattern 301 cannot be seen due to the displaced semiconductor die 200S when viewed from the top view, the degree of displacement of the semiconductor die 200S is evaluated as relatively low. On the contrary, if the first die excessive displacement indicating pattern 301 and the second die excessive displacement indicating pattern 303 cannot be seen due to the displaced semiconductor die 200S when viewed from the top view, the degree of displacement of the semiconductor die 200S was assessed as relatively high.

More specifically, as described with reference to FIG. 1, if the second distance D2, the third distance D3, and the fourth distance D4 are equal to each other and the first crystal grain excessive displacement indicating pattern 301 and the second crystal grain are observed when viewed from a top view If the grain excessive displacement indicates the pattern 303, the displacement distance or displacement degree of the semiconductor die 200S (or 200) may be estimated to be smaller than the fourth distance D4. If the second distance D2, the third distance D3, and the fourth distance D4 are equal to each other and only the first die excessive displacement indicating pattern 301 is observed when viewed from the top view, the displacement of the semiconductor die 200S (or 200) can be The distance or degree of displacement is evaluated to be greater than the fourth distance D4 and less than twice the fourth distance D4. If the second distance D2, the third distance D3, and the fourth distance D4 are equal to each other and the first die excessive displacement indicating pattern 301 and the second die excessive displacement indicating pattern 303 are not observed when viewed from the top view, the The displacement distance or displacement degree of the semiconductor die 200S (or 200 ) is evaluated to be equal to or greater than at least twice the fourth distance D4 . Therefore, at least one of the die excessive displacement indicating patterns 301 and 303 may be used as a reference pattern for obtaining the displacement distance of the semiconductor die 200S (or 200 ).

As described above, after attaching the semiconductor die 200S (or 200 ), inspecting or observing the die over-displacement indicating pattern 300 may help to determine the occurrence of the die over-displacement phenomenon.

FIG. 5 is a cross-sectional view illustrating a die excessive displacement indicating pattern 300A employed in the semiconductor package 20 according to another embodiment.

5 , the die excessive displacement indicating pattern 300A included in the semiconductor package 20 may be located at substantially the same position as the die excessive displacement indicating pattern 300 illustrated in FIG. 2 when viewed from a plan view. The die excessive displacement indicating pattern 300A may include a first die excessive displacement indicating pattern 301A and a second die excessive displacement indicating pattern 303A which are parallel to each other. The die excessive displacement indicating pattern 300A may be disposed between the first dielectric layer 120 and the body layer 110 constituting the package substrate 100. That is, the die excessive displacement indicating pattern 300A may be covered by the first dielectric layer 120 (eg, a solder resist layer). Even if the die excessive displacement indicating pattern 300A is covered by the first dielectric layer 120 , since the first dielectric layer 120 is formed of the solder resist layer as a translucent material, it can be visually seen through the first dielectric layer 120 Excessive die displacement indicates pattern 300A.

The die excessive displacement indicating pattern 300A may be located at the same level as the first interconnection pattern 151 in the package substrate 100 , wherein the first interconnection pattern 151 is disposed between the first dielectric layer 120 and the body layer 110 . The die excessive displacement indicating pattern 300A may be formed to include a conductive layer such as a copper layer. For example, the die excessive displacement indicating pattern 300A may be formed of substantially the same conductive layer as the first interconnect pattern 151 . Simultaneously with the formation of the first interconnection pattern 151, the die excessive displacement indication pattern 300A may also be formed. That is, the first interconnection pattern 151 and the die excessive displacement indicating pattern 300A may be simultaneously formed by patterning the conductive layer.

In FIG. 5, the same reference numerals as used in FIG. 2 denote the same elements.

FIG. 6 is a cross-sectional view illustrating a die excessive displacement indicating pattern 300B of a semiconductor package 30 according to yet another embodiment.

Referring to FIG. 6 , the die excessive displacement indicating pattern 300B of the semiconductor package 30 may be located at substantially the same position as the die excessive displacement indicating pattern 300 illustrated in FIG. 2 when viewed from a plan view. The die excessive displacement indicating pattern 300B may include a first die excessive displacement indicating pattern 301B and a second die excessive displacement indicating pattern 303B which are parallel to each other. The die excessive displacement indicating pattern 300B may be formed to protrude from the first surface 103 corresponding to the surface of the first dielectric layer 120 . Accordingly, the die excessive displacement indicating pattern 300B may be formed to protrude from the package substrate 100 . The die excessive displacement indicating pattern 300B may be a pattern printed on the surface of the first dielectric layer 120 with ink.

In FIG. 6, the same reference numerals as those used in FIG. 2 denote the same elements.

FIG. 7 is a cross-sectional view illustrating a semiconductor package 40 according to yet another embodiment. In Fig. 7, the same reference numerals as those used in Fig. 2 denote the same elements.

Referring to FIG. 7 , the die excessive displacement indicating pattern 300 may be applied to the semiconductor package 40 including the semiconductor die stack 200B. The first semiconductor die 210 may be attached to the die attach region 23 (see FIG. 8 ) of the package substrate 100 by using the first adhesive layer 510 and the second semiconductor die 230 may be attached to the package substrate 100 using the second adhesive layer 530 . The first semiconductor die 210 is used to implement the semiconductor die stack 200B. Because the semiconductor die stack 200B is achieved by stacking at least two semiconductor dies (ie, the first semiconductor die 210 and the second semiconductor die 230 ), the probability of an excessive die displacement phenomenon occurs in the semiconductor package 40 will become higher.

As exemplified in FIG. 7 , the first semiconductor die 210 and the second semiconductor die 230 may be designed to be shifted and stacked in sequence. In this case, edge portions of the second semiconductor die 230 may laterally protrude from the side surfaces of the first semiconductor die 210 to provide a reverse stepped structure. Because the second semiconductor die 230 is laterally displaced from the first semiconductor die 210 , the probability of excessive die displacement phenomenon in the semiconductor package 40 becomes higher.

The die over-displacement indicating pattern 300 of the semiconductor package 40 may be used as a means to effectively check for a die over-displacement phenomenon that can occur while forming the semiconductor die stack 200B. In this case, the die excessive displacement indicating pattern 300 may be disposed at a position suitable for inspecting the second semiconductor die 230 that may be displaced. For example, the die excessive displacement indicating pattern 300 may be arranged such that when the second semiconductor die 230 is laterally displaced from the die attach region 23 by a distance greater than the allowable range, at least a portion of the die excessive displacement indicating pattern 300 is The second semiconductor die 230 covers.

According to the above embodiments, a semiconductor package including a die excessive displacement indicating pattern is provided. Whether the semiconductor die attached to the package substrate is displaced may be assessed using the die excessive displacement indication pattern. Therefore, the semiconductor package including the displaced semiconductor die can be sorted in advance before forming the protective layer. As a result, a normal semiconductor package having only a side margin larger than the allowable range can be selectively provided.

FIG. 9 is a block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiment. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the embodiment.

The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that stored data is read out or stored data is read in response to a read/write request from the host 7830 .

10 is a block diagram illustrating an electronic system 8710 including at least one of the packages according to an embodiment. The electronic system 8710 may include a controller 8711 , an input/output device 8712 and a memory 8713 . The controller 8711, input/output devices 8712, and memory 8713 may be coupled to each other through a bus 8715 that provides a path for data to move.

In embodiments, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these elements. The controller 8711 or the memory 8713 may include one or more of the semiconductor packages according to embodiments of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and/or commands, etc. to be executed by the controller 8711 .

Memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, the flash memory can be installed in an information processing system such as a mobile terminal or a desktop computer. Flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

The electronic system 8710 may also include an interface 8714 configured to send data to and receive data from the communication network. The interface 8714 may be of the wired or wireless type. For example, interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending/receiving system. either.

If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 can be used for applications such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced A communication system based on technologies such as Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution) or Wibro (Wireless Broadband Internet).

Embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions can be made without departing from the scope and spirit of the present disclosure and the appended claims.

10‧‧‧Semiconductor Packaging

10S‧‧‧Side Surface

100‧‧‧Packaging substrate

100E‧‧‧Edge Region

101‧‧‧Saw cut side surface

200‧‧‧Semiconductor Die

201‧‧‧Side surface

203‧‧‧Die attach area

300‧‧‧Die Excessive Displacement Indication Pattern

301‧‧‧First Die Excessive Displacement Indication Pattern/Die Excessive Displacement Indication Pattern

303‧‧‧The second die excessive displacement indication pattern/die excessive displacement indication pattern

400‧‧‧Sawing area

A-A’‧‧‧line

D1‧‧‧First distance

D2‧‧‧Second distance

D3‧‧‧Third distance

D4‧‧‧The fourth distance

Claims (18)

A semiconductor package comprising: a package substrate including a die attach area; a semiconductor die attached to the die attach area; and a die excessive displacement indication pattern, the A die over-displacement indication pattern is provided on or in the package substrate and is spaced apart from the die attach area, wherein the die over-displacement indication pattern is used for obtaining the semiconductor A reference pattern of displacement distances of dies, wherein the excessive die displacement indication pattern is set such that when the semiconductor die is displaced by a distance greater than an allowable range relative to the die attachment region, the die Excessive grain displacement indicates that at least a portion of the pattern is covered by the semiconductor die. The semiconductor package of claim 1, wherein the die excessive displacement indicating pattern includes a line-shaped pattern parallel to lines at the sides of the die attach area. The semiconductor package of claim 1, wherein the die excessive displacement indicating pattern includes two line-shaped patterns that are spaced apart from each other and parallel to each other. The semiconductor package of claim 1, wherein the die excessive displacement indicating pattern is a groove-shaped pattern engraved at a surface of the package substrate. The semiconductor package of claim 4, wherein the groove-shaped pattern formation is included in a solder resist layer in the package substrate. The semiconductor package of claim 1, wherein the die excessive displacement indicating pattern protrudes from a surface of the package substrate. The semiconductor package of claim 1, wherein the die excessive displacement indication pattern is an ink-printed pattern provided on a surface of the package substrate. The semiconductor package of claim 1, wherein the die excessive displacement indicates The patterns are located at substantially the same level as the interconnect patterns formed in the package substrate. The semiconductor package of claim 1, wherein the die excessive displacement indicating pattern includes a conductive layer. The semiconductor package of claim 1, wherein the die excessive displacement indicating pattern is disposed between a side surface of the package substrate and the die attach area. The semiconductor package of claim 11, wherein the die excessive displacement indicating pattern is a linear pattern parallel to the side surface of the package substrate. The semiconductor package of claim 1, wherein the die excessive displacement indication pattern comprises: a first die excessive displacement indication pattern, the first die excessive displacement indication pattern being parallel to the side surface of the package substrate extending; and a second die over-displacement indication pattern disposed on the first die over-displacement indication pattern and the die parallel to the first die over-displacement indication pattern between die attachment regions, wherein the distance between the second die over-displacement indicating pattern and the die attachment region is substantially equal to the distance between the first die over-displacement indicating pattern and the second die attachment region Grain excess displacement indicates the distance between patterns. A semiconductor package comprising: a package substrate including a die attach area; a first semiconductor die attached to the die attach area; a second semiconductor die , the second semiconductor die is stacked on the first semiconductor die and is offset from the first semiconductor die; and a die excessive displacement indication pattern is provided on the package on the substrate or in the package substrate and separated from the die attach area, wherein the die excessive displacement indication pattern is used as a reference pattern for obtaining the displacement distance of the second semiconductor die, wherein the die excessive displacement indication pattern is set so that when the second semiconductor die is The excessive displacement of the die indicates that at least a portion of the pattern is covered by the second semiconductor die when the die is displaced relative to the die attachment region by a distance greater than an allowable range. The semiconductor package of claim 13, wherein the die excessive displacement indicating pattern comprises a line-shaped pattern parallel to lines at sides of the die attach area. The semiconductor package of claim 13, wherein the die excessive displacement indicating pattern includes two line-shaped patterns that are spaced apart from each other and parallel to each other. The semiconductor package of claim 13, wherein the die excessive displacement indicating pattern is a groove-shaped pattern engraved at the surface of the package substrate. The semiconductor package of claim 13, wherein the die excessive displacement indicating pattern protrudes from a surface of the package substrate. The semiconductor package of claim 13, wherein the die excessive displacement indication pattern is located at substantially the same level as an interconnect pattern formed in the package substrate.

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