CN107665921A - A kind of trench semiconductor device - Google Patents
A kind of trench semiconductor device Download PDFInfo
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- CN107665921A CN107665921A CN201610625419.5A CN201610625419A CN107665921A CN 107665921 A CN107665921 A CN 107665921A CN 201610625419 A CN201610625419 A CN 201610625419A CN 107665921 A CN107665921 A CN 107665921A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 108
- 239000004020 conductor Substances 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 60
- 230000004888 barrier function Effects 0.000 claims description 50
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 43
- 239000001301 oxygen Substances 0.000 claims description 43
- 229910052760 oxygen Inorganic materials 0.000 claims description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 239000000377 silicon dioxide Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 230000007797 corrosion Effects 0.000 claims description 10
- 238000005260 corrosion Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910003978 SiClx Inorganic materials 0.000 claims description 8
- 239000012774 insulation material Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- 230000008719 thickening Effects 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000002156 mixing Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 230000003628 erosive effect Effects 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000002305 electric material Substances 0.000 claims 1
- -1 which includes Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 13
- 230000000903 blocking effect Effects 0.000 abstract description 4
- 239000002210 silicon-based material Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 241000790917 Dioxys <bee> Species 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 208000005168 Intussusception Diseases 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention discloses a kind of trench semiconductor device, and different-thickness trench sidewall insulating layer is set in drift layer, conductive material is filled in groove, is additionally included in inside drift layer and sets groove structure；Compared with prior art, suppress channel bottom edge spike electric field, multiple peak value electric fields are formed in drift layer, improve device reverse blocking voltage or forward conduction ability.
Description
Technical field
The present invention relates to a kind of trench semiconductor device, and the invention further relates to the preparation method of trench semiconductor device.
Background technology
Semiconductor power device, such as field effect transistor switch device, IGBT or Schottky rectifying device it is expected low electric conduction
Resistance and high blocking voltage.For this there has been proposed new construction for accomplishing this.
Including introduced in device it is multiple there is insulating materials inner wall trench, while conductive material is set in groove,
Change the semi-conductor electricity field distribution between groove, the low on-resistance of device or high blocking voltage are realized with this；
This structure forms single spike electric field in space, and in trench bottom up and down in channel bottom edge semi-conducting material
High electric field is formed in the insulating barrier in portion, this electric field is higher than semi-conducting material avalanche breakdown electric field, therefore draws following problem, first
Because of single peak value electric field, when increasing the breakdown reverse voltage of device, the conducting resistance rapid decrease of device, said structure is uncomfortable
For high tension apparatus；Secondly because of spike electric field, device premature breakdown is caused, doping concentration carries in the drift layer of suppression device
Rise；Finally because introducing high electric field in device inside insulating barrier, hot carrier can be caused to damage channel bottom insulating barrier, influence device
The reliability of part.
The content of the invention
The present invention proposes for above-mentioned one or more problems, there is provided a kind of trench semiconductor device, further relates to device
Manufacture method.
A kind of trench semiconductor device, including：Substrate layer, it is semi-conducting material；Drift layer, it is the first conductive semiconductor material
Material, on substrate layer；Multiple grooves, inside drift layer surface or drift layer, trench wall is provided with insulating barrier, ditch
Groove sidewall insulating barrier sets two or more thickness, is upper-thin-lower-thick, it is different insulative material that trench sidewall insulating layer bottom, which includes,
Material is formed by stacking, and trench wall insulating barrier parcel conductive material, it is metal or doped polycrystalline semi-conducting material that conductive material, which includes,；
Semiconductor junction, it is schottky junction or PN junction positioned at drift layer surface.It is insulation material of the same race that wherein trench sidewall insulating layer, which includes,
Material；It is silica, silicon nitride or aluminum oxide that the composition of different insulative material trench side wall insulating layer, which includes,.Described trenched side-wall
Manufacture method comprises the following steps, is removed being provided with deposit filling silicon nitride, etching in the groove of insulating barrier silica inwall
Trench interiors divide silicon nitride, erosion removal trench sidewall insulating layer silica, remove silicon nitride in groove, carry out thermal oxide work
Skill, insulating barrier silica is grown in trenched side-wall, forms the side wall insulating layer of two thickness, again repeatedly said process, is formed
The side wall insulating layer of three thickness.Drift layer internal groove and drift layer surface grooves are included in device surface projection alternately to arrange
Row.
A kind of trench semiconductor device, including：Substrate layer, it is semi-conducting material；Drift layer, it is the first conductive semiconductor material
Material, on substrate layer；Multiple grooves, inside drift layer surface or drift layer, trench wall is provided with insulating barrier, ditch
Bottom, which is provided with, in groove mixes oxygen polysilicon layer, mixes oxygen polysilicon layer and abuts against trench wall surface of insulating layer, side wall mixes oxygen polysilicon
Layer is gradually thickening from top to bottom, and the oxygen amount of mixing for mixing oxygen polysilicon gradually rises on remote trench wall insulating barrier direction, groove
Interior setting conductive material, it is metal or doped polycrystalline semi-conducting material that conductive material, which includes,；Semiconductor junction, positioned at drift layer table
Face, it is schottky junction or PN junction.Trench wall insulating barrier includes being formed by stacking for different insulative material, and it is oxygen that insulating materials, which includes,
SiClx, silicon nitride or aluminum oxide.The manufacture method for mixing oxygen polysilicon layer of bottom setting comprises the following steps in described groove,
Deposit filling being provided with the groove of insulating barrier inwall and mix oxygen polysilicon, mixed in deposition process the oxygen content of oxygen polysilicon by
Edge up height, mix the corrosion of oxygen polysilicon, because corrosion rate is different and corrosion order is under upper, formation mix oxygen polysilicon layer from
It is up to lower gradually thickening.Trenched side-wall noted herein mixes oxygen polysilicon oxygen content scope for 20% to 80%.Inside drift layer
Groove and drift layer surface grooves include to be alternately arranged in device surface projection.
A kind of trench semiconductor device includes：Substrate layer, it is semi-conducting material；Drift layer, it is the first conductive semiconductor material
Material, on substrate layer；Multiple grooves, positioned at drift layer surface, groove is divided into two parts up and down by isolated insulation material；
Upper trench sidewall sets insulating barrier, sets conductive material in upper groove, and contacted with device surface electrode metal, bottom ditch
Groove inwall sets insulating barrier, and lower trench sidewalls abut against isolated insulation positions of materials and are not provided with insulating barrier, and lower trench sidewalls are faced
It is schottky barrier junction to include by isolated insulation material surface, sets conductive material in lower channel, wherein conductive material includes
For metal or doped polycrystalline semi-conducting material；Semiconductor junction, it is schottky junction or PN junction positioned at drift layer surface.It is described every
It is heavy insulation material layer from insulating materials or lower channel bottom insulation layer.Described upper groove or the side wall of lower channel are exhausted
Edge layer, two or more thickness are set, are upper-thin-lower-thick.Described upper groove or the side wall insulating layer bottom table of lower channel
Oxygen polysilicon layer is mixed in face, setting, gradually thickening from top to bottom.Drift layer internal groove and drift layer surface grooves are in device surface
Projection is included to be alternately arranged.
A kind of trench semiconductor device, including：Substrate layer, it is semi-conducting material；Drift layer, it is the first conductive semiconductor material
Material, on substrate layer；Multiple grooves, inside drift layer surface and drift layer, trench wall sets insulating barrier, groove
Interior setting conductive material, conductive material contacts with device surface electrode metal in drift layer surface grooves, drift layer internal groove
Interior conductive material contacts with drift layer semi-conducting material, and it is metal or doped polycrystalline semi-conducting material that wherein conductive material, which includes,
Lower trench includes setting the second conducting semiconductor material area；Semiconductor junction, it is schottky junction or PN positioned at drift layer surface
Knot.Drift layer internal groove and drift layer surface grooves include to be alternately arranged in device surface projection.
In said structure of the present invention, when drift layer internal groove fills metal, contact of the metal with semi-conducting material includes
For schottky barrier junction contact or it is no rectifying contact, drift layer internal groove filling metal is included for high-melting-points such as tungsten, platinum
Metal, to realize in metal surface deposition of semiconductor material or insulating materials；In said structure of the present invention, it can be set in drift layer
Put low-resistance region, position includes horizontal level drift layer region in the middle part of groove, for reducing conducting resistance, position include upper groove and
Region between lower groove, for forming peak value electric field in drift layer, in order to form peak value electric field in drift layer, it is additionally included in
It is the second conducting semiconductor material that drift layer internal groove upper surface, which sets inversion regime,；In said structure of the present invention, in trench bottom
Portion can set inversion regime i.e. the second conducting semiconductor material；In said structure of the present invention, mixed in the filling of drift layer internal groove
During miscellaneous polysilicon, it is preferably provided with the second conductive type impurity and is doped, also includes entering polycrystalline semiconductor material row metal such as
Gold doping, forms forbidden band complex centre；In said structure of the present invention, drift layer surface grooves and internal groove locus include
To be projected as being alternately arranged in device surface, also include being to project coincidence or intussusception, drift layer noted herein in device surface
Internal groove can spatially set multiple, conductions of three or more settable separation in drift layer surface grooves up and down
Material；In said structure of the present invention, this area is contemplated that including being manufactured applied to planar device, and applied to planar device
Flow is more succinct.
Brief description of the drawings
Fig. 1 is the trench semiconductor device diagrammatic cross-section of the present invention.
Fig. 2 is more trench semiconductor device diagrammatic cross-sections of the present invention.
Fig. 3 is the multi-layer insulation trench semiconductor device diagrammatic cross-section of the present invention.
Fig. 4 is the more trench semiconductor device diagrammatic cross-sections of multi-layer insulation of the present invention.
Fig. 5 is that having for the present invention mixes oxygen polysilicon trench semiconductor device diagrammatic cross-section.
Fig. 6 is that having for the present invention mixes the more trench semiconductor device diagrammatic cross-sections of oxygen polysilicon.
Fig. 7 is the present invention with more trench semiconductor device diagrammatic cross-sections up and down.
One kind that Fig. 8 is the present invention has more trench semiconductor device diagrammatic cross-sections up and down.
One kind that Fig. 9 is the present invention has more trench semiconductor device diagrammatic cross-sections up and down.
Figure 10 is multiple conductor material semiconductor device diagrammatic cross-sections in the groove of the present invention.
Figure 11 is multiple conductor material semiconductor device diagrammatic cross-sections in a kind of groove of the present invention.
Figure 12 is multiple conductor material semiconductor device diagrammatic cross-sections in a kind of groove of the present invention.
Wherein, 1, substrate layer；2nd, drift layer；3rd, semiconductor junction；4th, metal；5th, DOPOS doped polycrystalline silicon；7th, silicon nitride；8th, dioxy
SiClx；9th, oxygen polysilicon is mixed.
Embodiment
Fig. 1 is the trench semiconductor device diagrammatic cross-section of the present invention, including：Substrate layer 1, it is high-concentration dopant N conductive
Type semiconductor silicon materials, drift layer 2, it is the semiconductor silicon material of N conduction types on substrate layer 1；Semiconductor junction 3,
Positioned at the surface of drift layer 2, including it is schottky junction or PN junction；Groove is located at the surface of drift layer 2, and depth and width are 7 microns and 2
Micron；Trench wall insulating barrier is silica 8, and upper thickness is 0.1 micron, and bottom is 0.3 micron；Oxygen is mixed in filling in groove
Polysilicon 5；Trenched side-wall manufacture method comprises the following steps, is filled out being provided with deposit in the groove of insulating barrier silica inwall
Nitrogen charging SiClx, etching remove trench interiors and divide silicon nitride, erosion removal trench sidewall insulating layer silica, remove nitrogen in groove
SiClx, thermal oxidation technology is carried out, grow insulating barrier silica in trenched side-wall, form the side wall insulating layer of two thickness, it is upper thin
Lower thickness, said process can be repeated again, form the side wall insulating layer of three thickness.Device upper and lower surface includes setting electrode gold
Category.For Fig. 2 on the basis of Fig. 1 embodiments of the present invention, to set groove inside drift layer 2, trench wall insulating barrier sets such as Fig. 1 ditches
Groove inner wall insulation layer, the internal groove of drift layer 2 filling metal, metal form Schottky semiconductor knot 3, groove with semi-conducting material
Depth is 5 microns, and drift layer internal groove and drift layer surface grooves include to be alternately arranged in device surface projection.
Fig. 3 is the multi-layer insulation trench semiconductor device diagrammatic cross-section of the present invention, including：Substrate layer 1, it is highly concentrated
Degree doping N conductive type semiconductor silicon materials, drift layer 2, it is the semiconductor silicon material of N conduction types on substrate layer 1
Material；Semiconductor junction 3, positioned at the surface of drift layer 2, including it is schottky junction or PN junction；Groove is located at the surface of drift layer 2, depth and
Width is 7 microns and 2 microns；Trench wall insulating barrier is silica 8 and silicon nitride 7, and silicon nitride layer is located under trench interiors
Portion, silica 8 and the thickness of silicon nitride 7 are 0.1 micron；Oxygen polysilicon 5 is mixed in filling in groove；Trenched side-wall manufacture method includes
Following steps, deposit silicon nitride 7 in the groove of the inwall of insulating barrier silica 8 is being provided with, DOPOS doped polycrystalline silicon 5 is being deposited, anti-carves
Etching off divides DOPOS doped polycrystalline silicon 5 except trench interiors, corroding silicon nitride 7, DOPOS doped polycrystalline silicon 5 is formed in groove.Device upper and lower surface
Including setting electrode metal.On the basis of Fig. 4 is Fig. 3 embodiments of the present invention, groove is set inside drift layer 2, and trench wall is exhausted
Edge layer sets such as Fig. 3 trench wall insulating barriers, the internal groove of drift layer 2 filling metal, metal to form Xiao Te with semi-conducting material
Based semiconductor 3, gash depth are 5 microns, and drift layer internal groove and drift layer surface grooves include in device surface projection
To be alternately arranged.
Fig. 5 is that having for the present invention mixes oxygen polysilicon trench semiconductor device diagrammatic cross-section, including：Substrate layer 1, for height
Doped in concentrations profiled N conductive type semiconductor silicon materials, drift layer 2, it is the semiconductor silicon material of N conduction types on substrate layer 1
Material；Semiconductor junction 3, positioned at the surface of drift layer 2, including it is schottky junction or PN junction；Groove is located at the surface of drift layer 2, depth and
Width is 7 microns and 2 microns；Trench wall insulating barrier is silica 8 and mixes oxygen polysilicon 9, mixes oxygen polysilicon 9 and is located at groove
Inner lower, thickness gradually increase from top to bottom, and the thickness of silica 8 is 0.1 micron；Oxygen polysilicon 5 is mixed in filling in groove；Ditch
Groove sidewall manufacture method comprises the following steps, deposits filling being provided with the groove of the inwall of insulating barrier silica 8 to mix oxygen more
Crystal silicon, the oxygen content that oxygen polysilicon is mixed in deposition process gradually rise, and carry out mixing the corrosion of oxygen polysilicon, because corrosion rate is different
With corrosion order under upper, it is gradually thickening from top to bottom that oxygen polysilicon layer is mixed in formation.Device upper and lower surface includes setting electrode
Metal.For Fig. 6 on the basis of Fig. 5 embodiments of the present invention, to set groove inside drift layer 2, trench wall insulating barrier sets such as Fig. 5
Trench wall insulating barrier, the internal groove of drift layer 2 filling metal, metal form Schottky semiconductor knot 3, ditch with semi-conducting material
Groove depth is 5 microns, and drift layer internal groove and drift layer surface grooves include to be alternately arranged in device surface projection.
Fig. 7 is the more trench semiconductor device diagrammatic cross-sections up and down that have of the present invention, including：Substrate layer 1, it is high concentration
N conductive type semiconductor silicon materials are adulterated, drift layer 2, are the semiconductor silicon material of N conduction types on substrate layer 1；
Semiconductor junction 3, positioned at the surface of drift layer 2, including it is schottky junction or PN junction；Groove is located at the surface of drift layer 2, depth and width
For 7 microns and 2 microns；Trench wall insulating barrier is silica 8, and the thickness of silica 8 is 0.1 micron；Filling is mixed in groove
Oxygen polysilicon 5；The inside of drift layer 2 sets groove, and inner wall insulation layer is silica 8, and the thickness of silica 8 is 0.1 micron, drift
It is 5 microns and 2 microns to move the internal groove depth and width of layer 2；Device upper and lower surface includes setting electrode metal, in drift layer 2
Portion's trench fill metal, metal form schottky junction with semi-conducting material and contacted, drift layer surface grooves and drift layer internal access
Groove projects overlapping in device surface.Fig. 8 is setting drift layer internal groove and drift layer table on the basis of Fig. 7 embodiments of the present invention
Face groove is projected as being alternately arranged in device surface.Fig. 9 is setting drift layer internal groove on the basis of Fig. 8 embodiments of the present invention
It is projected as being alternately arranged in device surface with drift layer surface grooves, while drift layer internal groove and drift layer surface ditch is set
Part is projected as in groove horizontal direction to be alternately arranged.
Figure 10 is multiple conductor material semiconductor device diagrammatic cross-sections in the groove of the present invention, including：Substrate layer 1, it is
High-concentration dopant N conductive type semiconductor silicon materials, drift layer 2, it is the semiconductor silicon of N conduction types on substrate layer 1
Material；Semiconductor junction 3, positioned at the surface of drift layer 2, including it is schottky junction or PN junction；Groove is located at the surface of drift layer 2, depth
It it is 14 microns and 2 microns with width；Groove is divided for upper and lower two parts by isolated insulation materials silicon dioxide 8；Upper groove side
It is 0.1 micron that wall, which sets insulating barrier silica 8, and conductive material DOPOS doped polycrystalline silicon 5, lower channel inwall are set in upper groove
It is 0.1 micron to set insulating barrier silica 8, and lower trench sidewalls abut against isolated insulation positions of materials and are not provided with insulating barrier, under
Metal is set in portion's groove, and it forms schottky barrier junction with semi-conducting material；Manufacture method comprises the following steps, in drift layer
Surface forms silicon nitride layer, removes partial nitridation silicon layer, and etching forms groove；Silica is formed in trench wall, deposits nitrogen
SiClx, etching groove inside points silicon nitride corrode silica, and etching removes silicon nitride in groove；Deposit metal, erosion grooves
Inside points metal；Silica is deposited in trench wall, DOPOS doped polycrystalline silicon is filled in groove, etches DOPOS doped polycrystalline silicon and dioxy
SiClx, corrosion device surface nitrogen SiClx；Semiconductor junction is formed in device surface.Figure 11 be Figure 10 embodiments of the present invention on the basis of,
It is 0.5 micron to set the thickness of isolated insulation material silicon nitride 7, and it is 0.5 micro- that lower channel inwall bottom, which sets thick silicon dioxide 8,
Rice.Figure 12 is on the basis of Figure 10 embodiments of the present invention, bottom sets what thickness gradually changed in upper groove and lower channel
Mix oxygen polysilicon 9.
As described above, the trench device of the present invention is compared with prior art, different-thickness groove is set in drift layer
Side wall insulating layer, suppress spike electric field, groove structure be set inside drift layer, multiple peak value electric fields are formed in drift layer,
Improve device reverse blocking voltage or forward conduction ability.
The present invention is elaborated by examples detailed above, while other examples can also be used to realize the present invention, not office of the invention
It is limited to above-mentioned instantiation, therefore the present invention is limited by scope.
Claims (10)
- A kind of 1. trench semiconductor device, it is characterised in that：Including：Substrate layer, it is semi-conducting material；Drift layer, it is the first conducting semiconductor material, on substrate layer；Multiple grooves, inside drift layer surface or drift layer, trench wall is provided with insulating barrier, and trench sidewall insulating layer is set Two or more thickness are put, are upper-thin-lower-thick, trench sidewall insulating layer bottom includes being formed by stacking for different insulative material, groove Inner wall insulation layer wraps up conductive material, and it is metal or doped polycrystalline semi-conducting material that conductive material, which includes, drift layer internal groove Interior conductive material upper surface contacts with drift layer semi-conducting material, and conductive material upper surface includes setting in drift layer internal groove There is schottky barrier junction；Semiconductor junction, it is schottky junction or PN junction positioned at drift layer surface.
- 2. semiconductor device as claimed in claim 1, it is characterised in that：Described trench sidewall insulating layer is included to be of the same race exhausted Edge material, the composition of described different insulative material trench side wall insulating layer include being silica, silicon nitride or aluminum oxide.
- 3. semiconductor device as claimed in claim 1, it is characterised in that：Described trench sidewall insulating layer manufacture method includes Following steps, deposit filling silicon nitride in the groove of insulating barrier silica inwall is being provided with, etching removes trench interiors and divides nitrogen SiClx, erosion removal trench sidewall insulating layer silica, silicon nitride in groove is removed, thermal oxidation technology is carried out, in trenched side-wall Insulating barrier silica is grown, forms the side wall insulating layer of two thickness, again repeatedly said process, forms the side wall of three thickness Insulating barrier.
- A kind of 4. trench semiconductor device, it is characterised in that：Including：Substrate layer, it is semi-conducting material；Drift layer, it is the first conducting semiconductor material, on substrate layer；Multiple grooves, inside drift layer surface or drift layer, trench wall is provided with insulating barrier, and bottom is provided with groove Oxygen polysilicon layer is mixed, oxygen polysilicon layer is mixed and abuts against trench wall surface of insulating layer, it is gradual from top to bottom that side wall mixes oxygen polysilicon layer Thickening, that mixes oxygen polysilicon mixes oxygen amount away from being gradually risen on trench wall insulating barrier direction, and conductive material is set in groove, It is metal or doped polycrystalline semi-conducting material that conductive material, which includes, conductive material upper surface and drift layer in drift layer internal groove Semi-conducting material contacts, and conductive material upper surface includes being provided with schottky barrier junction in drift layer internal groove；Semiconductor junction, it is schottky junction or PN junction positioned at drift layer surface.
- 5. semiconductor device as claimed in claim 4, it is characterised in that：It is different insulative that the trench wall insulating barrier, which includes, Material is formed by stacking, and it is silica, silicon nitride or aluminum oxide that insulating materials, which includes,.
- 6. semiconductor device as claimed in claim 4, it is characterised in that：What bottom was set in described groove mixes oxygen polysilicon The manufacture method of layer comprises the following steps, mixes oxygen polysilicon being provided with deposit filling in the groove of insulating barrier inwall, is depositing During mix the oxygen content of oxygen polysilicon and gradually rise, carry out mixing the corrosion of oxygen polysilicon, because corrosion rate is different and corrosion order Under upper, it is gradually thickening from top to bottom that oxygen polysilicon layer is mixed in formation.
- A kind of 7. trench semiconductor device, it is characterised in that：Including：Substrate layer, it is semi-conducting material；Drift layer, it is the first conducting semiconductor material, on substrate layer；Multiple grooves, inside drift layer surface and drift layer, trench wall sets insulating barrier, and conduction material is set in groove Expect, conductive material contacts with device surface electrode metal in drift layer surface grooves, in drift layer internal groove on conductive material Surface contacts with drift layer semi-conducting material, and it is metal or doped polycrystalline semi-conducting material that wherein conductive material, which includes, drift layer Internal groove surface includes being provided with schottky barrier junction；Semiconductor junction, it is schottky junction or PN junction positioned at drift layer surface.
- A kind of 8. trench semiconductor device, it is characterised in that：Including：Substrate layer, it is semi-conducting material；Drift layer, it is the first conducting semiconductor material, on substrate layer；Multiple grooves, positioned at drift layer surface, groove is divided into two parts up and down by isolated insulation material；Upper trench sidewall is set Insulating barrier is put, conductive material is set in upper groove, and is contacted with device surface electrode metal, lower channel inwall sets insulation Layer, lower trench sidewalls abut against isolated insulation positions of materials and are not provided with insulating barrier, conductive material are set in lower channel, wherein leading Electric material includes being metal or doped polycrystalline semi-conducting material, and lower trench sidewalls, which abut against isolated insulation material surface, to be included being Xiao Special base barrier junction；Semiconductor junction, it is schottky junction or PN junction positioned at drift layer surface.
- 9. semiconductor device as claimed in claim 8, it is characterised in that：Described upper groove or the side wall of lower channel are exhausted Edge layer, two or more thickness are set, are upper-thin-lower-thick.
- 10. semiconductor device as claimed in claim 8, it is characterised in that：Described upper groove or the side wall of lower channel Oxygen polysilicon layer is mixed in the lower surface of insulating barrier, setting, gradually thickening from top to bottom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610625419.5A CN107665921A (en) | 2016-07-29 | 2016-07-29 | A kind of trench semiconductor device |
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| US20040209422A1 (en) * | 2003-04-15 | 2004-10-21 | Nanya Technology Corporation | Semiconductor device having trench top isolation layer and method for forming the same |
| US20060033154A1 (en) * | 2004-04-20 | 2006-02-16 | Jianjun Cao | MOSgated power semiconductor device with source field electrode |
| US20060205222A1 (en) * | 2002-12-14 | 2006-09-14 | In T Zandt Michael A A | Manufacture of trench-gate semiconductor devices |
| CN1930689A (en) * | 2004-03-10 | 2007-03-14 | 皇家飞利浦电子股份有限公司 | Trench-gate transistors and their manufacture |
| TW201421676A (en) * | 2012-11-27 | 2014-06-01 | Ind Tech Res Inst | Schottky barrier diode and fabricating method thereof |
| US20150279946A1 (en) * | 2014-03-26 | 2015-10-01 | International Rectifier Corporation | Power Semiconductor Device with Embedded Field Electrodes |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060205222A1 (en) * | 2002-12-14 | 2006-09-14 | In T Zandt Michael A A | Manufacture of trench-gate semiconductor devices |
| US20040209422A1 (en) * | 2003-04-15 | 2004-10-21 | Nanya Technology Corporation | Semiconductor device having trench top isolation layer and method for forming the same |
| CN1930689A (en) * | 2004-03-10 | 2007-03-14 | 皇家飞利浦电子股份有限公司 | Trench-gate transistors and their manufacture |
| US20060033154A1 (en) * | 2004-04-20 | 2006-02-16 | Jianjun Cao | MOSgated power semiconductor device with source field electrode |
| TW201421676A (en) * | 2012-11-27 | 2014-06-01 | Ind Tech Res Inst | Schottky barrier diode and fabricating method thereof |
| US20150279946A1 (en) * | 2014-03-26 | 2015-10-01 | International Rectifier Corporation | Power Semiconductor Device with Embedded Field Electrodes |
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Application publication date: 20180206 |