CN107665179A - A kind of system including field programmable gate array - Google Patents
A kind of system including field programmable gate array Download PDFInfo
- Publication number
- CN107665179A CN107665179A CN201710876010.5A CN201710876010A CN107665179A CN 107665179 A CN107665179 A CN 107665179A CN 201710876010 A CN201710876010 A CN 201710876010A CN 107665179 A CN107665179 A CN 107665179A
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- interface
- component
- input
- main equipment
- slave unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the present invention provides a kind of system including field programmable gate array, and the system belongs to technology of CPLD field, and the system includes main equipment and several slave units, in addition to system bus, wherein：First component of the system bus connects the input of the main equipment and the input of each slave unit, first component is used to produce clock signal and reset signal, and first component is additionally operable to caused clock signal and reset signal being sent to the main equipment and the slave unit；One end of second component of the system bus connects the main equipment, and the other end of second component connects the slave unit, and second component is used for the interface for several slave units by the interface conversion of the main equipment.The interface modes of traditional multi-to-multi are improved to one-to-many interface modes by the present invention, significantly reduce the complexity of application, greatly reduce the development difficulty of user's application.
Description
Technical field
The present invention relates to technology of CPLD field, more particularly to a kind of including field programmable gate array
System.
Background technology
With field programmable gate array (FPGA：Field-Programmable Gate Array) scale increasingly
Greatly, chip internal function is become increasingly complex, and higher requirement is proposed to FPGA system architecture.In numerous FPGA system frameworks
In, based on the system architecture of point-to-point interconnection, compared with other FPGA system frameworks, with the simplicity of its technology and realize straight
The property seen, is widely used, becomes the FPGA system framework of industry main flow.
Fig. 1 is traditional FPGA system configuration diagram based on point-to-point interconnection, as shown in figure 1, being currently based on a little pair
The FPGA system framework of point interconnection, the interface of FPGA user logic functional block and other modules inside FPGA are directly connected to.But
It is more and more with FPGA function, FPGA internal functional blocks are more and more, FPGA user logic and FPGA functional blocks
Kind of interface and quantity it is also more and more, user logic side's main equipment needs to realize various host device interface functions, with realize
Communicated with the functional block of various interfaces, considerably increase the application complexity of on-site programmable gate array FPGA, constrain
FPGA application.
The content of the invention
The embodiment of the present invention provides a kind of system including field programmable gate array, and the application that can reduce FPGA is complicated
Degree.
Technical scheme is as follows used by the present invention solves above-mentioned technical problem：
A kind of system including field programmable gate array provided according to an aspect of the present invention, including main equipment and
Several slave units, in addition to system bus, wherein：
First component of the system bus connects the input of the main equipment and the input of each slave unit, and this first
Component is used to produce clock signal and reset signal, and first component is additionally operable to caused clock signal and reset signal transmission
To the main equipment and the slave unit；
One end of second component of the system bus connects the main equipment, and the connection of the other end of second component should be from setting
Standby, second component is used for the interface for several slave units by the interface conversion of the main equipment.
In one of which embodiment, the slave unit includes configuration control system, SPI, is internally integrated electricity
Road, timer and phaselocked loop, the configuration control system, the SPI, the internal integrated circuit, the timer and the lock
Phase ring is both connected on the system bus.
In one of which embodiment, the internal integrated circuit includes two, and two inside are formed circuit and are all connected with
On the system bus.
In one of which embodiment, the phaselocked loop includes two, and two phaselocked loops are both connected to the system bus
On.
In one of which embodiment, the system bus is wishbone on-chip system buses, the of the system bus
One component is the system control assembly of the wishbone on-chip systems bus, and the second component of the system bus is should
The intarconnected cotrol component of wishbone on-chip system buses.
In one of which embodiment, the intarconnected cotrol component include Cycles Interface, gating interface, write enabled interface,
Address bus interface, data bus interface and response interface, wherein：
The input of Cycles Interface connects the output end of the Cycles Interface of the main equipment, the interconnection in the intarconnected cotrol component
The output end of Cycles Interface connects the input of the Cycles Interface of the slave unit in control assembly；
The input of gating interface connects the output end of the gating interface of the main equipment, the interconnection in the intarconnected cotrol component
The output end of gating interface connects the input of the gating interface of the slave unit in control assembly；
The input that enabled interface is write in the intarconnected cotrol component connects the output end for writing enabled interface of the main equipment, should
The output end that enabled interface is write in intarconnected cotrol component connects the input for writing enabled interface of the slave unit；
The input of address bus interface connects the output of the address bus interface of the main equipment in the intarconnected cotrol component
Hold, the output end of address bus interface connects the input of the address bus interface of the slave unit in the intarconnected cotrol component；
One end of the data bus interface connects the main equipment, and the other end of the data bus interface connects the slave unit；
The input of response interface connects the output end of the response interface of the slave unit, the interconnection in the intarconnected cotrol component
The output end of response interface connects the input of the response interface of the main equipment in control assembly.
In one of which embodiment, the system control assembly includes clock interface and reseting interface, wherein：
The output end of the clock interface of the system control assembly connect simultaneously the clock interface of the main equipment input and
The input of the clock interface of the slave unit；
The output end of the reseting interface of the system control assembly connect simultaneously the reseting interface of the main equipment input and
The input of the reseting interface of the slave unit.
In one of which embodiment, the system control assembly is located in the electronic equipment where the main equipment, and this is mutual
Connection control assembly is located in the field programmable gate array.
In one of which embodiment, the reset signal is synchronous reset signal.
The present invention is by the basis of the existing FPGA system framework based on point-to-point interconnection, in main equipment and slave unit
Between a piece of upper system bus is set, pass through the connecing in main equipment and each slave unit of the equipment interface in the on-chip system bus
Mouthful between realize conversion so that the user equipment where main equipment in other words when user logic only need to realize on-chip system bus
Host device interface function, and without the number of slave unit and the tool of each slave unit in tube field programmable gate array FPGA
Body interface, the complexity of application is significantly reduced, greatly reduce the development difficulty of user's application.
Brief description of the drawings
Fig. 1 is traditional FPGA system configuration diagram based on point-to-point interconnection；
Fig. 2 is the FPGA system configuration diagram based on on-chip system bus according to one embodiment of the present of invention；
Fig. 3 is the FPGA system configuration diagram based on on-chip system bus according to another embodiment of the present invention；
Fig. 4 is the FPGA system configuration diagram based on on-chip system bus according to another embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
A kind of system including field programmable gate array provided according to one embodiment of present invention, including main equipment
With several slave units, in addition to system bus, wherein：
First component of the system bus connects the input of the main equipment and the input of each slave unit, this first group
Part is used to produce clock signal and reset signal, and first component is additionally operable to caused clock signal and reset signal being sent to
The main equipment and the slave unit；
One end of second component of the system bus connects the main equipment, and the other end connection of second component should be from setting
Standby, second component is used for the interface for several slave units by the interface conversion of the main equipment.
In one of which embodiment, the slave unit includes configuration control system, SPI, is internally integrated electricity
Road, timer and phaselocked loop, the configuration control system, the SPI, the internal integrated circuit, the timing
Device and the phaselocked loop are both connected on the system bus.
In one of which embodiment, the internal integrated circuit includes two, and two inside are formed circuit and are all connected with
On the system bus.
In one of which embodiment, the phaselocked loop also includes two, and it is total that two phaselocked loops are both connected to the system
On line.
In one of which embodiment, the system bus is wishbone on-chip system buses, the of the system bus
One component is the system control assembly of the wishbone on-chip systems bus, and the second component of the system bus is should
The intarconnected cotrol component of wishbone on-chip system buses, wherein：
The system control assembly SYSCON of on-chip system bus output end connects the input of the main equipment and each
The input of the slave unit, the system control assembly are used to produce clock signal and reset signal, and the system control assembly is also used
In caused clock signal and reset signal are sent into the main equipment and the slave unit；
The intarconnected cotrol component INTERCON of on-chip system bus one end connects the main equipment, the intarconnected cotrol component
The other end connect the slave unit, what the intarconnected cotrol component was used for the interface conversion of the main equipment for several slave units
Interface.
Fig. 2 is the FPGA system configuration diagram based on on-chip system bus according to one embodiment of the present of invention,
In one of embodiment, above-mentioned slave unit can be the functional block in Fig. 2, and above-mentioned main equipment can be contained in user
In logic, as shown in Fig. 2 the user logic is interconnected by on-chip system bus wishbone and n functional block, wherein：
System bus in the on-chip system bus master interface connection sheet of user logic；
System bus in the on-chip system bus slave interface connection sheet of n functional block；
The interface conversion function of on-chip system bus slave interface and functional block interface is realized in functional block.
The system including field programmable gate array that the present embodiment provides is in the existing FPGA systems based on point-to-point interconnection
Unite on the basis of framework, increase on-chip system bus between user logic and functional block.On-chip system bus slave interface
Realize that user logic only needs the master for realizing on-chip system bus to set in functional block with the interface conversion function of functional block interface
Standby interface function, the complexity of application is significantly reduced, greatly reduce the development difficulty of user's application.
Fig. 3 is according to the FPGA system configuration diagram based on on-chip system bus of another embodiment of the present invention, root
According to the FPGA system framework based on on-chip system bus of another embodiment of the present invention as shown in figure 3, the slave unit includes matching somebody with somebody
Put control system, serial peripheral interface, internal integrated circuit I2C, timer and phase-locked loop pll, the configuration control system,
The serial peripheral interface, internal integrated circuit I2C, it is total to be both connected to the on-chip system for the timer and the phase-locked loop pll
On line.
In one of which embodiment, above-mentioned two internal integrated circuits are respectively I2C0 and I2C1, two inside
Form circuit to be both connected in the on-chip system bus.
In one of which embodiment, above-mentioned two phaselocked loops are respectively PLL0 and PLL1, and two phaselocked loops are equal
It is connected in the on-chip system bus.
In one of which embodiment, the intarconnected cotrol component include Cycles Interface, gating interface, write enabled interface,
Address bus interface, data bus interface and response interface, wherein：
The input of Cycles Interface connects the output end cyc_o of the Cycles Interface of the main equipment in the intarconnected cotrol component,
The output end of Cycles Interface connects the input cyc_i of the Cycles Interface of the slave unit in the intarconnected cotrol component；
The input of gating interface connects the output end stb_o of the gating interface of the main equipment in the intarconnected cotrol component,
The output end of gating interface connects the input stb_i of the gating interface of the slave unit in the intarconnected cotrol component；
The input that enabled interface is write in the intarconnected cotrol component connects the output end we_ for writing enabled interface of the main equipment
O, the output end that enabled interface is write in the intarconnected cotrol component connect the input we_i for writing enabled interface of the slave unit；
The input of address bus interface connects the output of the address bus interface of the main equipment in the intarconnected cotrol component
Hold adr_o [7:0], the output end of address bus interface connects the address bus interface of the slave unit in the intarconnected cotrol component
Input adr_i [4:0]；
One end of the data bus interface connects the main equipment, and the other end of the data bus interface connects the slave unit,
Wherein, the data/address bus output end dat_o [7 of main equipment:0] data that the slave unit is connected by the on-chip system bus are total
The input dat_i [7 of line:0], the data/address bus input dat_i [7 of main equipment:0] institute is connected by the on-chip system bus
State the output end dat_o [7 of the data/address bus of slave unit:0]；
The input of response interface connects the output end ack_o of the response interface of the slave unit in the intarconnected cotrol component,
The output end of response interface connects the input ack_i of the response interface of the main equipment in the intarconnected cotrol component.
In one of which embodiment, the system control assembly includes clock interface and reseting interface, wherein：
The output end clk_o of the clock interface of the system control assembly connects the input of the clock interface of the main equipment simultaneously
Hold the input clk_i of clk_i and the clock interface of the slave unit；
The output end rst_o of the reseting interface of the system control assembly connects the input of the reseting interface of the main equipment simultaneously
Hold the input rst_i of rst_i and the reseting interface of the slave unit.
Fig. 4 is the FPGA system configuration diagram based on on-chip system bus according to another embodiment of the present invention, such as
Shown in Fig. 4, in this embodiment, (or perhaps user patrols the electronic equipment that the system control assembly is located at where the main equipment
Volume) in, the system control assembly and main equipment may be constructed the user logic, and the intarconnected cotrol component is located at the scene and can compiled
In journey gate array, the intarconnected cotrol component and several described functional blocks (or perhaps slave unit) may be constructed the scene can
Program gate array.The system architecture may be constructed by the user logic and the field programmable gate array.
In one of which embodiment, above-mentioned reset signal is synchronous reset signal.
System architecture as shown in Figure 4, above-mentioned slave unit include：One configuration control system functional block, one it is serial
Peripheral interface SPI functional blocks, two internal integrated circuit I2C functional blocks, a timer function block and two phase-locked loop pll work(
Can block.Wherein：
Wishbone on-chip system buses are divided into two components：System control assembly SYSCON and intarconnected cotrol component
INTERCON。
SYSCON functions are realized by user logic, produce clock signal and the reset of wishbone on-chip system EBIs
Signal.
Intarconnected cotrol component INTERCON functions are realized by FPGA hardware, and the wishbone on-chip systems of user logic is total
Line host device interface is converted to a configuration control system functional block, a SPI functional block, two I2C functional blocks, a timing
The wishbone on-chip system bus slave interfaces of device functional block and two PLL functional blocks.
User logic connects wishbone on-chip system buses by wishbone on-chip system bus masters interface.
It is on the wishbone on-chip system bus slaves interface connection wishbone pieces of configuration control system functional block
System bus.
The wishbone on-chip system bus slaves interface connection wishbone on-chip system buses of SPI functional blocks.
I2The wishbone on-chip system bus slaves interface connection wishbone on-chip system buses of C0 functional blocks.
I2The wishbone on-chip system bus slaves interface connection wishbone on-chip system buses of C1 functional blocks.
The wishbone on-chip system bus slaves interface connection wishbone on-chip system buses of timer function block.
The wishbone on-chip system bus slaves interface connection wishbone on-chip system buses of PLL0 functional blocks.
The wishbone on-chip system bus slaves interface connection wishbone on-chip system buses of PLL1 functional blocks.
The interface conversion function of wishbone on-chip system bus slave interfaces and configuration control system functional block interface
Realized in control system functional block is configured.
The interface conversion function of wishbone on-chip system bus slave interfaces and SPI functional block interfaces is in SPI functions
Realized in block.
Wishbone on-chip system bus slave interfaces and I2The interface conversion function of C0 functional block interfaces is in I2C0 functions
Realized in block.
Wishbone on-chip system bus slave interfaces and I2The interface conversion function of C1 functional block interfaces is in I2C1 functions
Realized in block.
The interface conversion function of wishbone on-chip system bus slave interfaces and timer function block interface is in timing
Realized in device functional block.
The interface conversion function of wishbone on-chip system bus slave interfaces and PLL0 functional block interfaces is in PLL0 work(
It can be realized in block.
The interface conversion function of wishbone on-chip system bus slave interfaces and PLL1 functional block interfaces is in PLL1 work(
It can be realized in block.
The system including field programmable gate array that the present embodiment provides by existing based on point-to-point interconnection
On the basis of FPGA system framework, system bus on a piece of is set between main equipment and slave unit, it is total by the on-chip system
Equipment interface on line realizes conversion between main equipment and the interface of each slave unit so that the user equipment where main equipment
User logic only needs to realize the host device interface function of on-chip system bus when in other words, and may be programmed gate array without tube field
The number of slave unit and the physical interface of each slave unit in FPGA are arranged, the interface modes of traditional multi-to-multi are improved to one
To more interface modes, the complexity of application is significantly reduced, greatly reduces the development difficulty that user applies.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (9)
1. a kind of system including field programmable gate array, including main equipment and several slave units, it is characterised in that also wrap
System bus is included, wherein：
First component of the system bus connects the input of the main equipment and the input of each slave unit, described
First component is used to produce clock signal and reset signal, and first component is additionally operable to caused clock signal and resets letter
Number it is sent to the main equipment and the slave unit；
One end of second component of the system bus connects the main equipment, the other end connection of second component it is described from
Equipment, second component are used for the interface for several slave units by the interface conversion of the main equipment.
2. system according to claim 1, it is characterised in that the slave unit includes configuration control system, Serial Peripheral
Interface, internal integrated circuit, timer and phaselocked loop, the configuration control system, the SPI, the internal collection
It is both connected into circuit, the timer and the phaselocked loop on the system bus.
3. system according to claim 2, it is characterised in that the internal integrated circuit is described two interior including two
Form circuit and be both connected on the system bus in portion.
4. system according to claim 2, it is characterised in that the phaselocked loop includes two, and described two phaselocked loops are equal
It is connected on the system bus.
5. system according to claim 1, it is characterised in that the system bus is wishbone on-chip system buses,
First component of the system bus is the system control assembly of the wishbone on-chip systems bus, the system bus
Second component is the intarconnected cotrol component of the wishbone on-chip systems bus.
6. system according to claim 5, it is characterised in that the intarconnected cotrol component includes Cycles Interface, gating connects
Mouth, enabled interface, address bus interface, data bus interface and response interface are write, wherein：
The input of Cycles Interface connects the output end of the Cycles Interface of the main equipment in the intarconnected cotrol component, described mutual
Join the input of the Cycles Interface of the output end connection slave unit of Cycles Interface in control assembly；
The input of gating interface connects the output end of the gating interface of the main equipment in the intarconnected cotrol component, described mutual
Join the input of the gating interface of the output end connection slave unit of gating interface in control assembly；
The input that enabled interface is write in the intarconnected cotrol component connects the output end for writing enabled interface of the main equipment, institute
State the input for writing enabled interface for the output end connection slave unit that enabled interface is write in intarconnected cotrol component；
The input of address bus interface connects the output of the address bus interface of the main equipment in the intarconnected cotrol component
Hold, the output end of address bus interface connects the input of the address bus interface of the slave unit in the intarconnected cotrol component
End；
One end of the data bus interface connects the main equipment, and the other end connection of the data bus interface is described from setting
It is standby；
The input of response interface connects the output end of the response interface of the slave unit in the intarconnected cotrol component, described mutual
Join the input of the response interface of the output end connection main equipment of response interface in control assembly.
7. system according to claim 5, it is characterised in that the system control assembly includes clock interface and resetted to connect
Mouthful, wherein：
The output end of the clock interface of the system control assembly connect simultaneously the clock interface of the main equipment input and
The input of the clock interface of the slave unit；
The output end of the reseting interface of the system control assembly connect simultaneously the reseting interface of the main equipment input and
The input of the reseting interface of the slave unit.
8. according to the system described in any one of claim 5 to 7, it is characterised in that the system control assembly is located at the master
In electronic equipment where equipment, the intarconnected cotrol component is located in the field programmable gate array.
9. according to the system described in any one of claim 5 to 7, it is characterised in that the reset signal is synchronous reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710876010.5A CN107665179B (en) | 2017-09-25 | 2017-09-25 | System comprising field programmable gate array |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710876010.5A CN107665179B (en) | 2017-09-25 | 2017-09-25 | System comprising field programmable gate array |
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| CN107665179B CN107665179B (en) | 2023-06-13 |
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| CN101196857A (en) * | 2008-01-04 | 2008-06-11 | 太原理工大学 | Double-port access symmetrical dynamic memory interface |
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| Publication number | Publication date |
|---|---|
| CN107665179B (en) | 2023-06-13 |
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