CN115758987B - Video input interface verification system and verification method - Google Patents
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Abstract
The application provides a video input interface verification system and a verification method, wherein the video input interface verification system comprises: the verification excitation generation module is used for superposing verification excitation in the first video data subjected to verification by the video input interface control module and inputting the second video data superposed with the verification excitation into the video input interface control module; the video input interface control module is used for receiving the second video data sent by the verification excitation generation module, then performing de-excitation processing on the second video data to generate third video data, and outputting the third video data to the verification module; and the verification module is used for receiving the third video data and acquiring a verification result of the video input interface control module. The verification excitation generating module is used for verifying the removal capability of the video input interface control module to the verification excitation through the verification excitation of the video data superposition, so that the scene coverage rate in the verification process of the video input interface is greatly improved.
Description
Technical Field
The application relates to the technical field of chip verification, in particular to a video input interface verification system and a verification method.
Background
At present, the verification system for the video input interface mainly stays at the stage of directly sending the data generated by the video source into the video input interface control module in the verification system, and does not carry out scene processing on the data generated by the video source, so that the scene coverage rate of the video input interface verification is lower, and the high scene coverage rate verification requirement of the video input interface at the present stage cannot be met.
Disclosure of Invention
The embodiment of the application aims to provide a video input interface verification system and a verification method, which are used for improving high scene coverage rate verification of a video input interface.
In a first aspect, an embodiment of the present application provides a video input interface verification system, including: the programmable device comprises a verification excitation generation module, a video input interface control module and a verification module, wherein the verification excitation generation module is used for superposing verification excitation in first video data verified by the video input interface control module and inputting second video data superposed with the verification excitation into the video input interface control module; the video input interface control module is used for receiving the second video data sent by the verification excitation generation module, then performing de-excitation processing on the second video data to generate third video data, and outputting the third video data to the verification module; and the verification module is used for receiving the third video data, processing and acquiring a verification result of the video input interface control module.
In the implementation process of the scheme, the processing capacity of the video input interface control module for verification excitation is verified through the verification excitation of the verification excitation generation module for superposition of video data, so that the video input interface verification system can construct excitation corresponding to various scenes, and the scene coverage rate in the video input interface verification process is greatly improved.
In an implementation manner of the first aspect, the video input interface verification system further includes: a storage module for storing the first video data and the third video data; the verification module comprises: and comparing and checking the first video data and the third video data by reading the first video data and the third video data in the storage module, and obtaining a verification result of the video input interface control module.
In the implementation process of the scheme, the verification module has the capability of directly completing the control module of the video input interface in a mode of reading the first video data and the third video data, has higher automation degree and can realize efficient verification of the video input interface.
In an implementation manner of the first aspect, the video input interface verification system further includes: the man-machine interaction module is used for displaying the first video data and the third video data; the verification module comprises: the method comprises the steps of inputting the first video data and the third video data into a human-computer interaction module, and obtaining a verification result returned by the human-computer interaction module to the video input interface control module.
In the implementation process of the scheme, the verification module supports a manual verification mode, so that the video input interface verification system can be suitable for more application scenes while the functions of the video input interface verification system are enriched.
In one implementation manner of the first aspect, the video input interface includes: a sulvds video input interface.
In the implementation process of the scheme, the video input interface can be a SUBLVDS video input interface, so that the coverage rate of verification scenes of the SUBLVDS video input interface is improved.
In an implementation manner of the first aspect, the video input interface control module includes: and the SUBLVDS controller equivalent unit is used for receiving the second video data, then performing de-excitation processing on the second video data to generate third video data, and outputting the third video data to the verification module.
In the implementation process of the scheme, the controller of the SUBLVDS video input interface is equivalent to obtain the SUBLVDS controller equivalent unit, the SUBLVDS controller equivalent unit is used for carrying out the deexcitation processing on the second video output by the verification excitation generation module, so that the verification of the SUBLVDS controller equivalent unit can be realized, the verification excitation generated by the verification excitation generation module can be edited through a programmable device, the SUBLVDS controller equivalent unit can process video data in a richer verification scene, and the verification coverage rate of the SUBLVDS controller equivalent unit is greatly improved.
In an implementation manner of the first aspect, the video input interface control module further includes: and the SUBLVDS PHY equivalent unit is built by a bottom logic unit of the programmable device and is used for acquiring fourth video data and clock signals, and outputting first video data obtained after serial data to parallel data processing of the fourth video data and clock signals to the verification excitation generation module.
In the implementation process of the scheme, the SUBLVDS PHY equivalent unit provides a function of converting serial data into parallel data, and can also provide a clock signal, so that the video input interface verification system can verify not only the deexcitation function of the SUBLVDS controller, but also the data acquisition function of the SUBLVDS controller according to the synchronous signal, and the function verification coverage rate of the SUBLVDS video input interface is improved.
In one implementation manner of the first aspect, the video input interface verification system further includes: and a video source for generating the fourth video data and the clock signal and inputting the fourth video data and the clock signal to the SUBLVDS PHY equivalent unit.
In the implementation process of the scheme, a video source can be adopted outside the video input interface verification system to provide video data and clock signals for the video input interface verification system, and the requirements of the function verification coverage rate and the scene verification coverage rate of the video input interface can be met without additionally arranging other hardware outside the video input interface verification system to process the video data.
In one implementation manner of the first aspect, the verification stimulus generating module includes: the video processing device comprises at least one of a bit inverting unit, a high-low bit inverting unit, a Lane sequence adjusting unit and a Skew Shew inserting unit, wherein the bit inverting unit is used for performing bit inverting processing on the first video data; the high-low bit negation unit is used for performing high-low bit negation processing on the first video data; the Lane sequence adjusting unit is used for carrying out Lane sequence adjusting processing on the first video data; the Skew Skew insertion unit is used for performing insertion Skew Skew processing on the first video data.
In the implementation process of the scheme, the verification excitation generation module can carry out superposition verification excitation on the first video data by adopting at least one of a bit-based inversion unit, a high-low bit inversion unit, a Lane sequence adjustment unit and a Skew Skew insertion unit, so that the scene verification coverage rate of a SUBLVDS video input interface is improved; meanwhile, as the verification excitation generating module is arranged in the programmable device, verification excitation generated by the verification excitation generating module can be edited directly through the programmable device, so that the video input interface verification system can be suitable for more application scenes.
In one implementation manner of the first aspect, the programmable device includes: a field programmable gate array FPGA.
In the implementation process of the scheme, the field programmable gate array FPGA is selected as a programmable device to realize verification of the video input interface, so that the verification cost is reduced; meanwhile, the user can also customize the verification stimulus generated by the verification stimulus generating module, so that the verification scene coverage rate of the video input interface verification system is further improved.
In a second aspect, an embodiment of the present application provides an input interface verification method, including: constructing a video input interface control module based on the programmable device; determining a verification stimulus required by the video input interface; constructing a verification stimulus generating module for generating verification stimulus required by the video input interface in the programmable device based on a hardware description language; based on the verification excitation generating module, inputting second video data overlapped with verification excitation to the video input interface control module, and then obtaining third video data processed by the video input interface control module; and based on the third video data, completing verification of the video input interface control module.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a video input interface verification system according to an embodiment of the present application;
fig. 2 is a schematic diagram of a video input interface verification system applied to a sulkds video input interface verification scene according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another exemplary video input interface verification system for use in a SUBLVDS video input interface verification scenario according to an embodiment of the application;
Fig. 4 is a flowchart of a video input interface verification method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a video input interface verification system in an application scenario for verifying an SOC chip with a sulflvds video input interface according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a sulvds PHY equivalent unit in an application scenario for verifying an SOC chip with a sulvds video input interface according to an embodiment of the present application;
fig. 7 is a schematic diagram of clock signals that can be configured by the sulvds PHY equivalent unit in an application scenario for verifying an SOC chip with a sulvds video input interface according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Relational terms such as "first" and "second", and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In order to solve the problem of low scene coverage of the video input interface verification system 100 in the prior art, an embodiment of the present application provides a video input interface verification system 100. Referring to fig. 1, a video input interface verification system 100 according to an embodiment of the present application includes:
a programmable device 110 comprising a verification stimulus generation module 120, a video input interface control module 130, and a verification module 140, wherein:
a verification stimulus generating module 120 for superimposing a verification stimulus in the first video data on which the verification is performed by the video input interface control module 130, and inputting the second video data on which the verification stimulus is superimposed to the video input interface control module 130;
the video input interface control module 130 is configured to receive the second video data sent by the verification stimulus generating module 120, then perform a de-stimulus process on the second video data, then generate third video data, and output the third video data to the verification module 140;
the verification module 140 is configured to receive the third video data and obtain a verification result of the video input interface control module 130.
The programmable device 110 refers to: the field programmable gate array Field Programmable Gate Array, i.e., FPGA, has logic functions that allow a user to determine by device programming. The verification stimulus generation module 120, the video input interface control module 130 and the verification module 140 are implemented by device programming.
Since the video input interface not only has a function of collecting data by a synchronization signal, but also supports a processing function of input data, such as a deskew process and Lane (channel) order adjustment process, it is necessary to verify the data processing function of the video input interface when verifying the video input interface. The verification stimulus generating module 120 acquires the second video data by superimposing the verification stimulus on the first video data, and the video input interface control module 130 generates the third video data after performing the deactivation processing on the second video data, which can be understood as the capability of the video input interface control module 130 to deactivate, that is, the data processing capability representing the video input interface. One of the purposes of the video input interface verification system 100 according to the embodiments of the present application is to verify the data processing capability of the video input interface, that is, the capability of the video input interface control module 130 to deactivate the video input interface.
In the implementation process of the scheme, the programmable device 110 is adopted to realize the equivalence of the video input interface, meanwhile, the verification excitation generating module 120 for generating verification excitation is additionally arranged through the programmable device 110, and the capability of the video input interface control module 130 for removing the verification excitation is verified through the verification excitation superimposed on the video data by the verification excitation generating module 120, so that the scene coverage rate in the verification process of the video input interface is greatly improved.
Meanwhile, since the verification stimulus generated by the verification stimulus generating module 120 can be realized by the user through device programming, the scene coverage rate in the verification process of the video input interface and the adaptability of the verification system 100 of the video input interface are further improved; in addition, no additional hardware is added in the process of verifying the video interface, so that the time cost and hardware cost for verifying the video input interface and the complexity for building a verification environment are greatly reduced.
As an alternative implementation manner of the video input interface verification system 100, the verification module 140 may directly read and verify the first video data and the third video data to implement verification of the video input interface control module 130, and the verification module 140 may also perform manual verification by a man-machine interaction manner. These two embodiments are described in detail below:
in the first embodiment, the verification module 140 performs verification of the video input interface control module 130 by directly reading and verifying the first video data and the third video data. This embodiment is, for example: in the video input interface verification system 100, a storage module is provided, in which the first video data and the third video data are stored, and the verification module 140 performs verification by reading the first video data and the third video data stored in the storage module.
It should be noted that, in the system described above, other video processing algorithms are not introduced except for superposition excitation and de-excitation, so in the implementation process of the first embodiment described above, the verification module 140 may directly complete the video input interface control module 130 by reading the first video data and the third video data, which has a higher degree of automation, and can implement efficient verification of the video input interface.
In a second embodiment, the verification module 140 performs the manual verification by means of man-machine interaction. This embodiment is, for example: a man-machine interaction module is provided in the video input interface verification system 100, and the man-machine interaction module is configured to visually display the first video data and the third video data, and obtain a verification result of the video input interface control module 130 input by a user.
In the implementation process of the second embodiment, the verification module 140 supports a manual verification manner, that is, the first video data and the third video data are directly input into the man-machine interaction module to be visually displayed, and the verification result of the video input interface control module input by the user is obtained through the man-machine interaction module, so that the function of the video input interface verification system is enriched, and the video input interface verification system can be suitable for more application scenes.
As an alternative embodiment of the video input interface verification system 100, the video input interface may be a sulvds video input interface, i.e., the video input interface verification system described above may be applied to a verification scenario for a sulvds video input interface.
LVDS (Low-Voltage Differential Signaling, low voltage differential signaling) is a differential signaling technology with Low power consumption, low bit error rate, low crosstalk, and Low radiation, and can implement point-to-point or point-to-multipoint connection. As a result of the development of sulflvds as an LVDS, employing a low swing current mode transmission system, the sulflvds technique can operate with much lower noise margin and much lower swing due to better power supply noise immunity than conventional modes when reaching nearly the same performance level as compared to conventional voltage modes. Therefore, the sulvds video input interface has gradually become the mainstream video input interface in the SOC (System on Chip) chip.
Referring to fig. 2, an embodiment of the present application provides a video input interface verification system applied to a sulvds video input interface verification scene. As an alternative embodiment of the video input interface verification system 100 described above, the video input interface control module 130 includes: the sulkds controller equivalent unit 131 is configured to receive the second video data, then perform a de-excitation process on the second video data to generate third video data, and output the third video data to the verification module, where this embodiment is as follows: the sulvds controller equivalent unit 131 is an equivalent unit equivalent to a controller according to the sulvds video input interface, i.e., a digital design part of the sulvds video input interface, in the programmable device 110. The controller portion of the SUBLVDS video input interface supports functions of bit-wise inversion, data-high-low inversion, de-skew deShew and Lane sequential adjustment. Therefore, the equivalent unit equivalent to the digital design part of the SUBLVDS video input interface also has the functions of bit-wise negation, data high-low negation, de-skew deShew and Lane sequential adjustment.
The verification stimulus generating module 120 inputs the second video data superimposed with the verification stimulus into the sulvds controller equivalent unit 131, and the sulvds controller equivalent unit 131 performs the deactivation processing on the second video data superimposed with the verification stimulus and outputs the third video data subjected to the deactivation processing, so that the verification on the sulvds controller equivalent unit 131 can be realized by verifying the removal condition of the verification stimulus of the third video data.
In the implementation process of the scheme, the controller of the SUBLVDS video input interface is equivalent to obtain the SUBLVDS controller equivalent unit, the SUBLVDS controller equivalent unit is used for carrying out the deexcitation processing on the second video output by the verification excitation generation module, so that the verification of the SUBLVDS controller equivalent unit can be realized, the verification excitation generated by the verification excitation generation module can be edited through a programmable device, the SUBLVDS controller equivalent unit can process video data in a richer verification scene, and the verification coverage rate of the SUBLVDS controller equivalent unit is greatly improved.
Referring to fig. 3, an embodiment of the present application provides another video input interface verification system applied to a sulkds video input interface verification scenario. As an alternative embodiment of the video input interface verification system 100, the video input interface control module 130 further includes: the sulvds PHY equivalent unit 132 is configured to acquire fourth video data and clock signals, and output first video data obtained by processing the fourth video data to the verification stimulus generation module 120. This embodiment is, for example: the sulvds PHY equivalent unit 132 is an equivalent unit equivalent in the programmable device 110 according to the PHY of the sulvds video input interface, i.e., the physical design part of the sulvds video input interface. The main functions of the physical design part PHY of the suplhds include: serial LVDS data is converted into parallel data. Therefore, the above-described suplhds PHY equivalent unit 132 also has a function of performing serial-to-parallel data processing on externally input fourth video data.
It should be noted that the controller portion of the above-mentioned sulkds also has a function of data acquisition according to the synchronization signal, and the main functions of the physical design portion PHY of the sulkds also include: a clock signal is provided for data acquisition by the controller portion of the sulvds. Therefore, the above-described sulkds controller equivalent unit 131 also has a function of performing data acquisition according to the synchronization signal, and the sulkds PHY equivalent unit 132 also has a function of providing a clock signal.
As an alternative embodiment of the video input interface verification system 100, the video input interface verification system 100 further includes: a video source for generating fourth video data and clock signals and inputting the fourth video data and clock signals to the sulvds PHY equivalent unit 132. The video source may be a camera module with a sulvds video output interface.
In the implementation process of the scheme, a video source can be adopted outside the video input interface verification system to provide video data and clock signals for the video input interface verification system, and the requirements of the function verification coverage rate and the scene verification coverage rate of the video input interface can be met without additionally arranging other hardware outside the video input interface verification system to process the video data.
As an alternative embodiment of the video input interface verification system 100 described above, the verification stimulus generation module 120 includes: at least one of a bit inverting unit, a high-low bit inverting unit, a Lane sequence adjusting unit and a Skew Shew inserting unit, wherein the bit inverting unit is used for performing bit inverting processing on the first video data; the high-low bit inverting unit is used for performing high-low bit inverting processing on the first video data; the Lane sequence adjusting unit is used for carrying out Lane sequence adjusting processing on the first video data; and a Skew Skew insertion unit for performing insertion Skew Skew processing on the first video data. This embodiment is, for example: to verify the functions of the SUBLVDS video input interface controller of bit-wise inversion, data high-low inversion, deSkew and Lane sequential adjustment, the verification stimulus generation module 120 sets at least one of a bit-wise inversion unit, a high-low inversion unit, lane sequential adjustment unit, and a Skew Skew insertion unit to superimpose the verification stimulus in the first video data, thereby verifying the functions of the SUBLVDS controller equivalent unit 131 of de-actuation.
The bit-wise inverting unit comprises: all bits of the inverted parallel data, e.g., 8 'b 10101100, are bit-wise inverted to become 8' b01010011. The bit-wise inverting unit is used for mainly simulating the scene that the P end and the N end of the SUBLVDS are inverted in hardware and verifying the bit-wise inverting function of the SUBLVDS video input interface controller.
The high-low position inverting unit specifically comprises: the high and low bits are inverted, for example, 8 'b 10101100, and the high and low bits are inverted to form' b00110101. The high-low bit reversing unit mainly simulates scenes with different definitions of high and low bits of two sides of a received video, and further verifies the processing capacity of the SUBLVDS video input interface controller for reversing the high and low bits.
The Lane sequence adjusting unit specifically comprises: the order of lane is adjusted, for example, the order of lane0, lane1, lane2, and lane3 is adjusted to the order of lane3, lane2, lane1, and lane 0. The Lane sequence adjusting unit mainly simulates a scene which is not corresponding to the sequence of external Lanes, and further verifies the Lane reordering function of the SUBLVDS video input interface controller.
The Skew Shew insertion unit specifically includes: all Lane were made to become non-aligned by Skew insertion. The Skew Shew insertion unit mainly simulates a scene where data Lane exists Shew. To verify that the sulkvs video input interface controller de-skew function. It should be noted that when the Skew Shew insertion unit is actually used, there is a limitation in the deShew capability of the SUBLVDS video input interface controller, so the Skew insertion of this function can be set according to the design specification spec of the controller.
In the implementation process of the scheme, the verification excitation generation module can carry out superposition verification excitation on the first video data by adopting at least one of a bit-based inversion unit, a high-low bit inversion unit, a Lane sequence adjustment unit and a Skew Skew insertion unit, so that the scene verification coverage rate of a SUBLVDS video input interface is improved; meanwhile, as the verification excitation generating module is arranged in the programmable device, verification excitation generated by the verification excitation generating module can be edited directly through the programmable device, so that the video input interface verification system can be suitable for more application scenes.
As an alternative embodiment of the video input interface verification system 100 described above, the programmable device 110 may be a field programmable gate array FPGA. This embodiment is, for example: the field programmable gate array FPGA (Field Programmable Gate Array) is a product developed based on programmable devices such as programmable array logic PAL and general array logic GAL, and is a semi-custom circuit, so that the embodiment of the application can select the programmable gate array FPGA as the programmable device 110.
In the implementation process of the scheme, the field programmable gate array FPGA is selected as a programmable device to realize verification of the video input interface, so that the verification cost is reduced; meanwhile, the user can also customize the verification stimulus generated by the verification stimulus generating module, so that the verification scene coverage rate of the video input interface verification system is further improved.
Referring to fig. 4, based on the same inventive concept, the embodiment of the present application further provides a video input interface verification method for the video input interface verification system, including:
step S110: constructing a video input interface control module based on the programmable device;
step S120: determining a verification stimulus required by the video input interface;
step S130: constructing a verification stimulus generating module for generating verification stimulus required by a video input interface in a programmable device based on a hardware description language;
step S140: based on the verification excitation generating module, inputting second video data overlapped with verification excitation to the video input interface control module, and then obtaining third video data processed by the video input interface control module;
step S150: based on the third video data, the verification of the video input interface control module is completed.
In one implementation manner of the video input interface verification method, the manner of constructing the video input interface control module based on the programmable device in step S110 specifically includes: building a SUBLVDS PHY equivalent unit based on a bottom logic unit of the programmable device; and constructing an equivalent unit of the SUBLVDS controller in the programmable device based on the hardware description language.
In one implementation manner of the video input interface verification method, the hardware description language in step S130 may be Verilog description language, or may be Vhdl description language, and the specific description language may be selected according to practical situations.
In one implementation manner of the video input interface verification method, step S140 includes: and comparing and checking the first video data and the third video data by reading the first video data and the third video data in the storage module to obtain a verification result of the video input interface control module.
In one implementation manner of the video input interface verification method, step S140 includes: inputting the first video data and the third video data into a man-machine interaction module, and obtaining a verification result of the video input interface control module returned by the man-machine interaction module.
In one implementation of the video input interface verification method, the video input interface may be a sulvds video input interface.
In one implementation manner of the video input interface verification method, the video input interface control module in step S110 includes: and the SUBLVDS controller equivalent unit is used for receiving the second video data, then performing de-excitation processing on the second video data to generate third video data, and outputting the third video data to the verification module.
In one implementation manner of the video input interface verification method, the video input interface control module in step S110 further includes: and the SUBLVDS PHY equivalent unit is built by a bottom logic unit of the programmable device and is used for acquiring fourth video data and clock signals, and outputting first video data obtained after serial data to parallel data processing of the fourth video data and clock signals to the verification excitation generation module.
In one implementation of the video input interface verification method, the fourth video data and the clock signal may be acquired by a video source. It should be noted that the clock signal output by the video source may also be directly input to the sulvds controller equivalent unit.
In one implementation manner of the video input interface verification method, the verification stimulus required by the video input interface determined in step S120 includes: bit-wise negation, high-low negation, lane order adjustment, and Skew Skew insertion.
In one implementation of the video input interface verification method described above, the programmable device may employ a field programmable gate array FPGA.
Referring to fig. 5, an embodiment of the present application provides an application scenario for verifying an SOC chip with a sultvds video input interface using the video input interface verification system described above. The video input interface verification system includes:
The programmable device 110 adopts Virtex Ultrascale series FPGA devices of XILINX as the programmable device to realize prototype verification of the sulvds video input interface;
the verification stimulus generating module 120 is implemented by a hardware description language, and is used for implementing the process of superposing verification stimulus on video data;
the video input interface control module 130 comprises a SUBLVDS controller equivalent unit 131 and a SUBLVDS PHY equivalent unit 132, wherein the SUBLVDS PHY equivalent unit 132 is an equivalent unit for physically designing PHY for a SUBLVDS video input interface, which is built through a bottom logic unit of a programmable device, and the SUBLVDS PHY equivalent unit 132 can be directly in butt joint with external hardware supporting SUBLVDS because the programmable device can support the voltage standard of SUBLVDS; the sulkds controller equivalent unit 131 is an equivalent unit to the sulkds video input interface controller that is directly transplanted from the SOC design into the programmable device 110;
a verification module 140 for verifying the video input interface control module 130;
a video source 150 for generating SUBLVDS video data, transmitting serial data and a serial clock to the programmable device 110 through a SUBLVDS output interface;
The SOC other module 160 specifically includes: and when the SOC chip with the SUBLVDS video input interface is verified, other parts of the SOC except the SUBLVDS video input interface are used for realizing the completed SOC chip functions.
The following describes a video input interface verification system in an application scenario in which a video source 150 generates a clock Lane and four data lanes, each Lane having a parallel data bit width of 8 bits, for example, is used to verify an SOC chip with a sulvds video input interface.
Referring to fig. 6, the suplhds PHY equivalent unit 132 may implement the equivalent using logic units inherent in the FPGA. The function of converting serial data into parallel data in the sultvds PHY equivalent unit 132 may be implemented by an ISERDESE3 module in the FPGA, and the clock signal portion may be implemented by a phase-locked loop PLL or a mixed mode clock module MMCM in the FPGA, where both modules support functions such as clock frequency division, frequency multiplication, and phase adjustment, and support differential clock input. As ISERDESE3, PLL and MMCM have more internal resources in the FPGA, the simultaneous verification of multiple SUBLVDS input video interfaces can be realized.
ISERDESE3 is a logic unit which is specially used for realizing conversion from serial data to parallel data in XILINX FPGA, and has the following characteristics: supporting the bit width of the parameterized configuration parallel data; supporting SDR mode and DDR mode; fifo caches are supported. In the above application scenario for verifying the SOC chip with the sulkds video input interface, the ISERDESE3 adopts the DDR mode, and determines the parallel data bit width parameter of the ISERDESE3 according to the input data bit width of the sulkds controller equivalent unit 131, without using fifo buffer.
The clock signal portion is mainly provided by a PLL or MMCM module whose main function is to receive a clock signal input from the external video source 150. Since the input clock signal is a differential signal, the input clock of the PLL or MMCM is configured in a differential input mode (both the PLL or MMCM supports a single-ended mode and a differential mode), so that the differential input clock can be directly connected without other processing. Referring to fig. 7, after the input clock passes through the PLL or MMCM, the input clock is output as three clocks for other external modules, where the three clocks are respectively:
output clock 1: the same-frequency and same-phase clock is an input clock;
output clock 2: the same-frequency reverse phase clock is an input clock;
output clock 3: is the divide-by-4 clock of the input clock.
These three clocks are simultaneously sent to all ISERDESE3 modules, which are required by the ISERDESE3 modules to accurately convert the serial data signals to parallel data signals. Except for serial to parallel data to the ISERDESE3 module. The output clock 3, i.e. the parallel data clock, is also sent to the verification stimulus generation module 120 and to the sulkds controller equivalent unit 131.
In the application scenario of using the video input interface verification system to verify the SOC chip with the sulfvs video input interface, other designs are also provided to assist in implementing the verification of the sulfvs video input interface. These auxiliary designs are described below:
In addition to the above designs, the overall design requires a portion of additional control signals, including:
control signals of an external video source, including configuration interface signals and reset signals;
the internal verification stimulus generates a functional switch signal for the module.
The two signals can be implemented by using an I2C (Inter-Integrated Circuit) interface and a GPIO (General-purpose input/output) interface of the SOC chip, specifically:
utilizing an I2C interface to configure an external video source to generate different video formats, clock signals, SUBLVDS lane numbers and the like;
the reset of the external video source is controlled by using the GPIO interface;
and controlling each functional switch in the verification excitation generation module by using the GPIO interface to determine whether to insert a skew, whether to take the bit-by-bit inversion parallel data, whether to take the high-low bit inversion of the parallel data, whether to change the sequence of the lane, and the like.
In addition to the above design, there is a need to add clock constraints and physical constraints, where the clock constraints are constraints set for the clock signal, and since the above video input interface verification system involves only one subevds differential clock input, there is a need to add the following clock constraints:
(1) Creating a master clock
And performing clock creation constraint on the P end of the differential clock through the create_clock command, and setting a clock period and a duty ratio.
clk_p is the P terminal of the SUBLVDS differential input clock. The constraint clock period may be adjusted according to the clock frequency of the LVDS.
(2) Setting clock packets
The created clocks are set in groups through a set_clock_groups command, so that the tool can conveniently conduct correct time sequence analysis.
The following physical constraints (4 lane suplhds for example) also need to be added:
(1) Enabling a physical 100 ohm differential resistor inside the SUBLVDS interface;
(2) Constraining the pin voltage to sub_lvds voltage standard, XILINX FPGA sub_lvds supporting 0.9V common mode voltage;
(3) Interface pin position binding constraints are set.
The embodiment of the application also provides a video input interface verification method for the application scene, which comprises the following steps:
s1: generating the ISERDESE3 and the PLL (or MMCM) logic unit in the FPGA according to parameters of a SUBLVDS input video interface in the SOC chip;
s2: according to the number of data Lane and the data bit width of a single interface in the SUBLVDS video input interface to be verified, an ISERDESE3 and a PLL (or MMCM) are used for constructing a SUBLVDS PHY equivalent unit;
s3: according to the number of SUBLVDS video input interfaces to be verified, constructing a corresponding number of SUBLVDS PHY equivalent units;
S4: after verification excitation required by the SUBLVDS video input interface is determined, completing verification excitation generation module writing by using verilog or vhdl hardware description language;
s5: the SUBLVDS PHY equivalent unit, the verification excitation generation module and the SUBLVDS controller equivalent unit are integrated together to form a complete SUBLVDS interface module capable of working on the FPGA;
s6: integrating the SUBLVDS interface module in the S5 into the whole SOC design, namely finishing the FPGA prototype verification version code of the SOC design;
s7: taking the FPGA prototype verification code with the SOC design completed in S6 and the design constraint file as input files, and integrating through an FPGA integration tool, wherein the FPGA integration tool can adopt a synthosis tool;
s8: engineering synthesis, because the design is realized based on XILINX FPGA, VIVADO can be selected as a synthesis tool, and a Protocopler prototype verification tool of SYNOPSYS can be selected for logic synthesis; after the integration is completed, whether the integrated result meets the expectations or not and whether the constraint is effective or not is checked. Of course, the relevant debug setting can be added in the comprehensive process, so that the subsequent debugging is convenient;
s9: performing engineering layout wiring (space & route);
s10: generating a bitfile to finish the internal design and engineering flow of the FPGA;
S11: connecting a required video source with the FPGA well, and confirming that various connection of the FPGA is complete;
s12: powering on and starting the FPGA to ensure that the running states of the FPGA and the video source are normal;
s13: downloading the bitfile generated in the step S10 to an FPGA;
s14: starting to verify, configuring an external video source, generating a video image, and sending the video image to an FPGA internal SUBLVDS interface module;
receiving a video image by configuring a SUBLVDS module, and confirming whether the image is received correctly;
the confirmation of the image effect is realized by the design of the SOC itself, for example, the image is read out from a memory to be checked, and the human-computer interaction module can also be used for manual check;
s15: and testing whether the corresponding function of the SUBLVDS input video interface controller works normally or not by controlling the functions inside the verification excitation generation module through the switch. Thereby achieving the purpose of verifying whether each function supported by the SUBLVDS input video interface controller meets the expectations.
It should be noted that the video input interface verification method is implemented based on the FPGA of XILINX and the tools, if the FPGA and tools of other manufacturers are used, equivalent replacement can be performed by the corresponding module in the FPGA device of the target manufacturer, and the constraint file also needs to be rewritten by using the grammar rules supported by the tools of the target manufacturer. Other designs implemented using verilog/vhdl hardware description language may be directly transplanted without modification.
In the embodiments provided herein, it should be understood that the disclosed systems and methods may be implemented in other ways. The system embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions in actual implementation, and e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, system or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (7)
1. A video input interface verification system, comprising:
the programmable device comprises a verification stimulus generation module, a video input interface control module and a verification module, wherein,
the verification excitation generation module is used for superposing verification excitation in the first video data subjected to verification by the video input interface control module and inputting the second video data superposed with the verification excitation into the video input interface control module;
the video input interface control module is used for receiving the second video data sent by the verification excitation generation module, then performing de-excitation processing on the second video data to generate third video data, and outputting the third video data to the verification module;
the verification module is used for receiving the third video data, processing and obtaining a verification result of the video input interface control module;
The verification module comprises:
comparing and checking the first video data and the third video data to obtain a verification result of the video input interface control module;
the video input interface comprises: a SUBLVDS video input interface;
the video input interface control module comprises:
the SUBLVDS controller equivalent unit is used for receiving the second video data, then performing de-excitation processing on the second video data to generate third video data, and outputting the third video data to the verification module;
the SUBLVDS PHY equivalent unit is built by a bottom logic unit of the programmable device and is used for acquiring fourth video data and clock signals, and outputting first video data obtained after serial data to parallel data processing of the fourth video data and clock signals to the verification excitation generation module;
the SUBLVDS controller equivalent unit is an equivalent unit equivalent in the programmable device according to the digital design part of the SUBLVDS video input interface; the SUBLVDS PHY equivalent unit is an equivalent unit in the programmable device that is equivalent according to the physical design portion of the SUBLVDS video input interface.
2. The video input interface verification system of claim 1, wherein the video input interface verification system further comprises:
a storage module for storing the first video data and the third video data;
the verification module comprises:
and comparing and checking the first video data and the third video data by reading the first video data and the third video data in the storage module, and obtaining a verification result of the video input interface control module.
3. The video input interface verification system of claim 1, wherein the video input interface verification system further comprises:
the man-machine interaction module is used for displaying the first video data and the third video data;
the verification module comprises:
the method comprises the steps of inputting the first video data and the third video data into a human-computer interaction module, and obtaining a verification result returned by the human-computer interaction module to the video input interface control module.
4. The video input interface verification system of claim 1, wherein the video input interface verification system further comprises:
And a video source for generating the fourth video data and the clock signal and inputting the fourth video data and the clock signal to the SUBLVDS PHY equivalent unit.
5. The video input interface verification system of claim 4, wherein the verification stimulus generation module comprises:
at least one of a bit-wise inverting unit, a high-low inverting unit, a Lane order adjustment unit, and a Skew Skew insertion unit, wherein,
the bit-wise inverting unit is used for performing bit-wise inverting processing on the first video data;
the high-low bit negation unit is used for performing high-low bit negation processing on the first video data;
the Lane sequence adjusting unit is used for carrying out Lane sequence adjusting processing on the first video data;
the Skew Skew insertion unit is used for performing insertion Skew Skew processing on the first video data.
6. The video input interface verification system of claim 4, wherein the programmable device comprises:
a field programmable gate array FPGA.
7. A method for verifying a video input interface, comprising:
constructing a video input interface control module based on the programmable device;
Determining a verification stimulus required by the video input interface;
constructing a verification stimulus generating module for generating verification stimulus required by the video input interface in the programmable device based on a hardware description language;
based on the verification excitation generating module, inputting second video data overlapped with verification excitation to the video input interface control module, and then obtaining third video data processed by the video input interface control module;
based on the third video data, completing verification of a video input interface control module, including: comparing and checking the first video data and the third video data to obtain a verification result of the video input interface control module;
the video input interface comprises: a SUBLVDS video input interface;
the video input interface control module comprises:
the SUBLVDS controller equivalent unit is used for receiving the second video data, then performing de-excitation processing on the second video data to generate third video data, and outputting the third video data to the verification module;
the SUBLVDS PHY equivalent unit is built by a bottom logic unit of the programmable device and is used for acquiring fourth video data and clock signals, and outputting first video data obtained after serial data to parallel data processing of the fourth video data and clock signals to the verification excitation generation module;
The SUBLVDS controller equivalent unit is an equivalent unit equivalent in the programmable device according to the digital design part of the SUBLVDS video input interface; the SUBLVDS PHY equivalent unit is an equivalent unit in the programmable device that is equivalent according to the physical design portion of the SUBLVDS video input interface.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184132A (en) * | 2011-04-28 | 2011-09-14 | 谭洪舟 | Method and system for testing video processing chip |
| CN102348125A (en) * | 2010-07-30 | 2012-02-08 | 上海炬力集成电路设计有限公司 | Video data reception system verification method and apparatus thereof |
| CN109992804A (en) * | 2017-12-29 | 2019-07-09 | 北京中科寒武纪科技有限公司 | Motivate generating means, chip checking apparatus and system |
| CN113115112A (en) * | 2021-06-16 | 2021-07-13 | 上海齐感电子信息科技有限公司 | Verification platform and verification method |
| CN113220518A (en) * | 2021-05-19 | 2021-08-06 | 北京奕斯伟计算技术有限公司 | Chip verification system and chip verification method |
| CN113312879A (en) * | 2021-07-28 | 2021-08-27 | 北京燧原智能科技有限公司 | Chip circuit function verification system, method, device and storage medium |
| CN113766216A (en) * | 2021-09-08 | 2021-12-07 | 北京爱芯科技有限公司 | Verification method and verification system for video module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7558718B2 (en) * | 2004-09-28 | 2009-07-07 | Broadcom Corporation | Method and system for design verification of video processing systems with unbalanced data flow |
-
2022
- 2022-11-24 CN CN202211483513.3A patent/CN115758987B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102348125A (en) * | 2010-07-30 | 2012-02-08 | 上海炬力集成电路设计有限公司 | Video data reception system verification method and apparatus thereof |
| CN102184132A (en) * | 2011-04-28 | 2011-09-14 | 谭洪舟 | Method and system for testing video processing chip |
| CN109992804A (en) * | 2017-12-29 | 2019-07-09 | 北京中科寒武纪科技有限公司 | Motivate generating means, chip checking apparatus and system |
| CN113220518A (en) * | 2021-05-19 | 2021-08-06 | 北京奕斯伟计算技术有限公司 | Chip verification system and chip verification method |
| CN113115112A (en) * | 2021-06-16 | 2021-07-13 | 上海齐感电子信息科技有限公司 | Verification platform and verification method |
| CN113312879A (en) * | 2021-07-28 | 2021-08-27 | 北京燧原智能科技有限公司 | Chip circuit function verification system, method, device and storage medium |
| CN113766216A (en) * | 2021-09-08 | 2021-12-07 | 北京爱芯科技有限公司 | Verification method and verification system for video module |
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