CN107658300A - A kind of flash memory fabrication method - Google Patents
A kind of flash memory fabrication method Download PDFInfo
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- CN107658300A CN107658300A CN201710882950.5A CN201710882950A CN107658300A CN 107658300 A CN107658300 A CN 107658300A CN 201710882950 A CN201710882950 A CN 201710882950A CN 107658300 A CN107658300 A CN 107658300A
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- flash memory
- fabrication method
- active area
- memory fabrication
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention discloses a kind of flash memory fabrication method, including step：Front-end architecture is provided, the front-end architecture is formed with active area and isolation structure；And the front-end architecture is annealed, annealing temperature is 1050~1200 degrees Celsius, and annealing time is 10 50 minutes.The present invention to the front-end architecture formed with active area and isolation structure by making annealing treatment, release stress caused by the lattice deformity deformation of active area caused by during isolation structure the is formed etching of groove or filling, reduce the staggered floor of lattice simultaneously, the lattice defect of active area is repaired, reduce the electric property and product yield for because leakage current caused by active area lattice defect, improving flash memory.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, to a kind of flash memory fabrication method.
Background technology
Flash element (Flash Memory, abbreviation Flash), is a kind of non-volatile memory component, belongs to internal memory
One kind of part, it can be as caching or as the underlying device directly stored.Due to can repeatedly carry out the deposit of data, read
And erasing, and the data being stored in will not also disappear after a loss of power, it is widely used by personal computer and other electronic equipments institute.
According to the difference of logical construction, flash element can be divided mainly into two kinds of NAND and NOR-type, and the former can provide bigger
Capacity, but support code does not locally execute, and reading rate is also compared with slow (but writing speed is very fast)；And NOR-type flash memory support code sheet
Ground is run, and reading rate is also slightly fast (writing speed is slightly slow), but major defect is higher storage density difficult to realize.Different
Characteristic allows both to be belonging respectively to different market：NAND-type flash memory is widely used in the related field of data storage, such as mobile storage
Product, various types of flash cards, music player etc.；And to be mainly used in the needs such as mobile phone, palm PC direct for NOR-type flash memory
The occasion of operation code.
Either NAND-type flash memory or NOR-type flash memory, both on basic data storage method and mechanism all
It is identical.Memory cell of the flash element using single-transistor as binary signal, its structure and common semiconductor die
Body pipe (FET) is very similar, difference be flash element transistor add " floating boom (Floating gate) " and
" control gate (Control gate) "-the former be used for store electronics, surface is coated by one layer of silicon oxycarbide insulator, and leads to
Electric capacity is crossed to be coupled with control gate.When negatron is being injected into floating boom in the presence of control gate, NAND single-transistor
Storage state just become 0 by 1.Comparatively, after negatron is removed from floating boom, storage state just becomes 1 by 0；And wrap
The effect for overlaying on the insulator on floating boom surface is exactly by the electronics " bottling up " of inside, reaches the purpose for preserving data.
Although general principle is identical, flash memory can have different electric charge generations and storage scheme.It is wherein most widely used
Be " channel hot electron program (Channel Hot Electron, abbreviation CHE) ", this method, which passes through, applies high electricity to control gate
Pressure, makes conduction electronics break through the barrier of insulator in the presence of electric field and enters inside floating boom, and vice versa, is completed with this
Write-in or erasing move；And another method is referred to as " tunnelling (Fowler-Nordheim, abbreviation FN) ", it is
Directly apply high voltage in insulating barrier both sides and form high field, help electronics to pass through oxide layer passage disengaging floating boom.NAND
Flash memory is write and wiped using FN methods, and using the unified storage mode of a kind of " page-block " addressing.And NOR flash memory makes simultaneously
With above-mentioned two methods：CHE writes for data, supports single byte or individual character programming；FN rules are used to wipe, in units of block
Or erasing operation is performed to entire area.
With semiconductor devices integrated level continue to increase and the lasting reduction of the critical dimension related to these devices,
Test checking to the fine structure of semiconductor devices proposes higher requirement.The crucial chi of flash element memory cell at present
Very little more below 130 nanometers, the requirement of this dispatch from the factory functional test and reliability testing to flash memory is just higher.With flash memory member
The reduction of part memory cell critical size, the electron number that the floating boom in flash element memory cell can capture is reduced, if flash memory
The leakage current of element memory cell is larger, then the electron number that floating boom can capture in theory may incite somebody to action with regard to less when serious
The high level (electron number is more) of write-in becomes low level (electron number is few), so as to influence being programmed into for memory cell, causes to compile
Journey write-in functions malfunction.It is current urgent need to resolve so how to reduce the leakage current of the less and less flash element of critical size
The problem of.
The content of the invention
It is an object of the invention to provide a kind of manufacture method of flash memory, to reduce the leakage current of memory cell in flash memory,
Improve the performance and yield of flash memory.
In order to achieve the above object, the invention provides a kind of manufacture method of flash memory, it is characterised in that including：
Front-end architecture is provided, the front-end architecture is formed with active area and isolation structure；And
The front-end architecture is annealed, annealing temperature is 1050~1200 degrees Celsius, and annealing time is 10-50 points
Clock.
Optionally, the annealing temperature is 1080~1120 degrees Celsius, and annealing time is 25-35 minutes.
Optionally, the annealing is carried out in a nitrogen environment.
Optionally, the offer front-end architecture, the front-end architecture include formed with active area and the step of isolation structure：
Semi-conductive substrate is provided, formed with multiple active areas in the Semiconductor substrate；
Etching forms groove and opens the multiple active area isolation on the semiconductor substrate；And
To the trench fill isolation oxide to form the isolation structure.
Optionally, multiple active areas in the Semiconductor substrate are formed using self-registered technology.
Optionally, etching is formed before the groove, deposits sacrifice layer on the semiconductor substrate.
Optionally, the sacrifice layer includes oxide layer and the nitration case stacked gradually from bottom to up.
Optionally, the groove is formed by reactive ion etching.
Optionally, to before the trench fill isolation oxide, first one layer is deposited in the bottom of the groove and side wall
Interior lining oxide layer.
Optionally, the filling of the isolation oxide uses high-density plasma chemical vapor deposition method.
Compared with prior art, flash memory fabrication method of the invention is to the front-end architecture formed with active area and isolation structure
Annealed, by annealing, can effectively be discharged in the forming process of isolation structure caused by the etching of groove or filling
Active area structure lattice deformity deformation caused by stress；Annealing temperature is 1050~1200 degrees Celsius simultaneously, annealing time
For 10-50 minutes, temperature is very high and annealing time is grown, it is easy to accomplish the motion of lattice dislocation, by the sliding of edge dislocation, climbs
Commutative Banach aglebra with helical dislocation etc. is moved, realizes that substantial amounts of dislocation offsets, the staggered floor phenomenon of lattice is reduced, so as to active area
Lopsided lattice is replied, and then can be reduced in the active area of flash memory because leakage current caused by lattice defect, is improved
The yield and electric property of flash memory.
Brief description of the drawings
Fig. 1 is the flash memory fabrication method and step schematic diagram of the present invention；
Fig. 2 is the flash memory structure schematic diagram of the present invention；
Fig. 3 is the leakage current distribution schematic diagram that flash memory is made using the flash memory fabrication method of the present invention；
Fig. 4 is the leakage current distribution schematic diagram that flash memory is made using common flash memory fabrication method；
In figure, 1- Semiconductor substrates, 11- active areas, 11a- source electrodes, 11b- drain electrodes, 12- grooves, 2- tunnel oxides, 3-
Floating boom, 4- control gates.
Embodiment
The embodiment of the present invention is described in more detail below in conjunction with schematic diagram.According to description below and
Claims, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and
Using non-accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Inventor, which studies, to be found：As shown in Fig. 2 it is the flash memory structure in one embodiment of the invention, using existing shallow
When trench isolation process etching groove 12 is to isolate multiple active areas 11, the highdensity incident ion of high-energy, more or less
Active area 11 can be entered.The incident ion of high-energy can send out some lattice atoms with the atomic collision on the lattice of active area 11
Raw displacement so that the atomic arrangement in active area 11 is chaotic or is changed into amorphous area, destroys the lattice structure of active area 11, causes
Part distortion of lattice, internal stress is larger and skewness, lattice dislocation phenomenon also compare more, the shifting of part electronics in active area 11
It is dynamic to be obstructed, so as to cause no small static leakage current, and then influence the performance of flash element.Especially for 130 nanometers with
For the flash element of lower size, the leakage current in element not only influences the read or write speed of data, it is also possible to causing when serious
Read-write error.
Based on this, the present invention proposes a kind of flash memory fabrication method, i.e., before the flash memory after isolation structure is formed to etching filling
End structure carries out the high temperature anneal to repair the lattice defect of the active area 11 as caused by plasma etching groove 12, from
And the leakage current of flash memory is reduced, improve product yield.Wherein, the front-end architecture of flash memory includes multiple active areas 11, groove 12 is filled out
Fill the isolation structure to be formed, tunnel oxide 2, floating boom 3 and control gate 4.
As shown in figure 1, and combine Fig. 2, flash memory fabrication method of the invention comprises the following steps：
S1, front-end architecture is provided, the front-end architecture is formed with active area 11 and isolation structure；And
S2, the front-end architecture is annealed, annealing temperature is 1050~1200 degrees Celsius, annealing time 10-50
Minute.
Wherein, there is provided the front-end architecture, step S1 of the front-end architecture formed with active area and isolation structure include：
S11, semi-conductive substrate 1 is provided, form multiple active areas 11 in semiconductor substrate 1, wherein, active area 11 wraps
Include source electrode 11a and drain electrode 11b；
S12, etching forms groove 12 and keeps apart multiple active areas 11 on semiconductor substrate 1；And
S13, to groove 12 isolation oxide is filled to form the isolation structure.
As shown in Fig. 2 the memory cell of typical flash element is the polysilicon manufacture floating boom 3 and control gate 4 with doping,
Control gate 4 is set directly on floating boom 3, is separated by between the two with stacked gate dielectric layer, and floating boom 3 and Semiconductor substrate 1 with
Tunnel oxide 2 is separated by, and adjacent floating boom 3 fills the isolation structure formed by the groove 12 set in Semiconductor substrate 1
And it is isolated.
Optionally, multiple active areas 11 in Semiconductor substrate 1 are formed using self-registered technology.(formed sediment below with floating boom 3
Product have tunnel oxide 2) as mask come carry out source electrode 11a and drain electrode 11b ion implanting so that lap therebetween is several
It has been reduced to zero (substantially avoid overlapping covering of the floating boom 3 with source electrode 11a or the 11b that drains), floating boom 3 and source electrode 11a,
Drain electrode 11b alignment precision is high, while the memory cell that ensure that follow-up flash memory can turn on, additionally it is possible to it is single to reduce storage
The parasitic capacitance of member.While source electrode 11a and drain electrode 11b is formed with ion implanting autoregistration, also toward polysilicon membrane material
Floating boom 3 in be filled with phosphonium ion or arsenic ion, significantly reduce the resistance of floating boom 3.
Optionally, before etching groove 12, sacrifice layer is deposited on semiconductor substrate 1.Subsequently groove 12 is deposited and filled
It is much more general to use high density plasma deposition during isolation oxide, the structure of high energy high density ion destructible active area 11,
Therefore the sacrifice layer can prevent isolation oxide to the structural damage of active area 11 as the isolated protective layer of active area 11.
Optionally, the sacrifice layer includes oxide layer and the nitration case stacked gradually from bottom to up.Nitration case is a kind of hard
Solid mask material, can effectively stop the structural damage of high energy high density ion pair active area 11, be also used as subsequently partly leading
The surface planarisation processing barrier layer of body substrate 1, prevents that grinding and polishing is excessive；And oxide layer is subsequently removing as separation layer
By high energy high density ion contamination nitration case when, active area 11 can be protected not polluted by external environment.
Further, must be deposited before etching groove 12, on the sacrifice layer photoresist and by with the structure of groove 12
Corresponding lithography mask version carries out photoetching, and corresponding photoresist on groove 12 is removed.
Optionally, groove 12 is formed by reactive ion etching.The etching of groove 12 uses anisotropic dry etching more,
Dry etching has three kinds of ion beam milling etching, plasma etching and reactive ion etching main methods.Etched compared to others, instead
Answer ion etching not only to obtain preferable Etch selectivity and speed, active group can also be shortened by the selection of gas
Life-span, suppress the lateral reaction caused by these groups spread in the groove 12 being etched out, during etching groove 12, carve
Lose the etching pollution of ion, group to the active area 11 of the adjacent sidewalls of groove 12 less, etching precision is higher, can reduce to active
The structural damage of area 11.
Optionally, the etching depth of groove 12 is 5000 angstroms to 6000 angstroms.According to production design experience, the one of the present invention
In individual embodiment, the etching depth of groove 12 is between 5000 angstroms to 6000 angstroms.Because the depth of groove 12 is to the reliable of flash memory
Property may have an impact, therefore, with do not consider change groove 12 depth be advisable.In addition, the depth-to-width ratio of groove 12, bottom are inclined
The size at angle and its mitigation degree at edge, have together decided on the structural stability of groove 12, can be done with reference to actual production demand
Flexibly selection.
Optionally, before filling isolation oxide to groove 12, first one layer of liner is deposited in the bottom of groove 12 and side wall
Oxide layer.Interior lining oxide layer can improve the interfacial characteristics of isolation oxide and active area 11, prevent from subsequently using high density etc. from
During daughter deposit filling isolation oxide, the structural damage of high density ion pair active area 11.
Optionally, the filling of the isolation oxide uses high-density plasma chemical vapor deposition method.Using highly dense
Degree plasma activated chemical vapour deposition technique forms isolation junction to deposit the groove 12 that the isolation oxide etches to fill
Structure, higher deposition rate can be obtained.
Further, flash memory fabrication method of the invention also includes step：Enter line storage unit in multiple active areas 11
Construction.Wherein, before the construction that flash memory cell is carried out in multiple active areas 11, using chemical mechanical milling method half-and-half
The surface of conductor substrate 1 carries out planarization process.
And the construction of flash memory cell, self aligned storage organization mainly is formed using photoetching, corrosion, this step can
To be completed according to prior art, the present invention is to this without being described in detail.Due to the structural parameters and device property of flash element
Be closely related, therefore related process parameters can be adjusted flexibly according to actual product demand, for example, can combine priori and
The parameter such as product demand, length, width and height, source knot Implantation Energy and the dosage of thickness, floating boom 3 to tunnel oxide 2 carries out flexible
Adjustment.
Further, flash memory fabrication method of the invention also includes step：Peripheral logic work(is carried out on semiconductor substrate 1
The construction of energy device.All kinds of MOS mainly formed using techniques such as photoetching, corrosion and ion implantings required for functional circuit
Device, this some processes can also be completed according to prior art, and the present invention is to this without being described in detail.Can be according to actual product
Demand, and priori is combined, such as polysilicon gate size, threshold value Implantation Energy and dosage, metal silicide is adjusted flexibly and is formed
The related process parameters such as quality.
Further, the annealing of the front-end architecture is carried out in a nitrogen environment.First will before annealing
Annealing stove evacuation, and nitrogen is filled with backward annealing furnace, start to make annealing treatment.Annealing is carried out in inert nitrogen gas
, ensure the purity of nitrogen, erosion damage of the active gases such as oxygen in annealing to active area 11 can be avoided as far as possible.
Further, the annealing temperature of the annealing is 1050~1200 degrees Celsius, and annealing time is 10-50 points
Clock.In one embodiment of the invention, summarized by test of many times, proper annealing process is：Annealing temperature
For 1080~1120 degrees Celsius, annealing time is 25-35 minutes.Consider the factor such as leakage current effect and cost of reduction, move back
Fiery temperature and annealing time can be selected flexibly.For example, annealing temperature can be 1098.5 degrees Celsius, 1100 degrees Celsius,
1101.5 degrees Celsius, 1106 degrees Celsius etc., annealing time can be 29 minutes, 30 minutes, 30.5 minutes, 31 minutes etc..
In addition, preparation and annealing of the flash memory fabrication method of the present invention except above-mentioned front-end architecture, in addition to rear end
Technique, mainly there are metal connecting line, electric insulating medium deposition and planarization etc..The metal interconnection of flash element is generally no more than 3 layers,
It is usual the problems such as metal electro-migration, stress migration compared with the purely logical CMOS integrated circuit fabrication process of similar technology node
It is not so serious.
In one embodiment, the flash memory fabrication method and common flash memory fabrication method that the present invention is respectively adopted obtain two
Kind flash element, and leakage current test is carried out, obtain both leakage current distribution results as shown in Figure 3 and Figure 4.Compare Fig. 3 and
Fig. 4, using the manufacture method of the present invention, the front-end architecture formed to etching filling after isolation structure is made annealing treatment：Move back
Fiery temperature is 1050~1200 degrees Celsius, and annealing time is 10-50 minutes, and it is micro- that the leakage current of obtained flash element concentrates on 15
Peace left and right, overall distribution is between 13 to 20 microamperes, and integrated distribution is between 13 to 18 microamperes；And use common flash memory system
The leakage current for the flash element that the method for making obtains concentrates on 20 microamperes or so, and overall distribution is and scattered between 13 to 30 microamperes
It is distributed between 13 to 30 microamperes.As can be seen here, flash memory member is significantly reduced using the flash memory fabrication method of the present invention really
The leakage current of part, its electric property is improved, and then improve the yield of product.
In summary, in flash memory fabrication method provided in an embodiment of the present invention, to formed with active area and isolation structure
Front-end architecture made annealing treatment, by annealing, can effectively discharge quarter of the groove in the forming process of isolation structure
Stress caused by the lattice deformity deformation of active area structure caused by erosion or filling；Annealing temperature is taken the photograph for 1050~1200 simultaneously
Family name's degree, annealing time are 10-50 minutes, and annealing temperature is high and annealing time is grown, it is easy to accomplish the motion of lattice dislocation, reduces brilliant
The staggered floor phenomenon of lattice, has effectively repaired the lattice defect of active area, and then reduces in the active area of flash memory because lattice lacks
Leakage current caused by falling into, improves the electric property of flash element and the yield of flash memory products.
The preferred embodiments of the present invention are above are only, any restrictions are not played to the present invention and make use.Belonging to any
Those skilled in the art, in the range of technical scheme is not departed from, to the invention discloses technical scheme and
Technology contents make the variation such as any type of equivalent substitution or modification, belong to the content without departing from technical scheme, still
Belong within protection scope of the present invention.
Claims (10)
- A kind of 1. manufacture method of flash memory, it is characterised in that including：Front-end architecture is provided, the front-end architecture is formed with active area and isolation structure；AndThe front-end architecture is annealed, annealing temperature is 1050~1200 degrees Celsius, and annealing time is 10-50 minutes.
- 2. flash memory fabrication method as claimed in claim 1, it is characterised in that the annealing temperature is 1080~1120 Celsius Degree, annealing time is 25-35 minutes.
- 3. flash memory fabrication method as claimed in claim 1, it is characterised in that the annealing is to carry out in a nitrogen environment 's.
- 4. flash memory fabrication method as claimed in claim 1, it is characterised in that the offer front-end architecture, the front-end architecture Include formed with active area and the step of isolation structure：Semi-conductive substrate is provided, formed with multiple active areas in the Semiconductor substrate；Etching forms groove and opens the multiple active area isolation on the semiconductor substrate；AndTo the trench fill isolation oxide to form the isolation structure.
- 5. flash memory fabrication method as claimed in claim 4, it is characterised in that multiple active areas in the Semiconductor substrate are adopted Formed with self-registered technology.
- 6. flash memory fabrication method as claimed in claim 4, it is characterised in that etching is formed before the groove, described half Sacrifice layer is deposited on conductor substrate.
- 7. flash memory fabrication method as claimed in claim 6, it is characterised in that the sacrifice layer includes stacking gradually from bottom to up Oxide layer and nitration case.
- 8. flash memory fabrication method as claimed in claim 4, it is characterised in that the groove is formed by reactive ion etching.
- 9. flash memory fabrication method as claimed in claim 4, it is characterised in that to before the trench fill isolation oxide, First lining oxide layer in one layer is deposited in the bottom of the groove and side wall.
- 10. flash memory fabrication method as claimed in claim 4, it is characterised in that the filling of the isolation oxide is using highly dense Spend plasma chemical vapor deposition method.
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| CN201710882950.5A CN107658300A (en) | 2017-09-26 | 2017-09-26 | A kind of flash memory fabrication method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1218988A (en) * | 1997-12-01 | 1999-06-09 | 三星电子株式会社 | Method for forming isolated channels in semiconductor device |
| CN102013411A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | Manufacture method for shallow trench isolation structure |
| US9466608B1 (en) * | 2015-10-28 | 2016-10-11 | Freescale Semiconductor, Inc. | Semiconductor structure having a dual-gate non-volatile memory device and methods for making same |
| CN106558589A (en) * | 2015-09-24 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof, electronic installation |
-
2017
- 2017-09-26 CN CN201710882950.5A patent/CN107658300A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1218988A (en) * | 1997-12-01 | 1999-06-09 | 三星电子株式会社 | Method for forming isolated channels in semiconductor device |
| CN102013411A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | Manufacture method for shallow trench isolation structure |
| CN106558589A (en) * | 2015-09-24 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof, electronic installation |
| US9466608B1 (en) * | 2015-10-28 | 2016-10-11 | Freescale Semiconductor, Inc. | Semiconductor structure having a dual-gate non-volatile memory device and methods for making same |
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