CN107658282A - A kind of bonding structure and its manufacture method - Google Patents
A kind of bonding structure and its manufacture method Download PDFInfo
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- CN107658282A CN107658282A CN201610597083.6A CN201610597083A CN107658282A CN 107658282 A CN107658282 A CN 107658282A CN 201610597083 A CN201610597083 A CN 201610597083A CN 107658282 A CN107658282 A CN 107658282A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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Abstract
The present invention, which provides a kind of bonding structure and its manufacture method, the bonding structure, has the graphical wafer of some grooves；Oxide layer, the graphical crystal column surface is formed at, has in the oxide layer and is removed the dashpot that portion of oxide layer is formed；Bonding metal layer, it is formed in the oxide layer.The manufacture method comprises the following steps, step S1：There is provided one has the graphical wafer of some grooves；Step S2：Oxide layer is formed in the graphical crystal column surface, and the oxide layer for removing part forms dashpot；Step S3：In forming bonding metal layer in the oxide layer.A kind of bonding structure provided by the invention and its manufacture method, for solving in the prior art, in bonding technology, because the problem of damaged occurs for the graphic structure that pressure causes the preceding layer process of wafer to be formed.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of bonding structure and its manufacture method.
Background technology
(F2F Stacking), 2.5D silicon intermediary layers are stacked face-to-face in 3D integrated antenna packages, chip
Etc. (Interposer) in technology, the bonding problems of silicon chip and silicon chip can be all related to.
As shown in figs. la-ld, the manufacture method of bonding structure the most frequently used in currently available technology is as follows：One is provided to treat
Wafer 1 ' is handled, photoresist layer is formed in the pending surface of wafer 1 ', the photoresist layer is exposed, developed, shape
Into a graphical photoresist layer 2；Then, formed with the graphical photoresist layer 2 for pending wafer 1 ' described in mask etching
One graphical wafer 1 simultaneously removes photoresist.Then, oxide layer 3 is formed in the graphical surface of wafer 1.Finally, in the oxygen
Change and bonding metal layer 4 is formed on layer 3.
In MEMS fields, some product, it is to be formed on wafer after a part of graphic structure, is just bonded
(Bonding) technique.But due to the pressure influence of Bonding techniques, the graphic structure that preceding layer process is formed easily is broken
The phenomenon of damage.As shown in Fig. 2 due to the pressure influence by Bonding techniques, the oxidation of the recess sidewall of preceding layer process formation
There is phenomenon of rupture in layer, and so as to influence wafer performance, this significantly impacts the quality and yield of bonding.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of bonding structure and its manufacturer
Method, for solving in the prior art, in bonding technology, because the graphic structure that pressure causes the preceding layer process of wafer to be formed is sent out
The problem of raw damaged.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacture method of bonding structure, the key
The manufacture method for closing structure comprises the following steps：Step S1：There is provided one has the graphical wafer of some grooves；Step S2：In
The graphical crystal column surface forms oxide layer, and the oxide layer for removing part forms dashpot；Step S3：In the oxide layer
Upper formation bonding metal layer.
Preferably, the step S1 is further comprising the steps of：Step S1-1：One pending wafer is provided, waits to locate in described
Manage crystal column surface and form photoresist layer；Step S1-2：The photoresist layer is exposed, developed, forms a graphical photoetching
Glue-line；Step S1-3：Several grooves are formed as pending wafer described in mask etching using the graphical photoresist layer, with shape
Into graphical wafer and remove photoresist.
Preferably, the step S2 is further comprising the steps of：Step S2-1：Oxidation is formed in the graphical crystal column surface
Layer；Step S2-2：Photoresist layer is formed in the oxidation layer surface；Step S2-3：The photoresist layer is exposed, shown
Shadow, form a graphical photoresist layer；Step S2-4：Using the graphical photoresist layer as oxide layer described in mask etching, shape
Into the oxide layer with dashpot and remove photoresist.
Preferably, in the step S2, the corner at the top of the oxide layer is performed etching until exposing part
The crystal column surface of recess sidewall and/or partial groove top, form the oxide layer with dashpot.
Preferably, the size range of the crystal column surface of the groove top exposed is 1~2 micron.
The present invention also provides a kind of bonding structure, and the bonding structure includes：One has the graphical wafer of some grooves；
Oxide layer, the graphical crystal column surface is formed at, has in the oxide layer and is removed the buffering that portion of oxide layer is formed
Groove；Bonding metal layer, it is formed in the oxide layer.
Preferably, the dashpot includes multiple cavitys through the oxide layer corner, and exposes the recessed of part
The crystal column surface of groove sidewall and/or partial groove top.
Preferably, the size range of the crystal column surface of the groove top exposed is 1~2 micron.
Preferably, the oxide layer is silicon dioxide layer.
As described above, a kind of bonding structure and its manufacture method of the present invention, due to buffering depositing for slot structure in oxide layer
The space of compensator or trimmer pressure is being left in advance on bottom wafers (Bottom Wafer) surface so that the figure that preceding layer process is formed
After structure is under pressure in bonding technology, it can be discharged into this dashpot, so as to avoid the figure that preceding layer process is formed
Structure is squeezed and breakage.Have the advantages that：1) present invention is the change by technique, avoids Bonding from causing
Bottom wafers (Bottom Wafer) structural failure, improve product yield, reduce cost；2) avoid polluting board；
3) make production stable, it is smooth.
Brief description of the drawings
Fig. 1 a~1d are shown as a kind of bonding structure manufacture method schematic diagram of (in the prior art) of the invention.
Fig. 2 is shown as a kind of bonding structure electron micrograph of (in the prior art) of the invention.
Fig. 3 a~3f are shown as a kind of bonding structure manufacture method schematic diagram of the present invention.
Fig. 4 is shown as a kind of bonding structure electron micrograph of the present invention.
Component label instructions
1 ' the pending graphical photoresist layer of wafer 102 '
1 graphical 102 graphical photoresist layer of wafer
The 2 graphical oxide layers of photoresist layer 103
The dashpot of 3 oxide layer 104
The bonding metal layer of 4 bonding metal layer 105
101 ' the pending grooves of wafer 106
101 graphical wafer step S1~S3
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 3~Fig. 4.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in schema then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The manufacture method of bonding structure in the present embodiment by increase in current technological process special technique come
Realize, as shown in Fig. 3 a~3f, the manufacture method of the bonding structure in the present embodiment comprises the following steps：
As best shown in figures 3 a and 3b, step S1：There is provided one has the graphical wafer 101 of some grooves 106.Specifically, institute
It is further comprising the steps of to state step S1：
Step S1-1：One pending wafer 101 ' is provided, photoresist layer is formed in the pending surface of wafer 101 '.Institute
State the wafer that pending wafer 101 ' can be any required making devices being bonded or special construction.
Step S1-2：The photoresist layer is exposed, developed, forms a graphical photoresist layer 102 '.
Step S1-3：It is that the pending formation of wafer 101 ' is some described in mask etching with the graphical photoresist layer 102 '
Individual groove 106, to form graphical wafer 101 and remove photoresist.
As shown in Fig. 3 c~3e, step S2：Oxide layer 103 is formed in the graphical surface of wafer 101, and removes part
Oxide layer 103 formed dashpot 104.Specifically, the step S2 is further comprising the steps of：
Step S2-1：Oxide layer 103 is formed in the graphical surface of wafer 101.
In step, the methods of oxide layer 103 is silicon dioxide layer, and it is by such as chemical vapor deposition or thermal oxide
It is prepared on the graphical surface of wafer 101.Specifically, described image crystal column surface has multiple grooves 106, described
Thermal growth oxide layer 103 fills the groove 106 to described image wafer all surfaces in groove 106.
Step S2-2：Photoresist layer is formed in the surface of oxide layer 103.
Step S2-3：The photoresist layer is exposed, developed, forms a graphical photoresist layer 102.
Step S2-4：With the graphical photoresist layer 102 for oxide layer 103 described in mask etching, being formed has buffering
The oxide layer 103 of groove 104 simultaneously removes photoresist.
Dry etching or wet etching can be used in this step, because the precision of dry etching is higher, in the present embodiment
Preferably dry etching.The shape of oxide layer 103 after the etching can be any structure for meeting technological requirement.
In step S2-4, dry etching is carried out until exposing part to the corner at the top of oxide layer 103
The side wall of groove 106 and/or the crystal column surface at the partial top of groove 106, form the oxide layer 103 with dashpot 104.It is described
The size range of the crystal column surface of the groove top exposed is 1~2 micron.Specifically, the crystal column surface in the top of groove 106
Oxide layer 103 in etch through multiple sections of the corner of oxide layer 103 be in the cavity of alphabetical " L " shape, formed slow
Jet-bedding 104.The cavity of the crystal column surface at the top of groove 106 integrally connects with the cavity of the side wall of groove 106.This step
In the top of groove 106 crystal column surface cavity (as shown in the double-head arrow mark in dashpot 104 in Fig. 3 e) with groove 106
The turning at top is starting point, extends 1~2 micron of formation along the crystal column surface at the top of the groove 106.
In other embodiment, the dashpot 104 can be located at the optional position of the crystal column surface at the top of groove 106, institute
State dashpot 104 can also can also be not through the oxide layer 103 through the oxide layer 103, the present embodiment does not enter to it
Row limitation.In other embodiment, when performing etching, not only the graphical wafer can also be etched with etching oxidation layer 103
In 101, such as 1~2 micron is etched in the graphical wafer 101.
As illustrated in figure 3f, step S3：In formation bonding metal layer 105 in the oxide layer 103.
Specifically, in this step, when bonding metal layer 105 is formed in the oxide layer 103, metal bonding layer and groove
The oxide layer 103 of the crystal column surface at 106 tops contacts.
Due to the presence of the structure of dashpot 104 in oxide layer 103, left in advance on bottom wafers (Bottom Wafer) surface
The space of compensator or trimmer pressure.After the graphic structure that preceding layer process is formed is under pressure in bonding technology, this can be discharged into
In dashpot 104, so as to which layer process is formed before avoiding graphic structure is squeezed and damaged.As shown in figure 4, preceding layer process shape
Into the oxide layer 103 of the side wall of groove 106 occur phenomenon of rupture no longer occur, this greatly improves the quality of bonding and yield.
In addition, can finally be made annealing treatment with the wafer after para-linkage, the firm of bonding is increased by annealing process
Property.
Embodiment two
As illustrated in figure 3f, this implementation provides a kind of bonding structure and included：One has the graphical wafer of some grooves 106
101；Oxide layer 103, the graphical surface of wafer 101 is formed at, has in the oxide layer 103 and is removed portion of oxide layer
103 dashpots 104 formed；Bonding metal layer 105, it is formed in the oxide layer 103.The oxide layer 103 is dioxy
SiClx layer.
Wherein, the dashpot 104 includes multiple cavitys through the corner of oxide layer 103, and exposes part
The side wall of groove 106 and/or the top of partial groove 106 crystal column surface.The crystal column surface of the groove top exposed
Size range for 1~2 micron (as in dashpot 104 in Fig. 3 e double-head arrow mark shown in).As shown in figure 4, preceding layer process
The oxide layer 103 of the side wall of groove 106 of formation occurs phenomenon of rupture no longer occur, and this greatly improves the quality of bonding and production
Amount.
In summary, a kind of bonding structure of the invention and its manufacture method, have the advantages that：
1) present invention is the change by technique, bottom wafers caused by avoiding Bonding (Bottom Wafer) structure
Breakage, product yield is improved, reduces cost.
2) avoid polluting board.
3) make production stable, it is smooth.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of manufacture method of bonding structure, it is characterised in that the manufacture method of the bonding structure comprises the following steps：
Step S1：There is provided one has the graphical wafer of some grooves；
Step S2：Oxide layer is formed in the graphical crystal column surface, and the oxide layer for removing part forms dashpot；
Step S3：In forming bonding metal layer in the oxide layer.
2. the manufacture method of bonding structure according to claim 1, it is characterised in that：The step S1 also includes following step
Suddenly：
Step S1-1：One pending wafer is provided, photoresist layer is formed in the pending crystal column surface；
Step S1-2：The photoresist layer is exposed, developed, forms a graphical photoresist layer；
Step S1-3：Several grooves are formed as pending wafer described in mask etching using the graphical photoresist layer, with shape
Into graphical wafer and remove photoresist.
3. the manufacture method of bonding structure according to claim 1, it is characterised in that：The step S2 also includes following step
Suddenly：
Step S2-1：Oxide layer is formed in the graphical crystal column surface；
Step S2-2：Photoresist layer is formed in the oxidation layer surface；
Step S2-3：The photoresist layer is exposed, developed, forms a graphical photoresist layer；
Step S2-4：Using the graphical photoresist layer as oxide layer described in mask etching, the oxide layer with dashpot is formed
And remove photoresist.
4. according to the manufacture method of bonding structure according to any one of claims 1 to 3, it is characterised in that：The step S2
In,
Corner at the top of the oxide layer is performed etching until exposing the recess sidewall of part and/or partial groove top
The crystal column surface in portion, form the oxide layer with dashpot.
5. the manufacture method of bonding structure according to claim 4, it is characterised in that：The groove top exposed
The size range of crystal column surface is 1~2 micron.
6. bonding structure according to claim 1, it is characterised in that：The oxide layer is silicon dioxide layer.
7. a kind of bonding structure, it is characterised in that the bonding structure includes：
One has the graphical wafer of some grooves；
Oxide layer, the graphical crystal column surface is formed at, has in the oxide layer and is removed what portion of oxide layer was formed
Dashpot；
Bonding metal layer, it is formed in the oxide layer.
8. bonding structure according to claim 7, it is characterised in that：The dashpot runs through the oxide layer including multiple
The cavity of corner, and expose the recess sidewall of part and/or the crystal column surface of partial groove top.
9. the manufacture method of bonding structure according to claim 8, it is characterised in that：The groove top exposed
The size range of crystal column surface is 1~2 micron.
10. bonding structure according to claim 7, it is characterised in that：The oxide layer is silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610597083.6A CN107658282B (en) | 2016-07-26 | 2016-07-26 | Bonding structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610597083.6A CN107658282B (en) | 2016-07-26 | 2016-07-26 | Bonding structure and manufacturing method thereof |
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| CN107658282A true CN107658282A (en) | 2018-02-02 |
| CN107658282B CN107658282B (en) | 2020-07-07 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069047A (en) * | 1998-09-29 | 2000-05-30 | Wanlass; Frank M. | Method of making damascene completely self aligned ultra short channel MOS transistor |
| CN1700441A (en) * | 2004-05-19 | 2005-11-23 | 上海宏力半导体制造有限公司 | Method for making copper double inlaying arrangement with buffer layer on the side wall |
| CN104183483A (en) * | 2013-05-20 | 2014-12-03 | 上海华虹宏力半导体制造有限公司 | Preparing method for trench Schottky barrier diode |
| CN103839844B (en) * | 2014-03-10 | 2016-09-14 | 上海华虹宏力半导体制造有限公司 | Method for packing |
-
2016
- 2016-07-26 CN CN201610597083.6A patent/CN107658282B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069047A (en) * | 1998-09-29 | 2000-05-30 | Wanlass; Frank M. | Method of making damascene completely self aligned ultra short channel MOS transistor |
| CN1700441A (en) * | 2004-05-19 | 2005-11-23 | 上海宏力半导体制造有限公司 | Method for making copper double inlaying arrangement with buffer layer on the side wall |
| CN104183483A (en) * | 2013-05-20 | 2014-12-03 | 上海华虹宏力半导体制造有限公司 | Preparing method for trench Schottky barrier diode |
| CN103839844B (en) * | 2014-03-10 | 2016-09-14 | 上海华虹宏力半导体制造有限公司 | Method for packing |
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| CN107658282B (en) | 2020-07-07 |
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