The content of the invention
In order to solve the above problems, ridged array semi-conductor lasers proposed by the present invention can reduce active district center temperature
Degree and the temperature difference of both sides temperature on the outside of active area so that whole device architecture uniformity of temperature profile, output characteristics are consistent.
Concrete technical scheme proposed by the present invention is:A kind of ridged array semi-conductor lasers, including substrate, formation are provided
Epitaxial structure on the substrate, the top of the epitaxial structure have ridged semiconductor layer, the ridged semiconductor layer bag
Multiple ridged portions of array are included, the width in the multiple ridged portion is unequal.
Further, in multiple ridged portions of the array, according to the sequence of positions from centre to both sides, the ridged portion
Width increase successively.
Further, multiple symmetrical distributions in ridged portion of the array.
Further, in multiple ridged portions of the array, the width positioned at the first ridged portion at most edge is 10~12 μ
m;And/or the width positioned at the second most middle ridged portion is 6~8 μm;And/or positioned at the first ridged portion and the second ridged
The width in the 3rd ridged portion between portion is 7~9 μm.
Further, the height in the multiple ridged portion is equal.
Further, the distance between two neighboring ridged portion is 100~180 nanometers in the ridged array.
Further, the epitaxial structure includes the cushion, lower limit layer, lower waveguide being set in turn on the substrate
Layer, active layer, electronic barrier layer, upper ducting layer and upper limiting layer, the upper limiting layer are the ridged semiconductor layer.
Further, the bottom of the substrate is formed with hearth electrode;Formed with top electrode, institute on the ridged semiconductor layer
State and coating be provided between each ridged portion of ridged semiconductor layer and the top electrode, the ridged semiconductor layer it is each
Insulating barrier is provided between the both sides in ridged portion and the top electrode.
Further, the material of the substrate is N-type self-standing gan, and the material of the cushion is n-type doping
Gallium nitride, the material of the lower limit layer are the aluminium gallium nitride alloy of n-type doping, and the material of the lower waveguide layer is the nitrogen of n-type doping
Change gallium, the material of the electronic barrier layer is the aluminium gallium nitride alloy of p-type doping, and the material of the upper ducting layer is the nitrogen of p-type doping
Change gallium, the material of the upper limiting layer is the aluminium gallium nitride alloy of p-type doping, and the material of the coating is the gallium nitride of p-type doping,
The material of the insulating barrier is silica, and the active layer is SQW, it include the gallium nitride barrier layer of alternating growth and
InGaN potential well layer.
The present invention also provides a kind of preparation method of ridged array semi-conductor lasers as described above, including step:
There is provided a substrate and the substrate grown on top formed with epitaxial structure;
The epitaxial structure is etched using etching technics, the ridged semiconductor is formed at the top of the epitaxial structure
Layer.
Ridged array semi-conductor lasers proposed by the present invention, by setting multiple ridged portions at the top of epitaxial structure,
The width in multiple ridged portions is unequal, can reduce laser active district center and the temperature difference of active area both sides at work, from
And cause whole laser structure uniformity of temperature profile so that output characteristics is consistent during laser works.
Embodiment
Hereinafter, with reference to the accompanying drawings to embodiments of the invention are described in detail.However, it is possible to come in many different forms real
Apply the present invention, and the specific embodiment of the invention that should not be construed as limited to illustrate here.Conversely, there is provided these implementations
Example is in order to explain the principle and its practical application of the present invention, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.
Referring to Figures 1 and 2, the ridged array semi-conductor lasers that the present embodiment provides, including substrate 10, are formed at substrate
The epitaxial structure 11 at 10 top;The top of epitaxial structure 11 has ridged semiconductor layer 80, and ridged semiconductor layer 80 includes more
Individual ridged portion 110,111,112,113,114, wherein, the width in multiple ridged portions 110,111,112,113,114 is unequal.
Preferably, it is suitable according to the position from centre to both sides in multiple ridged portions 110,111,112,113,114 of array
Sequence, the width in ridged portion 110,111,112,113,114 increase successively.Wherein, multiple ridged portions 110 of array, 111,112,
113rd, 114 symmetrical distribution.Specifically, as shown in figure 1, in multiple ridged portions 110,111,112,113,114 of array,
Width positioned at the first ridged portion 110,111 at most edge is 10~12 μm;Width positioned at the second most middle ridged portion 114
For 6~8 μm;The width in the 3rd ridged portion 112,113 between the first ridged portion 110,111 and the second ridged portion 114 is 7
~9 μm.The height in multiple ridged portions 110,111,112,113,114 is equal in ridged semiconductor layer 80, wherein, two neighboring ridge
Shape portion 110,111,112,113, the distance between 114 is 100~180nm.During actual fabrication, user can be according to need
Come set the height in each ridged portion 110,111,112,113,114, width and two neighboring ridged portion 110,111,
112nd, 113, the distance between 114.
As a specific example, the ridged array in the present embodiment includes 5 ridged portions, as shown in figure 1, being respectively
Positioned at two first ridged portions 110,111 at most edge, positioned at a most middle second ridged portion 114, positioned at the first ridged
Two the 3rd ridged portions 112,113 between portion 110,111 and the second ridged portion 114.Wherein, two the 3rd ridged portions 112,
113 on the 114 symmetrical distribution of the second ridged portion, and two the first ridged portions 110,111 are on 114 or so pairs of the second ridged portion
Claim distribution.The width in the first ridged portion 110,111 can be selected in the range of 10~12 μm, the 3rd ridged portion 112,113
Width can be selected in the range of 7~9 μm, and the width in the second ridged portion 114 can be selected in the range of 6~8 μm, and
Meet condition:The width in the first ridged portion 110,111 is more than the width in the 3rd ridged portion 112,113, the 3rd ridged portion 112,113
Width be more than the width of the second ridged portion 114.Further, the first ridged portion 110,111, the second ridged portion 114 and the 3rd
The height in ridged portion 112,113 is equal, and two ridged portions 110,111,112,113, the distance between 114 of arbitrary neighborhood can be with
For 100~180nm.
Reference picture 2, epitaxial structure 11 include being set in turn in the cushion 20 at top of substrate 10, lower limit layer 30, under
Ducting layer 40, active layer 50, electronic barrier layer 60, upper ducting layer 70 and upper limiting layer 80a.Wherein, upper limiting layer 80a is
Ridged semiconductor layer 80, multiple ridged portions 110,111,112,113,114 are formed at upper limiting layer 80a top.Substrate 10
Bottom is formed with hearth electrode 12, formed with top electrode 14 on ridged semiconductor layer 80 (upper limiting layer 80a), multiple ridged portions 110,
111st, coating 13 is respectively arranged between 112,113,114 and top electrode 14;Each ridged portion 110,111,112,113,114
Both sides and top electrode 14 between be provided with insulating barrier 15.
Specifically, the material of substrate 10 is gallium nitride, sapphire or carborundum, it is preferred that the material of substrate 10 is N-type
Self-standing gan.The material of coating 13 is the gallium nitride of p-type doping, and it is used to form Ohmic contact with top electrode 14.Absolutely
The material of edge layer 15 is silica, and it is used to prevent current leakage.Hearth electrode 12 and top electrode 14 are metal electrode, for shape
Into Ohmic contact, it is easy to extraction electrode lead.The material of cushion 20 is the gallium nitride of N doping, and it is used for buffer lattice mismatch
Caused stress, in favor of the growth of remaining epitaxial layer.The material of lower limit layer 30 be n-type doping aluminium gallium nitride alloy, upper limitation
Layer 80a material is the aluminium gallium nitride alloy of p-type doping, wherein, lower limit layer 30 is used to limit light field in the direction towards substrate 10
Upper extension, upper limiting layer 80a extend up for limiting light field away from the side of substrate 10.The material of lower waveguide layer 40 is N-type
The gallium nitride of doping, the material of upper ducting layer 70 are the gallium nitride of p-type doping, and lower waveguide layer 40 and upper ducting layer 70 are used to increase
To the restriction effect of carrier, increase carrier reduces threshold value in the distribution of active area, raising light restriction factor, and increase is luminous
Efficiency.Active layer 50 is SQW, and it includes the gallium nitride barrier layer and InGaN potential well of 1~10 cycle alternating growth
Layer, for providing the gain of light.The material of electronic barrier layer 60 is the aluminium gallium nitride alloy of p-type doping, is overflow for stopping in active layer 50
The electronics gone out.
Shown in reference picture 3a~Fig. 3 e, the present embodiment also provides the making of ridged array semi-conductor lasers as described above
Method, so that operation wavelength is 450nm gallium nitride based blue laser device as an example, the preparation method comprises the following steps:
Step S1, one substrate 10 is provided and grown over the substrate 10 formed with epitaxial structure 11.
Specifically, step S1 includes being sequentially depositing cushion 20, lower limit layer 30 over the substrate 10, lower waveguide layer 40, had
Active layer 50, electronic barrier layer 60, upper ducting layer 70, upper limiting layer 80a and coating 13 (as shown in Figure 3 a), wherein, deposit work
Skill is MOCVD (MOCVD) technique or molecular beam epitaxy (MBE) technique.Wherein, cushion 20
Thickness be 5 μm, its material be n-type doping gallium nitride, doping concentration be 3 × 1018cm-3;The thickness of lower limit layer 30 is
0.8 μm, its material is the Al of n-type doping0.1Ga0.9N, doping concentration are 3 × 1018cm-3;The thickness of lower waveguide layer 40 is 0.08 μ
M, its material are the gallium nitride of n-type doping, and doping concentration is 5 × 1015cm-3;Active layer 50 includes 5 cycle alternating growths
Gallium nitride barrier layer and InGaN potential well layer, wherein, the thickness of gallium nitride barrier layer is 8nm, doping concentration is 3 × 1017cm-3, the thickness of InGaN potential well layer is 3nm, and its material is In0.17Ga0.83N;The thickness of electronic barrier layer 60 is 20nm, its material
Matter is the Al of p-type dopingxGa1-xN, doping concentration are 5 × 1015cm-3;The thickness of upper ducting layer 70 is 0.08 μm, and its material is P
The gallium nitride of type doping, doping concentration are 3 × 1017cm-3;Upper limiting layer 80a thickness is 0.6 μm, and its material is adulterated for p-type
Al0.08Ga0.92N, doping concentration are 8 × 1019cm-3;The thickness of coating 13 is 0.2 μm, and its material is the nitridation of p-type doping
Gallium, doping concentration are 2.4 × 1020cm-3。
Step S2, using etching technics from the top etch of coating 13 to the epitaxial structure 11, in the epitaxy junction
The ridged semiconductor layer 80, (as shown in Figure 3 b) are formed on the top of structure 11.
Specifically, using etching technics from the top etch of coating 13 to upper limiting layer 80a, to cause upper limiting layer
80a top has multiple ridged portions 110,111,112,113,114, forms the ridged semiconductor layer 80.Array it is multiple
In ridged portion 110,111,112,113,114, the width positioned at the first ridged portion 110,111 at most edge is 10~12 μm;Position
Width in the second most middle ridged portion 114 is 6~8 μm;Positioned at the first ridged portion 110,111 and the second ridged portion 114 it
Between the width in the 3rd ridged portion 112,113 be 7~9 μm, and meet condition:The width in the first ridged portion 110,111 is more than
The width in the 3rd ridged portion 112,113, the width in the 3rd ridged portion 112,113 are more than the width of the second ridged portion 114.Ridged is partly led
The height in multiple ridged portions 110,111,112,113,114 is equal in body layer 80, wherein, two neighboring ridged portion 110,111,
112nd, 113, the distance between 114 be 100~180nm.Wherein, etching technics is reactive ion etching process.
Step S3, on ridged semiconductor layer 80, growth forms insulating barrier 15 and top electrode 14 successively, and insulating barrier 15 is located at
Between the both sides in each ridged portion of ridged semiconductor layer 80 and top electrode (as shown in Figure 3 c).Wherein, by evaporation process system
Standby insulating barrier 15, top electrode 14 is prepared with the technique of evaporation or magnetron sputtering.
Step S4, the substrate 10 (as shown in Figure 3 d) is thinned from the bottom of the substrate 10.Specifically, by substrate 10
Bottom is thinned to 60~100 μm.
Step S5, in the bottom deposit hearth electrode 12 (as shown in Figure 3 e) of the substrate 10.
In actual fabrication process, Cavity surface will be formed along m faces cleavage by laser prepared by the above method, then will nitridation
The laser tube core of a length of 800 μm of [11-20] face cleavage coelosis of gallium, a pair of TiO are deposited in the front facet of laser tube core2/
SiO2Three couples of TiO are deposited in reflectance coating, rear facet2/SiO2Reflectance coating, and chip of laser is solder-connected to AlN heat with Au/Sn
On heavy.Last extraction electrode again, it is packaged into laser device.
The method that we calculate temperature with simulation nitrogenizes to the ridged array semi-conductor lasers of the present embodiment and single ridged
Gallium laser compares, wherein:
For single ridge gallium nitride laser, junction temperature and the relation of thermal resistance are utilized:
Rth=△ T/ (IH*VH-Popt)
Being calculated according to the gallium nitride based blue laser device of the present embodiment, ridged step width is 10 μm, thermal resistance 22K/W,
Environment temperature is 24 DEG C, is approximately considered device surface temperature and is equal to environment temperature.For single ridge gallium nitride laser, calculate
Temperature-difference 40K of device surface temperature and active area or so;And for the ridged array semi-conductor lasers in the present embodiment,
The temperature-difference of gauging surface temperature and active area is simulated, its thermal resistance is 6~7K/W, reduces device thermal resistance, in device architecture
Temperature Distribution relatively single ridge gallium nitride laser in portion's is substantially uniform, and the whole device inside temperature difference reduces, and identical injecting
Current density when, heat is wide directly proportional to bar caused by laser, and electric current on the wide most narrow ridged of bar is minimum, heat production
It is few, active area temperature and the temperature difference of both sides are reduced relative to single ridge gallium nitride laser, it is warm for total
Degree distribution is almost identical.
Described above is only the embodiment of the application, it is noted that for the ordinary skill people of the art
For member, on the premise of the application principle is not departed from, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as the protection domain of the application.