CN107636804B - Method for forming ohmic contact with semiconductor using quantized metal - Google Patents

Method for forming ohmic contact with semiconductor using quantized metal Download PDF

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CN107636804B
CN107636804B CN201580080401.5A CN201580080401A CN107636804B CN 107636804 B CN107636804 B CN 107636804B CN 201580080401 A CN201580080401 A CN 201580080401A CN 107636804 B CN107636804 B CN 107636804B
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metal
interface
contact
semiconductor material
region
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CN107636804A (en
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B.朱-龚
V.H.勒
R.里奥斯
G.德维
S.B.克伦登宁
J.T.卡瓦利罗斯
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Intel Corp
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Abstract

An apparatus includes an integrated circuit device including at least one low density of states metal/semiconductor material interface, wherein the at least one low density of states metal is quantized. An apparatus includes an integrated circuit device including at least one interface of a low density of states metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method includes confining a contact region of a semiconductor material; and forming a metal contact in the contact region.

Description

Method for forming ohmic contact with semiconductor using quantized metal
Technical Field
An integrated circuit device.
Background
Description of the Related Art
Integrated circuit devices typically employ metal-to-semiconductor contacts. One example is contact to the junction region (source or drain region) of a transistor device.
When depositing metal onto a semiconductor material, dangling bonds at the semiconductor surface cause the fermi levels of the metal and the semiconductor material to be mismatched. The result is that the fermi level in the semiconductor pins to a specific energy level (an energy level in the bandgap), which creates a barrier for carriers to pass through. As metal-to-semiconductor contact areas and integrated circuit devices become smaller, the resistance associated with such contact areas becomes larger (contact resistance is proportional to the inverse of contact area). Thus, the contact resistance becomes a large percentage of the overall parasitics of the device. Solutions to address contact resistance include creating less reactive contacts and reducing bandgap interfacial contacts or using lower bandgap interfacial contact layers.
Drawings
Figure 1 illustrates an embodiment of a cross-sectional side view of a transistor device having a metal contact to junction regions of the device.
Fig. 2 illustrates a portion of the transistor device of fig. 1 and a corresponding band structure.
Figure 3 illustrates a cross-sectional side view of a portion of another embodiment of a transistor device with a contact to a junction region and a metal/semiconductor material interface having a tapered shape.
Figure 4 illustrates a cross-sectional side view of a portion of another embodiment of a transistor device having a dielectric material restricting contact to junction regions.
Figure 5 illustrates another embodiment of a portion of a transistor device having a metal contact directly connecting (directly contacting) the channel of the device.
FIG. 6 is an interposer implementing one or more embodiments.
FIG. 7 illustrates an embodiment of a computing device.
Detailed Description
Techniques for reducing contact resistance at a metal-to-semiconductor interface (metal-to-semiconductor contact) are presented, as are transistor devices employing such techniques. In one embodiment, the contact resistance between the metal and semiconductor material is reduced by ramping the metal/semiconductor material interface to smooth out the band discontinuity. In one embodiment, the grading is achieved by confining (e.g., quantizing) the low density of states metal, wherein the metal is more confined (e.g., more quantized) toward the semiconductor.
Figure 1 illustrates a cross-sectional side view of an embodiment of a transistor device having a metal contact formed to a junction region of the device. Referring to fig. 1, a device structure 100 includes a substrate 110 of semiconductor material such as silicon, silicon germanium, III-V or II-VI compound semiconductors. Disposed on substrate 110 are transistor devices that include junction region 120 (e.g., source), junction region 130 (e.g., drain), channel 140 between the source and drain, gate dielectric 145 and gate electrode 150 over channel 140. A dielectric material 180 surrounds the components of the device structure. In embodiments where the transistor device is a field effect transistor (single gate or multi-gate transistor), junction region 120 and junction region 130 are semiconductor materials such as doped silicon, silicon germanium, III-V, or II-VI compound semiconductors. In one embodiment, for a p-type device, junction region 120 and junction region 130 are both p + silicon germanium or p + silicon, for example.
Figure 1 shows metal contacts to each of junction region 120 and junction region 130. In one embodiment, the material of metal contact 160 and metal contact 170 to the respective junction regions is a low density of states metal. Examples of low energy density state metals include, but are not limited to, antimony (Sb), bismuth (Bi), tin (Sn), and alloys thereof. These metals can be deposited by physical line-of-sight methods such as evaporation or sputtering, or by chemical means such as Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD). Chemical thin film deposition techniques include, but are not limited to, techniques such as SbCl3Or SnCl4Such as volatile metal chlorides, as a precursor together with a co-reactant such as hydrogen plasma or a co-reactant such as Sb (SiR)3)3Or Sn (SiR)3)4Or Sn (SiR)3)2And the use of such co-reactants with a metalosilyl group, wherein R is an organic substituent including, but not limited to, methyl, ethyl, isopropyl, butyl, or phenyl. To achieve void-free contact fill, it may or may not be inertAnnealing the metal either under a reducing atmosphere, such as one containing hydrogen. Figure 1 shows the interface between the metal contact and the semiconductor material of the junction (contact 160/junction region 120 and contact 170/junction region 130), which is graded as in the sense that the metal is increasingly confined by the semiconductor material. Fig. 1 shows a metal to semiconductor material interface having the following profile: so that the contact area between the semiconductor material and the metal (as viewed) taken through the horizontal cross-section of the interface is progressively smaller proceeding in a direction toward the substrate 110. Such limitations tend to quantify the metal in contact.
Fig. 2 shows a portion of a transistor device and a corresponding bandgap. Fig. 2 illustrates that the gradual transition of the metal/semiconductor material interface of the gradually confined (e.g., quantized) metal results in a gradual transition of the band discontinuity. Figure 2 illustrates that the barrier height at a first location (location 1) where the cross-sectional contact area between the metal and the semiconductor material is dominated by the metal material (the least restrictive metal state) has a barrier height between the valence band and the metal work function. At the cross-section through the interface contacting the semiconductor material at position 2, the metal material becomes more confined by the semiconductor material resulting in a barrier height ΦB2(ii) a Is even more limited at position 3 resulting in what is illustrated as ΦB3The barrier height of (d); and finally only the semiconductor material at position 4 and thus the barrier height ΦB4. Contact resistance is expressed
Figure 294273DEST_PATH_IMAGE001
But is exponentially proportional to the barrier height. By splitting the barrier height into different sub-components (phi)B1，ΦB2，ΦB3And phiB4) Reduce the resistance because
Figure 808431DEST_PATH_IMAGE002
Is less than
Figure 378DEST_PATH_IMAGE003
。
In the above embodiments, the interface between the metal and the semiconductor material is shown as graded or stepped. It is appreciated that other limiting profiles will also be suitable. Fig. 3 illustrates a cross-sectional side view of a portion of another embodiment of a transistor device. The device 200 includes a junction region 220 (e.g., source or drain) at a channel 240 on a substrate 210 and a metal contact 260 to the junction region 220. Fig. 3 shows an interface having a conical shape. The graded interface (fig. 1) or the tapered interface of fig. 3 can be formed by an etching process into the junction region material followed by metal deposition. In another embodiment, such a tapered or stepped etch profile need not be precise (e.g., due to etch recipe or tool properties), but rather may be suitable in terms of confining (e.g., quantifying) the low density of states metal to a contoured contact, such as contact 260 or contact 160.
Fig. 4 illustrates a cross-sectional side view of a portion of another embodiment of a transistor device. Fig. 4 shows a transistor device 300 including a junction region 320 (e.g., source or drain) and a channel 340 on a substrate 310. Figure 4 also shows a contact 360 to junction region 320. In this embodiment, the contact 360, for example, of a low density of states metal, is bounded by a dielectric material 370. The dielectric material, such as deposited silicon dioxide, is a high bandgap material that when it confines a metal will reflect a similar band structure to that shown in figure 2. As illustrated, in this embodiment, the cross-sectional area of the metal contact 360 decreases in a tapered manner in a direction towards the junction region 320. In another embodiment, the confinement of the metal contact 360 in a direction toward the semiconductor material 320 may have other profiles, including a step profile for a regular profile, which similarly confines (e.g., quantifies) the metal material.
Fig. 5 illustrates another embodiment of a portion of a transistor device. The device 400 includes a channel 440 formed on a substrate 410 and a metal contact 460 in direct contact with the channel 440. In other words, for example, the junction region (source or drain) of the semiconductor material is removed and the metal directly contacts the channel 440 of the transistor device. As illustrated, the contacts 460 are defined by a dielectric layer 470. When the metal contacts the channel 440, the metal is confined by the dielectric layer 470 at the channel 440. Each of the low-doped semiconductor material for the channel 440 and the dielectric layer 470 is a high bandgap material. A high band gap will tend to increase the barrier. Thus, in this case, the restriction of adding metal in a direction toward the channel 440 will have a tendency to smooth out the junction and reduce the contact resistance.
Fig. 6 illustrates an interposer 500 that includes one or more embodiments. The interposer 500 is an intervening substrate used to bridge a first substrate 502 to a second substrate 504. The first substrate 502 may be, for example, an integrated circuit die. The second substrate 504 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 500 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, the interposer 500 may couple the integrated circuit die to a Ball Grid Array (BGA) 506, which may then be coupled to the second substrate 504. In some embodiments, the first and second substrates 502/504 are attached to opposite sides of the interposer 500. In other embodiments, the first and second substrates 502/504 are attached to the same side of the interposer 500. In further embodiments, three or more substrates are interconnected by interposer 500.
Interposer 500 may be formed from epoxy, fiberglass reinforced epoxy, ceramic material, or polymeric material such as polyimide. In further implementations, the interposer may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.
The interposer may include metal interconnects 508 and vias 510, including but not limited to through-silicon vias (TSVs) 512. The interposer 500 may also include embedded devices 514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 500.
In accordance with an embodiment, the devices or processes disclosed herein may be used in the fabrication of interposer 500.
FIG. 7 illustrates a computing device in accordance with one embodiment. Computing device 600 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternative embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. Components in computing device 600 include, but are not limited to, an integrated circuit die 602 and at least one communication chip 608. In some implementations, the communication chip 608 is fabricated as part of the integrated circuit die 602. The integrated circuit die 602 may include a CPU 604 and on-die memory 606 (typically used as cache memory, which may be provided by technologies such as embedded dram (edram) or spin transfer torque memory (STTM or STTM-RAM)).
Computing device 600 may include other components that may or may not be physically and electrically coupled to a motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 610 (e.g., DRAM), non-volatile memory 612 (e.g., ROM or flash memory), a graphics processing unit 614 (GPU), a digital signal processor 616, a crypto processor 642 (a special purpose processor that performs cryptographic algorithms in hardware), a chipset 620, an antenna 622, a display or touchscreen display 624, a touchscreen controller 626, a battery 628 or other power source, a power amplifier (not shown), a Global Positioning System (GPS) device 644, a compass 630, a motion co-processor or sensor 632 (which may include an accelerometer, gyroscope, and compass), a speaker 634, a camera 636, a user input device 638 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 640 (such as a hard drive, Compact Disc (CD), Digital Versatile Disc (DVD), and so forth).
The communication chip 608 enables wireless communication for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 608 may implement any of a number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and above. The computing device 600 may include a plurality of communication chips 608. For example, the first communication chip 608 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 608 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 604 of the computing device 600 includes one or more devices, such as transistors or metal interconnects, formed in accordance with embodiments, including a metal-to-semiconductor interface as described to confine low energy density metal. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 608 may also include one or more devices, such as transistors or metal interconnects, formed in accordance with embodiments, including a metal-to-semiconductor interface as described to confine low energy density metal.
In further embodiments, another component housed within the computing device 600 may contain one or more devices, such as transistors or metal interconnects, formed in accordance with implementations, including a metal-to-semiconductor interface as described to confine low energy density metal.
In various embodiments, the computing device 600 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.
Examples of the invention
The following examples pertain to embodiments:
example 1 is an apparatus comprising an integrated circuit device comprising at least one low density of states metal/semiconductor material interface, wherein the at least one low density of states metal is quantized.
In example 2, the quantization of example 1 is a graded quantization, wherein the metal is quantized more at a first point of the interface than at a second point of the interface.
In example 3, a contact area of the metal and the semiconductor material at the interface of any of examples 1 or 2 decreases in a graded manner.
In example 4, the semiconductor material of any of examples 1-3 includes a heavily doped semiconductor material.
In example 5, the contact area of the metal and the semiconductor at the interface of example 4 is reduced in a graded manner.
In example 6, the metal of any of examples 1-4 is confined in the dielectric material and the quantification is quantified by a grading of the dielectric material, the metal being quantified more at the interface than at a point away from the interface.
In example 7, the metal/semiconductor interface of any of examples 1-4 includes a junction region of a transistor device.
In example 8, the metal of example 1 includes a channel of a contact and semiconductor material transistor device.
In example 9, the contact area of the contact and the channel at the interface of example 8 decreases in a graded manner.
In example 10, the at least one low density of states metal of any of examples 1-4 includes antimony, bismuth, tin, or an alloy thereof.
Example 11 is an apparatus comprising a transistor comprising a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; a source on one side of the gate electrode, a drain on an opposite side of the gate electrode, and a channel between the source and the drain, each of the source, the drain, and the channel comprising a semiconductor material; and a contact to one of the source and drain, wherein the contact comprises a low energy density of states metal, and an interface of the low energy density of states metal to the semiconductor material of the one of the source and drain and the channel is graded.
In example 12, the contact region of example 11 is confined by the semiconductor material of the one of the source and drain or the channel, and the contact region of the interface changes from the first region to the second region.
In example 13, the first region of example 12 is disposed at a greater distance toward the metal side of the interface than the second region.
In example 14, the semiconductor material of any of examples 11-13 includes a heavily doped semiconductor material.
In example 15, the semiconductor material of example 14 includes the one of the source and the drain.
In example 16, the apparatus of example 11 includes a dielectric material on the transistor, wherein the contact is disposed through the dielectric material and the contact area of the metal is confined in the dielectric material.
In example 17, the semiconductor material of example 11 includes a channel.
In example 18, the apparatus of example 17 includes a dielectric material on the transistor, wherein the contact is disposed through the dielectric material and a contact area of the contact is limited by the dielectric material and the channel.
In example 19, the at least one low density of states metal of any of examples 11-18 includes antimony, bismuth, tin, or an alloy thereof.
Example 20 is a method comprising limiting a contact region of a semiconductor material; and forming a metal contact in the contact region.
In example 21, the restricting the contact area of example 20 includes ramping the contact area of the semiconductor material from a first area to a smaller second area.
In example 22, the limiting the contact region of any of claims 20 or 21 comprises forming an opening in the dielectric material.
In example 23, the semiconductor material of any of examples 20 or 21 includes a channel of a transistor device.
In example 24, the metal of example 20 comprises a low energy density of states metal.
In example 25, forming the metal of example 24 includes depositing the metal by a chemical thin film technique and annealing under an inert or reducing atmosphere.
The above description of illustrated implementations, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope, as those skilled in the relevant art will recognize.
These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (26)

1. An integrated circuit device, comprising:
an integrated circuit device comprising at least one low density of states metal/semiconductor material interface, wherein said at least one low density of states metal is quantized,
wherein the quantifying is a graded quantifying, wherein the low density of states metal is more quantified at a first point of the interface than at a second point of the interface;
wherein the low density of states metal is one of: antimony (Sb), bismuth (Bi), tin (Sn), and alloys thereof;
wherein the interface between the low density of states metal and the semiconductor material has a stepped profile;
wherein the contact area between the low density of states metal and the semiconductor material is taken through a horizontal cross section of the interface and gradually becomes smaller going in a direction from the top of the interface to the bottom of the interface.
2. The device of claim 1, wherein the semiconductor material comprises a heavily doped semiconductor material.
3. The apparatus of claim 2, wherein a contact area of the metal and the semiconductor at the interface decreases in a graded manner.
4. The apparatus of any of claims 1-2, wherein the low energy density of states metal is confined in a dielectric material and quantization is by graded quantization of the dielectric material, the low energy density of states metal being quantized more at an interface than at a point away from the interface.
5. The apparatus of any of claims 1-2, wherein the metal/semiconductor interface comprises a junction region of a transistor device.
6. The apparatus of claim 1, wherein the low density of states metal comprises a contact and the semiconductor material comprises a channel of a transistor device.
7. The apparatus of claim 6, wherein the contact area of the channel and the contact at the interface decreases in a graded manner.
8. An integrated circuit device, comprising:
a transistor, comprising:
a gate dielectric layer formed on the substrate;
a gate electrode formed on the gate dielectric layer;
a source on one side of the gate electrode, a drain on an opposite side of the gate electrode, and a channel between the source and the drain, each of the source, the drain, and the channel comprising a semiconductor material; and
a contact to one of the source and the drain, wherein the contact comprises a low energy density of states metal, and an interface of the low energy density of states metal to the semiconductor material of the one of the source and the drain and the channel is graded,
wherein the low density of states metal is one of: antimony (Sb), bismuth (Bi), tin (Sn), and alloys thereof;
wherein the interface between the low density of states metal and the semiconductor material has a stepped profile;
wherein the contact portion is taken through a horizontal cross section of the interface and gradually becomes smaller in going in a direction from a top of the interface to a bottom of the interface.
9. The device of claim 8, wherein the contact region is bounded by the semiconductor material of one of the source and drain or the channel, and the contact region of the interface changes from the first region to the second region.
10. The device of claim 9, wherein the first region is disposed at a greater distance toward the metal side of the interface than the second region.
11. The apparatus of any of claims 8-9, wherein the semiconductor material comprises a heavily doped semiconductor material.
12. The device of claim 11, wherein the semiconductor material comprises the one of a source and a drain.
13. The apparatus of claim 8, further comprising a dielectric material on the transistor, wherein the contact is disposed through the dielectric material and limits a contact area of the metal in the dielectric material.
14. The device of claim 8, wherein the semiconductor material comprises a channel.
15. The apparatus of claim 14, further comprising a dielectric material on the transistor, wherein the contact is disposed through the dielectric material and a contact area of the contact is bounded by the dielectric material and the channel.
16. A method for forming an ohmic contact to a semiconductor using a quantization metal, comprising:
limiting a contact area of semiconductor material; and
a metal contact is formed in the contact area,
wherein the metal contact comprises a low energy density of states metal and an interface between the low energy density of states metal and the semiconductor material;
wherein the low density of states metal is one of: antimony (Sb), bismuth (Bi), tin (Sn), and alloys thereof;
wherein the interface between the low density of states metal and the semiconductor material has a stepped profile;
wherein the contact area is taken through a horizontal cross-section of the interface and gradually becomes smaller in going in a direction from a top of the interface to a bottom of the interface.
17. The method of claim 16, wherein confining the contact region comprises ramping the contact region of semiconductor material from a first region to a smaller second region.
18. The method of any of claims 16 or 17, wherein limiting the contact area comprises forming an opening in the dielectric material.
19. The method of any of claims 16 or 17, wherein the semiconductor material comprises a channel of a transistor device.
20. The method of claim 16, wherein forming the low density of states metal comprises depositing the metal by a chemical thin film technique and annealing under an inert or reducing atmosphere.
21. A computer-readable medium having stored thereon instructions that, when executed, cause a computing device to perform the method of any of claims 16 to 20.
22. An apparatus, comprising:
means for confining a contact region of semiconductor material; and
means for forming a metal contact in the contact area,
wherein the contact region comprises a low energy density of states metal and an interface between the low energy density of states metal and the semiconductor material;
wherein the low density of states metal is one of: antimony (Sb), bismuth (Bi), tin (Sn), and alloys thereof;
wherein the interface between the low density of states metal and the semiconductor material has a stepped profile;
wherein the contact area is taken through a horizontal cross-section of the interface and gradually becomes smaller in going in a direction from a top of the interface to a bottom of the interface.
23. The apparatus of claim 22, wherein the means for confining the contact region comprises means for ramping the contact region of the semiconductor material from a first region to a smaller second region.
24. The apparatus of any of claims 22 or 23, wherein the means for limiting the contact area comprises means for forming an opening in a dielectric material.
25. The apparatus of any of claims 22 or 23, wherein the semiconductor material comprises a channel of a transistor device.
26. The apparatus of claim 22, wherein the means for forming the low density of states metal comprises means for depositing metal by chemical thin film techniques and means for annealing under an inert or reducing atmosphere.
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