CN107632914B - Fault positioning method and system for EMMC array - Google Patents
Fault positioning method and system for EMMC array Download PDFInfo
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Abstract
The application provides a fault positioning method of an EMMC array, which comprises the steps of monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the position of the EMMC chip with the initialization fault when the initialization fault of any one EMMC chip is monitored; when the initialization of the EMMC array normally passes, detecting the erasing function of each EMMC chip, and when the erasing function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal erasing function; when the erasing function of the EMMC array is detected to be normal, detecting the writing function of each EMMC chip, and when the writing function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal writing function; when the write function of the EMMC array is detected to be normal, the read function of each EMMC chip is detected, and when the read function of any one EMMC chip is detected to be abnormal, the position of the EMMC chip with the abnormal read function is output, so that the all-dimensional fault detection and fault positioning of the EMMC array are realized.
Description
Technical Field
The invention relates to the technical field of fault location, in particular to a fault location method and system of an EMMC array.
Background
The EMMC (english full name: Embedded Multi Media Card) is the standard specification of the Embedded memory that is established by the MMC association and mainly aims at products such as mobile phones or tablet computers. The EMMC integrates a controller in the package, provides a standard interface and manages the flash memory, so that the handset manufacturer can concentrate on other parts of the product development and shorten the time to market the product.
The EMMC array generally refers to a memory chip in a mobile phone or a tablet computer, and compared with a general FLASH, the EMMC array is internally provided with an MCU (micro controller Unit), and can be read, written and erased through instruction control.
In the prior art, the fault state of the EMMC array is generally determined by monitoring the initialization state, and if the EMMC does not find a fault in the initialization process, the EMMC array starts to operate normally. However, when an EMMC array fails during operation, it is impossible to determine the type of the failure, and it is also impossible to determine which EMMC chip in the EMMC array fails.
Disclosure of Invention
In view of this, the present invention provides a method and a system for locating a fault of an EMMC array, which can detect and locate the fault of the EMMC array during initialization, erasing data after initialization, and reading and writing.
In order to achieve the above purpose, the invention provides the following specific technical scheme:
a fault location method of an EMMC array comprises the following steps:
monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the position of the EMMC chip with the initialization fault when any one EMMC chip with the initialization fault is monitored;
when the initialization of the EMMC array normally passes, detecting the erasing function of each EMMC chip in the EMMC array, and when the erasing function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal erasing function;
when the erasing function of the EMMC array is detected to be normal, detecting the writing function of each EMMC chip in the EMMC array, and when the writing function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal writing function;
and when the read function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal read function.
Preferably, the monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the location of the EMMC chip with the initialization fault when any one of the EMMC chips with the initialization fault is monitored, includes:
sequentially sending a reset command and a working voltage setting command to each EMMC chip in the EMMC array;
monitoring the feedback state of each EMMC chip to the set working voltage command;
when the fact that the preset state bit in the feedback state of any one EMMC chip to the set working voltage command is not the first preset value is monitored, the EMMC chip with the preset state bit not being the first preset value in the feedback state is judged to be the EMMC chip with the initialization fault;
and outputting the position of the EMMC chip with the initialization fault.
Preferably, the method further comprises:
and prompting the EMMC array to initialize to normally pass when the preset state bits in the feedback states of all the EMMC chips in the EMMC array to the set working voltage command are the first preset value.
Preferably, the detecting the erase function of each of the EMMC chips in the EMMC array, and outputting the location of the EMMC chip with the abnormal erase function when detecting that the erase function of any one of the EMMC chips is abnormal, includes:
sending an erasing configuration command to each EMMC chip in the EMMC array, and configuring an erasing working mode of the EMMC array;
erasing all data of each EMMC chip;
respectively detecting the value of a preset bit of a data line of each EMMC chip;
when the value of the preset bit of the data line of any one EMMC chip is not a second preset value within preset time, judging the EMMC chip with the preset bit value of the data line not being the second preset value as an EMMC chip with abnormal erasing function;
and outputting the position of the EMMC chip with abnormal erasing function.
Preferably, the method further comprises:
and prompting that the erasing function of the EMMC array is normal when the values of the preset bits of the data lines of all the EMMC chips in the EMMC array are the second preset value within preset time.
Preferably, the detecting the write function of each of the EMMC chips in the EMMC array, and outputting the location of the EMMC chip with the abnormal write function when detecting that the write function of any one of the EMMC chips is abnormal, includes:
sending a write configuration command to each EMMC chip in the EMMC array, and configuring a write working mode of the EMMC array;
respectively generating different linear data according to the capacity of each EMMC chip, and sub-packaging and writing the different linear data into the corresponding EMMC chips;
when an EMMC chip which does not detect that the value of the preset bit of the data line is a third preset value within preset time after each packet of linear data is written exists, judging the EMMC chip which does not detect that the value of the preset bit of the data line is the third preset value as an EMMC chip with abnormal writing function;
and outputting the position of the EMMC chip with the abnormal writing function.
Preferably, the method further comprises:
and when all the EMMC chips in the EMMC array detect that the value of the preset bit of the data line is the third preset value within the preset time after each packet of linear data is written, prompting that the writing function of the EMMC array is normal.
Preferably, the detecting the read function of each of the EMMC chips in the EMMC array, and outputting the location of the EMMC chip with the abnormal read function when the read function of any one of the EMMC chips is detected to be abnormal, includes:
sending a read configuration command to each EMMC chip in the EMMC array;
respectively reading the full-capacity data of each EMMC chip in a sub-package mode;
respectively judging whether the value of the preset bit of the data line is detected to be a fourth preset value within preset time after each EMMC chip reads each packet of data;
if so, performing data verification on each read data packet, and judging that the EMMC chip corresponding to the data packet with the data verification error is an EMMC chip with an abnormal reading function when the data verification is wrong;
if not, determining that the corresponding EMMC chip is the EMMC chip with abnormal reading function;
and outputting the EMMC chip with the abnormal reading function.
Preferably, the method further comprises:
and in a preset time, when the feedback values of all the EMMC chips in the EMMC array to the write-in configuration command are the fourth preset value and all the read data pass data verification, prompting that the read function of the EMMC array is normal.
A fault location system for an EMMC array, comprising:
the initialization monitoring unit is used for monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the position of the EMMC chip with the initialization fault when the initialization fault of any one EMMC chip is monitored;
the erasing function detection unit is used for detecting the erasing function of each EMMC chip in the EMMC array after the initialization of the EMMC array normally passes, and outputting the position of the EMMC chip with the abnormal erasing function when the erasing function of any one EMMC chip is detected to be abnormal;
the write-in function detection unit is used for detecting the write-in function of each EMMC chip in the EMMC array after the erase function of the EMMC array is detected to be normal, and outputting the position of the EMMC chip with the abnormal write-in function when the write-in function of any EMMC chip is detected to be abnormal;
and the read function detection unit is used for detecting the read function of each EMMC chip in the EMMC array after the write function of the EMMC array is detected to be normal, and outputting the position of the EMMC chip with the abnormal read function when the read function of any EMMC chip is detected to be abnormal.
Compared with the prior art, the invention has the following beneficial effects:
the fault positioning method of the EMMC array not only can monitor the initialization state of each EMMC chip in the EMMC array, output the position of the EMMC chip with the initialization fault when any one EMMC chip with the initialization fault is monitored, but also can detect the erasing function, the writing function and the reading function of the EMMC array, and output the position of the abnormal EMMC chip when the abnormal EMMC chip is detected. The problem of can only judge the fault condition of EMMC array through monitoring initialization state among the prior art is solved, can all-round carry out fault detection and fault location to the EMMC array.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a fault location method of an EMMC array according to an embodiment of the present invention;
fig. 2 is a flowchart of another fault location method for an EMMC array according to an embodiment of the present disclosure;
fig. 3 is a flowchart of another fault location method for an EMMC array according to an embodiment of the present disclosure;
fig. 4 is a flowchart of a fault location method for an EMMC array according to another embodiment of the present disclosure;
fig. 5 is a flowchart of a method for locating a fault in an EMMC array according to another embodiment of the present disclosure;
fig. 6 is a flowchart of another fault location method for an EMMC array according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a fault location system of an EMMC array according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a fault positioning method of an EMMC array, which can not only monitor and position faults in the process of initializing the EMMC array, but also detect and position faults of an erasing function, a writing function and a reading function of each EMMC chip in the EMMC array, solves the problem that the fault state of the EMMC array can only be judged by monitoring the initialization state in the prior art, and can carry out fault detection and fault positioning on the EMMC array in an all-around way.
Referring to fig. 1, fig. 1 is a schematic diagram of an embodiment of a fault location method according to an embodiment of the present invention, as shown in the figure, specifically:
s101: monitoring the initialization state of each EMMC chip in the EMMC array; if the initialization is normally executed S102, if the initialization is wrong, S105 is executed;
s102: detecting the erasing function of each EMMC chip in the EMMC array; if the erase function is executed normally S103, if the erase function is executed incorrectly S105;
s103: detecting the write-in function of each EMMC chip in the EMMC array, and executing S104 if the write-in function is normal, and executing S105 if the write-in function is wrong;
s104: detecting the read function of each EMMC chip in the EMMC array, if the read function is normal, the EMMC array is normal and has no fault, and if the read function is wrong, executing S105:
s105: the location of the failed EMMC chip is output.
Fig. 2 is a flowchart illustrating a fault location method for implementing the EMMC array of the present disclosure, where the fault location method specifically includes the following steps:
s201: monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the position of the EMMC chip with the initialization fault when any one EMMC chip with the initialization fault is monitored;
after the system is powered on, the EMMC array needs to be initialized first, whether a fault occurs in the initialization process of the EMMC array is monitored, if the EMMC array cannot normally work, and if any EMMC chip has an initialization fault, the position of the EMMC chip with the initialization fault needs to be output, so that a worker can conveniently process the fault.
The location of an output failed EMMC chip, as referred to herein, and of all output abnormal EMMC chips referred to below, the location of an EMMC chip refers specifically to location data that can indicate the location of the failed or abnormal EMMC chip in the EMMC array, such as: identification or numbering of the EMMC chip, etc.
S202: when the initialization of the EMMC array normally passes, detecting the erasing function of each EMMC chip in the EMMC array, and when the erasing function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal erasing function;
the erase function refers to the ability to erase all data in the EMMC chip.
S203: when the erasing function of the EMMC array is detected to be normal, detecting the writing function of each EMMC chip in the EMMC array, and when the writing function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal writing function;
s204: and when the read function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal read function.
If the initialization, erase function detection, write function detection, and read function detection all pass normally, then the EMMC array is faultless.
The fault location method for the EMMC array provided by this embodiment can not only monitor the initialization state of each EMMC chip in the EMMC array, output the position of the EMMC chip with the initialization fault when any one of the EMMC chips is monitored for the initialization fault, but also detect the erase function, the write-in function, and the read function of the EMMC array, and output the position of the abnormal EMMC chip when the abnormal EMMC chip is detected. The problem of can only judge the fault condition of EMMC array through monitoring initialization state among the prior art is solved, can all-round carry out fault detection and fault location to the EMMC array.
Specific implementations of the initialization, erase, write, and read functions of the EMMC array in the above embodiments are described below.
Referring to fig. 3, fig. 3 is a flowchart of a method for monitoring initialization of an EMMC array according to the foregoing embodiment, including:
s301: sequentially sending a reset command and a working voltage setting command to each EMMC chip in the EMMC array;
s302: monitoring the feedback state of each EMMC chip to the set working voltage command;
s303: when the fact that the preset state bit in the feedback state of any one EMMC chip to the set working voltage command is not the first preset value is monitored, the EMMC chip with the preset state bit not being the first preset value in the feedback state is judged to be the EMMC chip with the initialization fault;
preferably, the preset state bit is a busy state bit in a feedback state, the first preset value is 1, and when the busy state bit is 1, it indicates that the setting of the working voltage is completed.
And performing AND operation on the values of the busy state bits of all EMMC chips in the EMMC array, if the busy state bits of all the EMMC chips are all 1, enabling the initialization of the EMMC array to normally pass, and if the value of the busy state bit of any one or more EMMC chips is not 1, judging that the EMMC chip with the busy state bit not being 1 is the EMMC chip with the initialization fault.
It should be noted that the first preset value is a value preset by the system and indicating that the setting of the operating voltage is completed, and a user may set the first preset value to an arbitrary value.
S304: outputting the position of the EMMC chip with the initialization fault;
s305: and prompting the EMMC array to initialize to normally pass when the preset state bits in the feedback states of all the EMMC chips in the EMMC array to the set working voltage command are the first preset value.
Referring to fig. 4, fig. 4 is a flowchart illustrating a method for detecting and locating a failure of an erase function of an EMMC array according to an embodiment of the present invention, which includes:
s401: sending an erasing configuration command to each EMMC chip in the EMMC array, and configuring an erasing working mode of the EMMC array;
s402: erasing all data of each EMMC chip;
s403: respectively detecting the value of a preset bit of a data line of each EMMC chip;
s404: when the value of the preset bit of the data line of any one EMMC chip is not a second preset value within preset time, judging the EMMC chip with the preset bit value of the data line not being the second preset value as an EMMC chip with abnormal erasing function;
s405: outputting the position of the EMMC chip with abnormal erasing function;
s406: and prompting that the erasing function of the EMMC array is normal when the values of the preset bits of the data lines of all the EMMC chips in the EMMC array are the second preset value within preset time.
It should be noted that the preset time and the second preset value are calibration values preset by the system, and the values of the first preset value and the second preset value may be the same or different.
When the preset bit of the data line is a 0bit of the data line, the preset time is 2s, and the second preset value is 0, a specific implementation scenario of the embodiment corresponding to fig. 4 is as follows:
when the initialization of the EMMC array is normally passed, sending an erasing configuration command to each EMMC chip, configuring an erasing working mode of the EMMC array, erasing all data of each EMMC chip, detecting an erasing working state fed back by a 0bit of a data line of each EMMC chip, and when the value of the 0bit of the data line is 1, indicating that the erasing is still performed and the erasing is not finished; when the value of 0bit of the data line is 0, indicating that the erasing is normally finished; and if the 0bit value of the data line is not fed back within 2s after the erasing is finished, judging that the corresponding EMMC chip is the EMMC chip with the abnormal erasing function, and outputting the position of the EMMC chip with the abnormal erasing function.
Referring to fig. 5, fig. 5 is a flowchart illustrating a method for performing fault detection and location on a write function of an EMMC array according to the present invention, which specifically includes:
s501: sending a write configuration command to each EMMC chip in the EMMC array, and configuring a write working mode of the EMMC array;
s502: respectively generating different linear data according to the capacity of each EMMC chip, and sub-packaging and writing the different linear data into the corresponding EMMC chips;
s503: when an EMMC chip which does not detect that the value of the preset bit of the data line is a third preset value within preset time after each packet of linear data is written exists, judging the EMMC chip which does not detect that the value of the preset bit of the data line is the third preset value as an EMMC chip with abnormal writing function;
s504: outputting the position of the EMMC chip with the abnormal writing function;
s505: and when all the EMMC chips in the EMMC array detect that the value of the preset bit of the data line is the third preset value within the preset time after each packet of linear data is written, prompting that the writing function of the EMMC array is normal.
When the preset bit of the data line is a 0bit of the data line, the preset time is 2s, and the third preset value is 0, a specific implementation scenario of the embodiment corresponding to fig. 5 is as follows:
if the erasure test normally passes, sending a write configuration command word to each EMMC chip in the EMMC array, configuring the EMMC array as a write working mode, generating different linear data according to the capacity of each EMMC chip, writing the different linear data into the corresponding EMMC chip in a sub-packet manner, fully writing the EMMC chip, monitoring the write working state fed back by 0bit of the data line after writing a packet of linear data each time, and indicating that the write is not finished when the feedback is 1; when the feedback is 0, it means that the writing is normally ended. And if the single-packet writing time of the EMMC chip exceeds 2s and 0 is not fed back, determining that the writing time of the EMMC chip is overtime, determining that the EMMC chip is a fault EMMC chip, and outputting the position of the fault EMMC.
Referring to fig. 6, fig. 6 is a flowchart illustrating a method for detecting and locating a failure of a read function of an EMMC array according to the present invention, which specifically includes:
s601: sending a read configuration command to each EMMC chip in the EMMC array;
s602: respectively reading the full-capacity data of each EMMC chip in a sub-package mode;
s603: respectively judging whether the value of the preset bit of the data line is detected to be a fourth preset value within preset time after each EMMC chip reads each packet of data, if so, executing S604, and if not, executing S605;
s604: performing data verification on each read packet of data, judging whether the data verification on each read packet of data passes, if so, executing S606, and if not, executing S605;
s605: judging that the corresponding EMMC chip is an EMMC chip with abnormal reading function;
s606: and outputting the EMMC chip with the abnormal reading function.
When the preset bit of the data line is a 0bit of the data line, the preset time is 2s, and the fourth preset value is 0, a specific implementation scenario of the embodiment corresponding to fig. 5 is as follows:
and if the write test is passed normally, sending a read configuration command to each EMMC chip in the EMMC array, and separately and sub-packaging and reading the full-capacity data of each EMMC chip. If the feedback value of 0bit of the data line received in 2s is 0, performing data verification on the data of the packet, and if the data verification is wrong, determining that the reading function of the EMMC chip corresponding to the data of the packet is abnormal; if the feedback value of 0bit of the data line is not received within 2s and is 0, the reading of the EMMC chip corresponding to the data packet is overtime, and the reading function is abnormal; when the feedback values of all the EMMC chips in the EMMC array are 0 within 2s and all the read data pass the data verification, the reading function of the EMMC array is normal.
It should be noted that the first preset value, the second preset value, the third preset value, and the fourth preset value are preset calibration values of the system, and the first preset value, the second preset value, the third preset value, and the fourth preset value may be the same or different.
Based on the fault location method of the EMMC array disclosed in the foregoing embodiment, this embodiment correspondingly discloses a fault location system of the EMMC array, please refer to fig. 7, where the fault location system specifically includes:
the initialization monitoring unit 101 is used for monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the position of the EMMC chip with the initialization fault when any one EMMC chip with the initialization fault is monitored;
an erasing function detecting unit 102, configured to detect an erasing function of each EMMC chip in the EMMC array after the EMMC array is initialized to normally pass through, and output a position of an EMMC chip with an abnormal erasing function when the erasing function of any one of the EMMC chips is detected to be abnormal;
a write function detection unit 103, configured to detect a write function of each EMMC chip in the EMMC array after the EMMC array erase function is detected to be normal, and output a location of the EMMC chip with the abnormal write function when the write function of any one of the EMMC chips is detected to be abnormal;
and a read function detection unit 104, configured to detect a read function of each EMMC chip in the EMMC array after the write function of the EMMC array is detected to be normal, and output a position of an EMMC chip with an abnormal read function when the read function of any one of the EMMC chips is detected to be abnormal.
The fault location system of the EMMC array disclosed in this embodiment carries out all-around fault detection and location on the EMMC array through the initialization monitoring unit, the erasing function detection unit, the writing function detection unit and the reading function detection unit, which not only can realize monitoring the initialization state of each EMMC chip in the EMMC array, when any one of the EMMC chips is monitored for an initialization fault, the position of the EMMC chip with the initialization fault is output, but also can realize detection of the erasing function, the writing function and the reading function of the EMMC array, and when an abnormal EMMC chip is detected, the position of the abnormal EMMC chip is output. The problem of can only judge the fault condition of EMMC array through monitoring initialization state among the prior art is solved, can all-round carry out fault detection and fault location to the EMMC array.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A fault location method for an EMMC array, comprising:
monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the position of the EMMC chip with the initialization fault when any one EMMC chip with the initialization fault is monitored;
when the initialization of the EMMC array normally passes, detecting the erasing function of each EMMC chip in the EMMC array, and when the erasing function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal erasing function;
when the erasing function of the EMMC array is detected to be normal, sending a write configuration command to each EMMC chip in the EMMC array, and configuring a write working mode of the EMMC array;
respectively generating different linear data according to the capacity of each EMMC chip, and sub-packaging and writing the different linear data into the corresponding EMMC chips;
when an EMMC chip which does not detect that the value of the preset bit of the data line is a third preset value within preset time after each packet of linear data is written exists, judging the EMMC chip which does not detect that the value of the preset bit of the data line is the third preset value as an EMMC chip with abnormal writing function;
outputting the position of the EMMC chip with the abnormal writing function;
and when the read function of any one EMMC chip is detected to be abnormal, outputting the position of the EMMC chip with the abnormal read function.
2. The method of claim 1, wherein monitoring the initialization status of each EMMC chip in the EMMC array, and outputting the location of an initialization fault EMMC chip when any one EMMC chip is monitored for an initialization fault, comprises:
sequentially sending a reset command and a working voltage setting command to each EMMC chip in the EMMC array;
monitoring the feedback state of each EMMC chip to the set working voltage command;
when the fact that the preset state bit in the feedback state of any one EMMC chip to the set working voltage command is not the first preset value is monitored, the EMMC chip with the preset state bit not being the first preset value in the feedback state is judged to be the EMMC chip with the initialization fault;
and outputting the position of the EMMC chip with the initialization fault.
3. The method of claim 2, further comprising:
and prompting the EMMC array to initialize to normally pass when the preset state bits in the feedback states of all the EMMC chips in the EMMC array to the set working voltage command are the first preset value.
4. The method of claim 1, wherein the detecting an erase function of each of the EMMC chips in the EMMC array, and when an erase function abnormality of any one of the EMMC chips is detected, outputting a location of the EMMC chip with the abnormal erase function comprises:
sending an erasing configuration command to each EMMC chip in the EMMC array, and configuring an erasing working mode of the EMMC array;
erasing all data of each EMMC chip;
respectively detecting the value of a preset bit of a data line of each EMMC chip;
when the value of the preset bit of the data line of any one EMMC chip is not a second preset value within preset time, judging the EMMC chip with the preset bit value of the data line not being the second preset value as an EMMC chip with abnormal erasing function;
and outputting the position of the EMMC chip with abnormal erasing function.
5. The method of claim 4, further comprising:
and prompting that the erasing function of the EMMC array is normal when the values of the preset bits of the data lines of all the EMMC chips in the EMMC array are the second preset value within preset time.
6. The method of claim 1, further comprising:
and when all the EMMC chips in the EMMC array detect that the value of the preset bit of the data line is the third preset value within the preset time after each packet of linear data is written, prompting that the writing function of the EMMC array is normal.
7. The method of claim 1, wherein the detecting the read function of each of the EMMC chips in the EMMC array and outputting the location of the EMMC chip with the read function abnormal when the read function abnormal of any one of the EMMC chips is detected comprises:
sending a read configuration command to each EMMC chip in the EMMC array;
respectively reading the full-capacity data of each EMMC chip in a sub-package mode;
respectively judging whether the value of the preset bit of the data line is detected to be a fourth preset value within preset time after each EMMC chip reads each packet of data;
if so, performing data verification on each read data packet, and judging that the EMMC chip corresponding to the data packet with the data verification error is an EMMC chip with an abnormal reading function when the data verification is wrong;
if not, determining that the corresponding EMMC chip is the EMMC chip with abnormal reading function;
and outputting the EMMC chip with the abnormal reading function.
8. The method of claim 7, further comprising:
and in a preset time, when the feedback values of all the EMMC chips in the EMMC array to the write-in configuration command are the fourth preset value and all the read data pass data verification, prompting that the read function of the EMMC array is normal.
9. A fault location system for an EMMC array, comprising:
the initialization monitoring unit is used for monitoring the initialization state of each EMMC chip in the EMMC array, and outputting the position of the EMMC chip with the initialization fault when the initialization fault of any one EMMC chip is monitored;
the erasing function detection unit is used for detecting the erasing function of each EMMC chip in the EMMC array after the initialization of the EMMC array normally passes, and outputting the position of the EMMC chip with the abnormal erasing function when the erasing function of any one EMMC chip is detected to be abnormal;
the write-in function detection unit is used for sending a write-in configuration command to each EMMC chip in the EMMC array and configuring a write-in working mode of the EMMC array after the erase function of the EMMC array is detected normally; respectively generating different linear data according to the capacity of each EMMC chip, and sub-packaging and writing the different linear data into the corresponding EMMC chips; when an EMMC chip which does not detect that the value of the preset bit of the data line is a third preset value within preset time after each packet of linear data is written exists, judging the EMMC chip which does not detect that the value of the preset bit of the data line is the third preset value as an EMMC chip with abnormal writing function; outputting the position of the EMMC chip with the abnormal writing function;
and the read function detection unit is used for detecting the read function of each EMMC chip in the EMMC array after the write function of the EMMC array is detected to be normal, and outputting the position of the EMMC chip with the abnormal read function when the read function of any EMMC chip is detected to be abnormal.
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| CN110289039B (en) * | 2018-03-19 | 2021-07-27 | 北京兆易创新科技股份有限公司 | Debugging method and device of eMMC |
| CN109271276B (en) * | 2018-12-18 | 2019-04-05 | 展讯通信（上海）有限公司 | Chip positioning device and method |
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| CN113936730B (en) * | 2020-07-13 | 2022-10-14 | 长鑫存储技术有限公司 | Test method, test system and test equipment for semiconductor chip |
| CN111736780B (en) | 2020-08-07 | 2021-02-02 | 苏州浪潮智能科技有限公司 | Solid state disk erasing method, device, equipment and storage medium |
| CN113628674B (en) * | 2021-07-09 | 2023-08-18 | 杭州电子科技大学 | Method for positioning fault eMMC in RAIM framework SSD |
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