CN107611033B - Negative capacitance molybdenum disulfide transistor based on ferroelectric gate dielectric and preparation method thereof - Google Patents
Negative capacitance molybdenum disulfide transistor based on ferroelectric gate dielectric and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a negative capacitance molybdenum disulfide transistor based on a ferroelectric gate dielectric and a preparation method thereof, which comprises the step of preparing a negative capacitance molybdenum disulfide transistor on SiO2MoS growth on the surface of the substrate2A film; in MoS2A first High-K layer, a first TiN layer, a ferroelectric film layer, a second TiN layer and a second High-K layer are sequentially grown on the surface of the film to serve as gate dielectric layers; growing a third TiN layer and a Ti/Au metal layer on the gate dielectric layer to be used as a gate electrode; in MoS2Two Al metals are grown on the thin film layer and used as a source electrode and a drain electrode. The invention wraps the ferroelectric gate dielectric film layer with TiN layer, and the metal TiN rebalances the additional electric field generated by the polarization reversal of the ferroelectric gate dielectric film and uniformly applies the rebalanced additional electric field to MoS2On the thin film layer, avoiding each point MoS in the channel2The conditions of slow starting, large subthreshold value and the like of the device caused by different inversion conditions are avoided, and meanwhile, the condition that point breakdown is easy to occur when the field intensity of the High-K layer at the point is large is also avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a negative capacitance molybdenum disulfide transistor based on a ferroelectric gate dielectric and a preparation method thereof.
Background
Molybdenum disulfide (MoS)2) The film is used as a novel two-dimensional material, is similar to graphene in structure and performance, and has a layered structure and high carrier mobility. However, compared to the zero band gap of graphene, MoS2The band gap of the thin film varies with the number of layers. Bulk crystalline MoS2The band gap of (A) is 1.20eV, and the electron transition mode of the band gap is indirect transition; when the thickness is a single layer, MoS2The band gap of the crystal can reach 1.82eV, and the electronic transition mode of the crystal is converted intoA direct transition. Thus, MoS2The unique structure, excellent physical properties and adjustable energy band gap of the film enable the film to have greater application potential than graphene in the field of two-dimensional semiconductor devices, the characteristic dimension of a channel is expected to reach 2nm, the process of Moore's law is expected to be continued, and the performance of an integrated circuit is further improved. However, the integration of devices with too high density will bring larger power consumption per unit area, the heat dissipation performance of the chip will become difficult to guarantee, and the higher temperature will also hinder the increase of the CPU frequency. In a traditional CMOS integrated circuit, a large part of working heat comes from the on-off state switching process of devices, the switching process of all MOS devices is a gradual transition process, and under the same working frequency, the faster the switching speed is, the less the wasted power consumption is. An important parameter reflecting the transition speed is the subthreshold slope, and the smaller the subthreshold slope is, the smaller the power consumption of the device is, and the smaller the heating value of the corresponding integrated circuit is. The conventional MOSFET is limited by thermodynamics, and the subthreshold slope of the MOSFET cannot be less than 60mV/dec under the normal-temperature working state. The threshold value of the sub-threshold slope may be expressed as:
wherein only have
Is a variable, which is normally a positive value, and thus SS>60 mV/dec. If it is desired to make SS<60mV/dec, if necessary
Wherein C issIs a depletion layer capacitance, CitIs a surface state capacitance, CoxIs the gate oxide capacitance, and these three capacitances are generally positive values. The ferroelectric material is used as the gate oxide layer, so that C can be used during switching of the deviceox<0, which is mainly due to the fact that the charge center of the ferroelectric material moves along with the change of the external electric field, thereby causing the electric polarization strength to change and adding an additional electric field to the ferroelectric material at the moment of opening the channel. Behave as a gateThe capacitance is negative, and in formula (1), SS may be less than the limit of 60 mV/dec.
In addition to this, the MoS is caused by a sudden transition of the polarization of the ferroelectric gate oxide2When the threshold voltage of the field effect transistor is lowered, the operating voltage of the corresponding integrated circuit is lowered, and the power consumption of the integrated circuit is estimated according to the relation P-V2(where P is circuit power consumption, V is operating voltage, and R is integrated circuit resistance), which also further reduces MoS2The power consumption of the field effect transistor reduces the heat productivity, and the lower environmental temperature is beneficial to improving the switching speed of the device.
Conventional MOS structure MOS2The subthreshold slope of the transistor is larger than 60mV/dec, and the power consumption is large. If the high-density integrated circuit is miniaturized and prepared, particularly the integrated circuit with the characteristic size smaller than 5nm, the heat productivity of the high-density integrated circuit cannot be ignored, and under higher temperature, a carrier is seriously scattered by phonons, so that the operation speed of a chip is limited, the upper limit of the working frequency of the chip is reduced, the performance of the chip is reduced, and compared with devices such as FinFETs (Fin field effect transistors) with the same size, the high-density integrated circuit has difficulty in representing electrical advantages. In addition, the conventional planar gate MoS is limited by short channel effects2The subthreshold slope of the field effect transistor increases as the channel width becomes shorter, i.e., the gating capability deteriorates as the channel becomes shorter.
Accordingly, the prior art is deficient and needs improvement.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the negative capacitance molybdenum disulfide transistor based on the ferroelectric gate medium and the preparation method thereof are provided, wherein the negative capacitance molybdenum disulfide transistor can realize that the subthreshold slope breaks through the thermodynamic limit, the starting speed is high, and the power consumption of the device is low.
The technical scheme of the invention is as follows: a preparation method of a negative capacitance molybdenum disulfide transistor based on a ferroelectric gate dielectric is disclosed, and S1: in SiO2Growing a two-dimensional material film on the surface of the substrate; s2: photoetching and defining an active area of the two-dimensional material film, and etching the two-dimensional material film in other areas; s3, growing a first High-K layer on the surface of the two-dimensional material film; s4: growing a first High-K layer on the surface of the first High-K layerA TiN layer; s5: growing a ferroelectric gate dielectric film layer on the surface of the first TiN layer; s6: growing a second TiN layer on the surface of the ferroelectric gate dielectric film layer; s7: growing a second High-K layer on the surface of the second TiN layer; s8: growing a third TiN layer on the surface of the second High-K layer; s9: photoetching is carried out, a gate metal area is defined, and a gate electrode is stripped; s10: photoetching protection is carried out on the metal grid, the dielectric layer in the non-grid region is etched, and a source-drain contact region of the two-dimensional material film layer is leaked out; s11: and defining a source and drain electrode area of the device by photoetching to form a source electrode and a drain electrode.
The preparation method is applied to the technical scheme, and the two-dimensional material film layer is made of MoS2A thin film layer, or a tungsten disulfide thin film layer, or a black phosphorus thin film layer.
Applied to each technical scheme, in the preparation method, the MoS2The thin film layer is a single-layer MoS2Thin film, or dual layer MoS2Thin film, or three-layer MoS2A film.
The ferroelectric grid dielectric thin film layer is a barium titanate ferroelectric thin film layer, or a PZT ferroelectric thin film layer, a perovskite ferroelectric material thin film layer, or an organic ferroelectric material thin film layer.
The preparation method is applied to each technical scheme, and the thicknesses of the first High-K layer, the second High-K layer, the first TiN layer, the second TiN layer and the third TiN layer are all 5 nm; and the first High-K layer and the second High-K layer are both Al2O3And (3) a layer.
The preparation method is applied to each technical scheme, and the thickness of the ferroelectric gate dielectric thin film layer is preferably 20 nm.
In the preparation method, in step S9, a Ti/Au metal layer is grown on the surface of the third TiN layer by electron beam evaporation, and the gate electrode is stripped by lift-off process.
In the preparation method, in step S11, electron beam evaporation is used to prepare source and drain metals, and a lift-off process is used to form a source electrode and a drain electrode.
In the preparation method, in step S11, the prepared source-drain metal is Al metal, and the thickness is preferably 50 nm.
The preparation method is applied to each technical scheme, and in the preparation method, the ferroelectric gate dielectric-based negative capacitance molybdenum disulfide transistor and SiO prepared by adopting any one of the preparation methods2Substrate of SiO2The two-dimensional material thin film layer grows on the surface of the substrate, and the first High-K layer, the first TiN layer, the ferroelectric gate dielectric thin film layer, the second TiN layer, the second High-K layer, the third TiN layer, the gate electrode, the source electrode and the drain electrode sequentially grow on the surface of the two-dimensional material thin film layer.
By adopting the scheme, the invention has the following advantages:
1) steep subthreshold slope (less than 60 mV/dec);
2) a small threshold voltage (Vth is expected to be about 0.2V);
3) less power consumption and less heat generation;
4) less gate leakage.
5) The preparation method provided by the invention has the advantages that the process flow can be compatible with a silicon process, and the large-scale circuit integration is easy.
6) The transistor provided by the invention has the advantages of high turn-on speed, low power consumption and suitability for the preparation of nanoscale devices, and the expected minimum trench width can reach 2 nm.
7) In the invention, the ferroelectric gate dielectric film layer is wrapped by the first TiN layer and the second TiN layer, so that the difference of additional field intensity of each point caused by different ferroelectric domain polarization conditions in the dielectric layer is avoided. Because TiN is metal, the additional electric field generated by the polarization reversal of the ferroelectric film can be rebalanced and uniformly applied to MoS2On the channel, so that MoS2The channel obtains uniform electric field intensity, and each point MoS in the channel is avoided2The conditions of slow device opening, large subthreshold value and the like caused by different inversion conditions. Meanwhile, the situation that point breakdown is easy to occur under the condition that the field intensity of the High-K gate dielectric at a certain point is larger is also avoided.
Drawings
FIG. 1 is a schematic structural diagram of a negative capacitance molybdenum disulfide transistor according to the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
The embodiment provides a preparation method of a negative capacitance molybdenum disulfide transistor based on a ferroelectric gate dielectric, which comprises the following steps of firstly, preparing SiO2Cleaning the substrate with SiO2The specific cleaning process of the substrate is as follows:
1) carrying out ultrasonic cleaning on acetone, wherein the ultrasonic frequency is 45-50 KHz;
2) ultrasonically cleaning the ethanol, wherein the ultrasonic frequency is 50-55 KHz;
3) washing in a deionized water beaker;
4) in concentrated sulfuric acid: hydrogen peroxide is 4: 1 (volume ratio) in the mixed solution, boiling for 15 minutes at 90 ℃, and washing with deionized water. The concentration of the sulfuric acid is 98 percent, and the concentration of the hydrogen peroxide is 40 percent.
The cleaned material is put into CVD equipment to grow molybdenum sulfide material, and the CVD method refers to a process of introducing vapor of gaseous reactants or liquid reactants containing film-forming elements and other gases required by reaction into a reaction chamber to generate chemical reaction on the surface of the substrate to generate a film.
The experimental conditions of the process are as follows: with sulfur powder and MoO3(99.9%, analytical purity) as a sulfur source and a molybdenum source, high purity argon as a carrier gas, in SiO2Preparation of MoS by upward deposition2A film. Wherein the growth temperature is 700 ℃, the mass of the sulfur source is 0.8g, the mass of the molybdenum source is 0.04g, and the pressure is normal pressure. The quality of the sulfur source and the molybdenum source can be adjusted according to the number of the layers of the molybdenum sulfide which needs to be grown. The sulfur powder and MoO3When the mass ratio of (1) to (3) is 50, the obtained MoS2The number of layers of the film is a single layer; the sulfur powder and MoO3In a mass ratio of 30:1, the obtained MoS2The number of layers of the film is two; the sulfur powder and MoO3In a mass ratio of 15-20: 1, preferably 20:1, and the obtained MoS2The number of layers of the film is more than or equal to three.
Then, a device process can be performed, wherein the device process comprises the following steps:
first, define MoS lithographically2An active region, and a MoS of the other region by oxygen plasma2And etching away. Second, in MoS2And a gate dielectric layer grows on the surface of the film, wherein the gate dielectric layer consists of a plurality of dielectric layers and comprises a first High-K layer, a first TiN layer, a ferroelectric film layer, a second TiN layer and a second High-K layer which are sequentially stacked from bottom to top. In growth, i.e. first, at MoS using an Atomic Layer Deposition (ALD) method2A first High-K layer with the thickness of 5nm grows on the surface of the thin film layer; then, a first TiN layer with the thickness of 5nm is grown on the surface of the first High-K layer by utilizing a magnetron sputtering or atomic layer deposition method; then, a ferroelectric gate dielectric film layer with the thickness of 20nm is grown on the surface of the first TiN layer by utilizing magnetron sputtering or molecular beam epitaxy; then, a second TiN layer with the thickness of 5nm is grown on the surface of the ferroelectric gate dielectric thin film layer by utilizing a magnetron sputtering or atomic layer deposition method; then, growing a second High-K layer with the thickness of 5nm on the surface of the second TiN layer by utilizing an atomic layer deposition method; and finally, growing a third TiN layer with the thickness of 5nm on the surface of the second High-K layer by utilizing a magnetron sputtering or atomic layer deposition method. Wherein the High-K layer is Al2O3(ii) a The ferroelectric gate dielectric thin film layer can be a barium titanate or PZT ferroelectric thin film layer.
And secondly, photoetching the device, defining a gate metal area, growing a Ti/Au metal layer on the surface of a gate dielectric layer by using electron beam evaporation, and stripping off the metal gate electrode by a lift-off process to form the gate of the molybdenum disulfide transistor, wherein the third TiN layer and the Ti/Au metal layer are combined into the gate electrode.
And secondly, carrying out photoetching protection on the metal gate, etching the dielectric layer in the non-gate region, and leaking a source-drain contact region of the two-dimensional material film, wherein the photoetching protection is to etch and remove redundant parts of the third TiN layer, the second High-K layer, the second TiN layer, the ferroelectric gate dielectric film layer, the first TiN layer and the first High-K layer from top to bottom in sequence. The removing method specifically comprises the following steps: ammonia water was used: hydrogen peroxide: deionized water 1: 1: mixing the solution at a volume ratio of 5, and removing the TiN layer under the water bath condition of 50 ℃; the use of phosphoric acid: deionized water: acetic acid: concentrated nitric acid 16: 2: 1: removing a High-K layer from the mixed solution with the volume ratio of 1; and removing the ferroelectric gate dielectric thin film layer by using an RIE etching system.
Finally, defining a source drain contact region of the device by photoetching, and preparing source drain metal by electron beam evaporation, specifically, MoS2And growing an Al metal electrode with the thickness of 50nm on the thin film layer, and forming a source electrode and a drain electrode through a lift-off process to respectively form the source electrode and the drain electrode of the molybdenum disulfide transistor. The structure of the device is schematically shown in figure 1.
In the negative capacitance molybdenum disulfide transistor based on the ferroelectric gate dielectric, the ferroelectric gate dielectric material is used as the gate oxide layer, and the ferroelectric gate dielectric thin film layer is wrapped by the TiN layer, so that the difference of additional field intensity at each point caused by different ferroelectric domain polarization conditions in the gate dielectric layer is avoided. Wherein, because TiN is metal, the additional electric field generated by the polarization reversal of the ferroelectric gate dielectric thin film layer can be rebalanced and uniformly applied to MoS2On the thin film layer channel, so that MoS2The thin film layer channel obtains uniform electric field intensity, and each point MoS in the channel is avoided2The conditions of slow device opening, large subthreshold value and the like caused by different inversion conditions are avoided, the condition that point breakdown is easy to occur under the condition that the field intensity of a High-K layer at a certain point is large is avoided, and the subthreshold slope can break through the thermodynamic limit (<60mV/dec), high starting speed, low device power consumption, suitability for preparation of nanoscale devices, and estimated minimum trench width of 2nm and MoS2And large-scale integration of devices provides guarantee. Meanwhile, the process flow provided by the embodiment can be compatible with a silicon process, and is easy for large-scale circuit integration.
It is worth noting that MoS can also be used in the present invention2Modified to other two-dimensional materials, e.g. tungsten disulphide (WS)2) Black phosphorus, etc., or varying MoS2In the growth mode of (i) MoS2The material is not formed by growth but by material transfer; in addition, the ferroelectric gate dielectric material, i.e. the ferroelectric gate dielectric thin film layer, can adopt all other materials with ferroelectric properties, such as other perovskite ferroelectric materials, organic ferroelectric materials, and the like.
The invention innovatively provides a secondary gate capacitor MoS based on a ferroelectric material2Transistor capable of achieving sub-threshold slope breaking thermodynamic limit<60mV/dec), device power consumption is reduced, and meanwhile, guarantee is provided for large-scale integration of the MoS2 device.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A preparation method of a negative capacitance molybdenum disulfide transistor based on a ferroelectric gate dielectric is characterized by comprising the following steps:
sl: in SiO2Growing a two-dimensional material film on the surface of the substrate;
s2: photoetching and defining an active area of the two-dimensional material film, and etching the two-dimensional material film in other areas;
s3: growing a first High-K layer on the surface of the two-dimensional material film;
s4: growing a first TiN layer on the surface of the first High-K layer;
s5: growing a ferroelectric gate dielectric film layer on the surface of the first TiN layer;
s6: growing a second TiN layer on the surface of the ferroelectric gate dielectric film layer;
s7: growing a second High-K layer on the surface of the second TiN layer;
s8: growing a third TiN layer on the surface of the second High-K layer;
s9: photoetching is carried out, a gate metal area is defined, and a gate electrode is stripped;
s10: photoetching protection is carried out on the metal grid, the dielectric layer of the non-grid region is etched, and a source-drain contact region of the two-dimensional material film is leaked out;
s11: photoetching and defining a source and drain electrode area of the device to form a source electrode and a drain electrode;
in step S1, the grown two-dimensional material film is MoS2A film, or a tungsten disulfide film, or a black phosphorus film, said MoS2Film(s)Is a single layer of MoS2Thin film, or multilayer MoS2A film;
in steps S3-S8, the thicknesses of the grown first High-K layer, second High-K layer, first TiN layer, second TiN layer and third TiN layer are preferably 5 nm; and the first High-K layer and the second High-K layer are both Al2O3And (3) a layer.
2. The method of claim 1, wherein: in step S5, the grown ferroelectric gate dielectric thin film layer is a barium titanate ferroelectric thin film layer, or a PZT ferroelectric thin film layer, a perovskite ferroelectric material thin film layer, or an organic ferroelectric material thin film layer.
3. The method of claim 1, wherein: in step S5, the thickness of the grown ferroelectric gate dielectric thin film layer is preferably 20 nm.
4. The method of claim 1, wherein: in step S9, a Ti/Au metal layer is grown on the surface of the third TiN layer by electron beam evaporation, and the gate electrode is stripped by lift-off process.
5. The method of claim 1, wherein: in step S11, electron beam evaporation is used to prepare source and drain metals, and a lift-off process is used to form a source electrode and a drain electrode.
6. The method of claim 4, wherein: in step S11, the prepared source-drain metal is Al metal, and the thickness thereof is preferably 50 nm.
7. A ferroelectric gate dielectric based molybdenum disulfide transistor fabricated by the method of any of claims 1-6, wherein SiO is2Substrate of SiO2A two-dimensional material film growing on the surface of the substrate, a first High-K layer, a first TiN layer and a second TiN layer sequentially growing on the surface of the two-dimensional material film,The ferroelectric gate comprises a ferroelectric gate dielectric thin film layer, a second TiN layer, a second High-K layer, a third TiN layer, a gate electrode, a source electrode and a drain electrode.
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| CN108682703B (en) * | 2018-05-30 | 2020-01-17 | 厦门大学 | Fully-electrically-controlled spin luminescence detection integrated device and preparation method thereof |
| CN110943128B (en) * | 2018-09-21 | 2021-02-09 | 中国科学院半导体研究所 | Two-dimensional MOSFET/MFIS multifunctional switch memory device and preparation method thereof |
| CN109980013A (en) * | 2019-03-04 | 2019-07-05 | 上海华力集成电路制造有限公司 | A kind of FinFET and preparation method thereof |
| CN109904050B (en) * | 2019-03-13 | 2020-02-21 | 中山大学 | Device structure for regulating and controlling two-dimensional atomic crystal field emission by ferroelectric material polarization field and preparation method and application thereof |
| CN110649092A (en) * | 2019-09-18 | 2020-01-03 | 西北工业大学 | Two-dimensional material heterojunction back gate negative capacitance tunneling transistor and preparation method thereof |
| KR20210095459A (en) | 2020-01-23 | 2021-08-02 | 삼성전자주식회사 | Field effect transistor including gate dielectric formed of two dimensional material |
| CN113363317B (en) * | 2021-06-06 | 2023-01-06 | 复旦大学 | Negative quantum capacitor device and preparation method thereof |
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Effective date of registration: 20210927 Address after: 335400 in the park, No. 1, chemical Avenue, Huayuan street, Guixi City, Yingtan City, Jiangxi Province (the former site of Liuguo chemical industry) Patentee after: Guixi crossing Photoelectric Technology Co.,Ltd. Address before: No.16, Keji Third Road, circular economy industrial park, Yongji economic and Technological Development Zone, Yongji City, Yuncheng City, Shanxi Province 044000 Patentee before: Shanxi Ganneng Semiconductor Technology Co.,Ltd. |
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