CN107610738A - A kind of efficient out of memory analysis method - Google Patents

A kind of efficient out of memory analysis method Download PDF

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Publication number
CN107610738A
CN107610738A CN201710906554.1A CN201710906554A CN107610738A CN 107610738 A CN107610738 A CN 107610738A CN 201710906554 A CN201710906554 A CN 201710906554A CN 107610738 A CN107610738 A CN 107610738A
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China
Prior art keywords
failure
memory
physical address
data
physics
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CN201710906554.1A
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Chinese (zh)
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董攀
蒋玉茜
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Beijing CEC Huada Electronic Design Co Ltd
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Beijing CEC Huada Electronic Design Co Ltd
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Priority to CN201710906554.1A priority Critical patent/CN107610738A/en
Publication of CN107610738A publication Critical patent/CN107610738A/en
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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A kind of efficient out of memory analysis method, it can realize and the visual analysis method that reliability failures analyzed pattern is shown is carried out to memory cell, physical address, failure mode that memory cell occurs in reliability evaluating etc. can be efficiently analyzed, helps the out of memory reason of fast positioning product;The present invention only provides a kind of graphic method of memory reliability failure analysis, it is not limited to how developer simulates physical address assignments with display-memory, the position for showing storage-unit-failure and form are relied in figure, intuitively shows physics of failure address and distribution.

Description

A kind of efficient out of memory analysis method
Technical field
The present invention relates to a kind of efficient out of memory Physical Analysis Methods, the physics of failure for memory is analyzed.
Background technology
Memory has been widely applied in many electronic products substantially at present, for example, mobile phone, PC, PAD, etc.;Even The high-risk field such as domestic air mail, space flight is quite a few to use memory.Memory is not only widely used, and its frequency of use is relative CPU is only second to for other peripheral circuits, therefore the reliability of its memory is extremely important, in the life cycle that it is used not Integrity problem can occur.On the other hand, the reliability assessment of memory is very important.
Current major chip companies and enterprise also all pay much attention to the reliability assessment of memory, are used in evaluation process Method it is all similar:First, carry out repeatedly erasable to memory in high and low temperature environment and read data comparison, by fail data Print to form text entry.Secondly, staff wins data from substantial amounts of text entry, then progressively analysis failure Physical data, then by physics of failure Data Integration in Microsoft Excel.Finally, histogram, normal distribution are drawn according to form Etc. pattern analysis and final conclusion.
Above-mentioned method, belongs to conventional method, has the following disadvantages:
1), staff needs to arrange text entry, and filtering out effective physical data from centre, (part producer realizes Software automatic screening), workload is huge;
2), when arranging physics of failure data, it is necessary to turn over 1,1 physical address and the corresponding positions whole for turning over 0 and upset by 0 Sort out and, intricate operation;
3) Microsoft Excel, is finally organized into, draws distribution map, intricate operation is not also directly perceived;
4), because figure is not directly perceived enough, form and distribution map for arrangement discuss and problem analysis, contrast locating are relatively tired It is difficult;
From above mentioned problem as can be seen that memory reliability evaluation work is that a kind of workload is big, the work of intricate operation, And currently without efficiently intuitively method can assess the reliability of memory, therefore it is very necessary to design a kind of analysis method 's.
According to above mentioned problem, set forth herein a kind of this method that designs for efficiently intuitively the reliability of analysis memory to be asked Topic.Following three aspect of this method requirement, first, the out of memory physical address data record of unified specification;Secondly, by soft Part draws 2D or 3D memory cell physical model;Finally, the out of memory physical address data of unified specification is recorded The software is imported, physics of failure unit is shown, and counts corresponding result on software interface, including failure sum, 0 Turn over 1,1 and turn over the information such as 0 sum, physical address, corresponding fail bit, wherein every kind of fail message is distinguished using different colors Come, facilitate staff's analyzing and positioning.
The content of the invention
The method of the present invention solves problem:Improve the deficiency of existing method, there is provided a kind of efficient out of memory Analysis method, the reliability assessment efficiency of memory can be improved.
The present invention method solution be:
First, the out of memory physical address data record of unified specification is established, will be found during reliability demonstration The physics of failure element failure mode record and preserves according to a unified form, generate the text entry of the forms such as TXT, example Such as:
VCC=5, CLK=30M, ADDR=0x0000AF4E, EXPECTDATA=0x55555555, WRONGDATA= 0x55555557;
Above-mentioned form expression, operating voltage 5V, working frequency 30Mhz, fail address 0xAF4E, expected data 0x55555555;Real data 0x55555557;Showing the at 0xAF4E addresses the 1st, there occurs the failure change that 0 turns over 1;
Secondly, memory cell physical address model is established using software, each physical address can be mapped in this In software model, the relevant information of the address can be shown by inputting specific address, the fail data of generation is recorded and imported The software model, visual physics of failure figure is generated, can intuitively find out which part physical address holds from figure Easily fail, when mouse is moved in the address realm, show specific fail message, and amplify and reduce by mouse Function can show specific physical address information;Such as Fig. 1 to Fig. 2 change.
Finally, software is counting all physical address fail datas and intuitively shown from the background, facilitate customer analysis and Orientation problem, as shown in Figure 3.
The actual physics model of graphical analog memory unit is used to pass through the actual physical address unit of memory Software on Drawing is into 2D or 3D figures and shows each physical address unit in the graphic, additionally it is possible to passes through color, shape Distinguish the concrete mode of out of memory (0, which turns over 1 or 1, turns over 0);The out of memory physical address data record of unified specification, Physics of failure data are exported by fixed and unified mode mainly during reliability testing, mainly facilitate software In the actual physics model for parsing and being easily guided into graphical analog memory unit, (physics of failure data exist concrete form Display mode in text) and form (TXT, EXCEL, WORD etc.) realized by developer, the text be used for fail data is led Enter into the physical model of graphical memory cell, form the memory physical addresses figure of failure;Fail data shows lattice Formula and mode, mainly show failure analysis result, and concrete form is realized by software developer.
The actual physics model of graphical analog memory unit is mainly used in point of analog memory actual physical address Distribution pattern and distribution situation, such as the bit wide (8bit, 16bit, 32bit) of memory cell, the distribution of address location array etc. The out of memory physical address data record importing of unified specification can be come in graphically to show fail data Deng, the model Show, and show 0 turn over 1 and 1 turn over 0 address, digit (the X position of same address location), failure sum etc.;And support To being shown while multiple memory chips.
The actual physics model of graphical analog memory unit, the display format of fail data and mode are same soft Shown in part, for intuitively showing physics of failure data to analysis personnel.
The out of memory physical address data record of unified specification, memory cell physical address model, failure logging (record) Data display format realizes that software programming can be realized using the including but not limited to software such as VB, C# by software programming.
The present invention compared with prior art the advantages of be:
(1) graphic software platform can intuitively export the result of physics of failure data, and truly reflect the mistake of unit Effect situation.
(2) the big data quantity housekeeping of staff is reduced, improves operating efficiency;
(3) searched problem relative to the substantial amounts of data result of manual read, graphic software platform is easier to analyze and positioning is lost Effect problem;
Brief description of the drawings
Fig. 1 is the visual pattern analysis method 2D schematic block diagrams of the present invention;
Fig. 2 is the physics of failure unit display format schematic block diagram of the present invention;
Fig. 3 is the physics of failure data display format and mode exemplary plot of the present invention;
Embodiment
The invention provides a kind of method, Fig. 1 is by taking 32 bit memories as an example, based on method provided by the present invention to 32 It is as follows that the reliability assessment of bit memory carries out graph visualization analytic explanation.
The first step, as shown in figure 1, being divided into 32 block 0-31 by 32 of memory, memory physics list is represented respectively 32 positions of member, wherein 0 represents 1 of all memory cell, 1 represents 2 of all memory cell, and 31 represent all storage lists 32 of member.Each is divided into N rows M row (grid line of division can select to hide), wherein NxM representative memory cells again Total actual physical address size, so all storage physical locations are indicated in figure.Require that software has herein Amplification and reduction capability, than if desired for a certain specific physical address is observed, mouse meaning address can be shown and be amplified Check.
Second step, as shown in Fig. 2 being 0 bit address physics of failure data display mode corresponding to all memory cell.Wherein Circle represents 0 fail data for turning over 1, and triangular representation 1 turns over 0 fail data.What party's inframe represented is all storage physics The failure figure that 1 of unit is occurred.It can be seen that the physics of failure data for occurring to store position at the 1st are total from the figure Number.The figure that this means suitable software can each be put with zoom, fail data is checked to facilitate, and mouse obtains the mistake During effect point position, the relevant information of the point failure, such as storage location can be being shown near mouse, failure mode, work Voltage etc..
3rd step, as shown in figure 3, being to be shown to the statistical information of global failure physical data, software developer can root More functions are added herein according to being actually needed, for more physical failure data messages to be watched and analyzed required for user, Such as when user zooms in or out to the information of the specific unit in a certain position and checked, it can separately open new window and carry out part Presentation of information.
The content not being described in detail in description of the invention belongs to the known technology of those skilled in the art.

Claims (5)

  1. A kind of 1. efficient out of memory analysis method, using the actual physics model of graphical analog memory unit, system Record, display format and the mode of one physics of failure data, graphical physical model and physical data display format are in software In show;Characterized in that, first:The out of memory physical address data record of unified specification is established, by reliability The physics of failure element failure mode found in verification process is recorded and preserved according to a unified form, generation text note Record;Secondly, memory cell physical address model is established using software, each physical address can be mapped in the software mould In type, the relevant information of the address is shown by inputting specific address, the fail data record of generation is imported into the software model, Visual physics of failure figure is generated, can intuitively find out which part physical address is easily failed from figure, When mouse is moved in the address realm, specific fail message is shown, and can show by mouse amplification and reduction capability Show specific physical address information;Finally, software statistics go out all physical address fail datas and intuitively shown.
  2. 2. out of memory analysis method according to claim 1, it is characterised in that the graphical analog memory list The actual physics model of member is used to paint the actual physical address unit of memory by software (can use the softwares such as VB, C#) 2D or 3D figures are made and show each physical address unit in the graphic, additionally it is possible to distinguishes and deposits by color, shape The concrete mode of reservoir failure (0, which turns over 1 or 1, turns over 0);The out of memory physical address data record of unified specification, mainly Physics of failure data are exported by fixed and unified mode during reliability testing, concrete form (physics of failure number According to display mode in the text) and form (TXT, EXCEL, WORD etc.) realize that the text is used for failure number by developer According to importeding into the physical model of graphical memory cell, the memory physical addresses figure of failure is formed;Fail data shows Show form and mode, mainly show failure analysis result, concrete form is realized by software developer.
  3. 3. according to the method for claim 1, it is characterised in that the actual physics of described graphical analog memory unit Model is mainly used in the distribution figure and distribution situation of analog memory actual physical address, and the model can be by unified specification Physics of failure Import data records come in fail data graphic software platform, and show that 0 turns over 1 and 1 address, the digit for turning over 0 (the X position of same address location), failure sum etc.;And support to being shown while multiple memory chips.
  4. 4. according to the method for claim 1, it is characterised in that the display format and mode of fail data and claim 1 Described figure is shown in same software, for intuitively showing physics of failure data to analysis personnel.
  5. 5. according to the method for claim 1, it is characterised in that the out of memory physical address data note of unified specification Record, memory cell physical address model, failure logging (record) data display format are realized by software programming.
CN201710906554.1A 2017-09-29 2017-09-29 A kind of efficient out of memory analysis method Pending CN107610738A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112233718A (en) * 2020-12-15 2021-01-15 深圳市芯天下技术有限公司 Fault location analysis method and device for storage unit, storage medium and terminal
WO2022160574A1 (en) * 2021-01-26 2022-08-04 长鑫存储技术有限公司 Failure analysis method, computer device and storage medium

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CN1488149A (en) * 2000-11-28 2004-04-07 ��ʽ���簬��� Fail analysis device
CN101145400A (en) * 2006-09-13 2008-03-19 上海华虹Nec电子有限公司 Embedded memory SOC mapping realization method
CN201576463U (en) * 2009-12-03 2010-09-08 上海华虹Nec电子有限公司 Device for producing and displaying bitmap information during embedded flash memory testing process
CN101976582A (en) * 2010-10-15 2011-02-16 北京航天测控技术开发公司 Storage modeling method and device
CN104751875A (en) * 2013-12-25 2015-07-01 上海华虹宏力半导体制造有限公司 Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip
US9135103B2 (en) * 2012-02-16 2015-09-15 Mentor Graphics Corporation Hybrid memory failure bitmap classification

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1488149A (en) * 2000-11-28 2004-04-07 ��ʽ���簬��� Fail analysis device
CN101145400A (en) * 2006-09-13 2008-03-19 上海华虹Nec电子有限公司 Embedded memory SOC mapping realization method
CN201576463U (en) * 2009-12-03 2010-09-08 上海华虹Nec电子有限公司 Device for producing and displaying bitmap information during embedded flash memory testing process
CN101976582A (en) * 2010-10-15 2011-02-16 北京航天测控技术开发公司 Storage modeling method and device
US9135103B2 (en) * 2012-02-16 2015-09-15 Mentor Graphics Corporation Hybrid memory failure bitmap classification
CN104751875A (en) * 2013-12-25 2015-07-01 上海华虹宏力半导体制造有限公司 Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112233718A (en) * 2020-12-15 2021-01-15 深圳市芯天下技术有限公司 Fault location analysis method and device for storage unit, storage medium and terminal
WO2022160574A1 (en) * 2021-01-26 2022-08-04 长鑫存储技术有限公司 Failure analysis method, computer device and storage medium

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