CN107590086B - Communication connection device and method and communication single board - Google Patents
Communication connection device and method and communication single board Download PDFInfo
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- CN107590086B CN107590086B CN201610533990.4A CN201610533990A CN107590086B CN 107590086 B CN107590086 B CN 107590086B CN 201610533990 A CN201610533990 A CN 201610533990A CN 107590086 B CN107590086 B CN 107590086B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
Abstract
The embodiment of the invention provides a communication connection device and a method, and a communication single board.A communication connection is switched to be connected with a configuration channel through a channel management unit, and configuration information of a processor is acquired from the configuration channel; the read-write period of the processor is prolonged through the configuration information, so that the read-write period of the CPU is matched with the BOOT FLASH, the problem that the time sequence of the CPU and the slow equipment is not matched in the prior art is solved, the flexible configuration of the communication connecting device is realized, and the communication between the CPU and the slow equipment is quickly realized.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a communication connection device and method, and a communication board.
Background
At present, in order to improve the communication efficiency, most communication devices are implemented by using a high-performance processor (CPU), for the use of high performance CPUs, however, special attention needs to be paid to the fact that when communicating with slow devices, for the selection of the interface chip and the matching of the timing sequence, generally speaking, in order to adapt to the slower external memory and the input/output device, the existing processing method is to perform the program initialization setting on the CPU, the method can be realized in various ways, and the current proposal is that the CPU is realized by an internal solidified program, in particular, the CPU is provided with an internal solidified programmable storage space, it stores programs that can extend the bus cycle, but due to hardware constraints, such extensions are typically limited, the type selection of the interface device is relatively limited, and the interface device is configured through a CPU external interface chip, specifically, I is loaded through the CPU.2C. The configuration program of the interface chip such as SPI is implemented, but the cost is increased by externally connecting the interface chip.
Disclosure of Invention
The communication connection device, the communication connection method and the communication single board provided by the embodiment of the invention aim to solve the problem that the CPU cannot be matched with the BOOT FLASH to read data because the time sequence of the CPU is not matched with that of slow equipment in the prior art.
To solve the above technical problem, an embodiment of the present invention provides a communication connection device, including: the system comprises a time sequence analysis unit, a channel management unit, a configuration channel and a connection channel;
the time sequence analysis unit is externally connected with a processor, and the connecting channel is externally connected with a slow device;
when the processor is powered on, the channel management unit switches the communication connection to the configuration channel and transmits configuration information to the processor through the time sequence analysis unit;
after the transmission of the configuration information is completed, the channel management unit switches the communication connection to the connection channel, and the information on the slow equipment is loaded to the processor through the time sequence analysis unit by the channel management unit.
In one aspect, an embodiment of the present invention further provides a communications board, including: a processor, a slow device, and a communication link as described above.
On the other hand, an embodiment of the present invention further provides a communication connection method, including:
after the processor is powered on, acquiring configuration information of the processor through a configuration channel;
sending the configuration information to the processor for configuration;
and after the configuration information is sent, switching the processor to be in communication connection with the slow equipment through a connection channel.
On the other hand, the embodiment of the present invention further provides a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and the computer-executable instructions are used to execute the foregoing communication connection method.
The invention has the beneficial effects that:
according to the communication connection device, the communication connection method, the communication single board and the computer storage medium provided by the embodiment of the invention, the communication connection is switched to be connected with the configuration channel through the channel management unit, the configuration information of the processor is obtained from the configuration channel, the channel management unit sends the configuration information to the processor through the time sequence analysis unit, and the processor adjusts according to the received configuration information so that the reading rate of the processor is matched with that of the slow-speed equipment; after the sending of the configuration information is completed, the communication management unit switches the communication connection to the connection channel, and the information on the slow equipment is loaded on the processor through the time sequence analysis unit through the connection channel, so that the communication between the high-performance processor and the slow equipment is realized.
Drawings
Fig. 1 is a schematic structural diagram of a communication connection device according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of another communication connection device according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a communications board according to a third embodiment of the present invention;
fig. 4 is a flowchart of a communication connection method according to a fourth embodiment of the present invention;
fig. 5 is another flowchart of a communication connection method according to a fifth embodiment of the present invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
The first embodiment:
the communication connection device provided by the embodiment of the invention has the advantages that the configuration information for adjusting the configuration of the processor is stored in the configuration channel, the channel management unit reads the configuration information of the processor from the configuration channel and sends the configuration information to the processor through the time sequence analysis unit, the processor performs configuration according to the received configuration information and simultaneously switches the communication management unit to be connected with the connection channel, so that the communication connection between the high-performance processor and the slow-speed equipment is realized, and the problem that the time sequence of a CPU (central processing unit) and the slow-speed equipment is not matched in the prior art is solved.
Referring to fig. 1, fig. 1 is a structural diagram of a communication connection device provided in this embodiment, where the communication connection device 1 includes: timing analysis unit 11, channel management unit 12, configuration channel 13 and connection channel 14, wherein:
the communication connecting device 1 is connected with the processor through the timing sequence analysis unit 11 and is connected with the slow speed equipment through the connecting channel 14;
when the processor is powered on, the communication connection device 1 switches the channel management unit 12 to be in communication connection with the configuration channel 13, reads configuration information of the processor from the configuration channel 13 and sends the configuration information to the timing analysis unit 11, the timing processing unit 11 transmits the received configuration information to the processor, and the processor performs corresponding configuration according to the configuration information so that the processing read-write rate is matched with that of the slow-speed equipment;
after the communication connection device 1 completes the processor configuration through the configuration information, the channel management unit 12 is switched to be in communication connection with the connection channel 14, and the information on the slow equipment is loaded onto the processor through the timing analysis unit 11.
All the modules or units provided in this embodiment may also be implemented by a Programmable Logic Device (CPLD), specifically implemented by interconnecting Logic configuration channels in the CPLD, and may also be implemented by writing configuration program codes according to the type of the slow Device to combine the Logic configuration channels in the CPLD, so as to implement all the functions of the communication connection apparatus 1 provided in this embodiment.
In this embodiment, the connection channel 14 specifically includes a FLASH channel, the communication connection device 1 is connected to a BOOT FLASH in the slow device through the FLASH channel, and the system version information on the BOOT FLASH is loaded into the processor through the timing analysis unit 11 through the FLASH channel.
The channel management unit 12 is specifically configured to manage the configuration channel 13 and the connection channel 14, and by determining whether all configuration information in the configuration channel 13 is read and sent out, if yes, the channel management unit 12 is switched to be connected with the connection channel 14, so that the processor communicates with the BOOT FLASH, and the processor reads system version information on the BOOT FLASH through the connection channel 114.
In this embodiment, when the processor needs to read configuration information from the configuration channel 13, the timing analysis unit 11 specifically includes an ADDR address information of a pre-latch processor, reads corresponding configuration information through the configuration channel 13 stack, and transmits the configuration information to the processor for configuration.
In this embodiment, the communication connection apparatus 1 further includes setting a counter and a count threshold in the channel management unit 12, determining the count value of the configuration information read by the channel management unit 12 and the count threshold, and adjusting the channel management unit 12, the configuration channel 13 and the connection channel according to the determination result to switch the communication connection.
By implementing the communication connection device 1 provided in this embodiment, when powering on the CPU, the communication connection device 1 first needs to analyze the LOCAL BUS timing of the CPU through the timing analysis unit 11, configure the configuration information of the adjustment processor according to the analyzed result through the configuration channel 13, and directly output the configured configuration information to the processor through the timing analysis unit 11 through the channel management unit 12 to extend the read-write cycle of the CPU to match the BOOT FLASH in the slow device.
Further, in the process that the channel management unit 12 reads the configuration information in the configuration channel 13, the channel management unit 12 also counts the actual times of reading the configuration information through a counter, wherein the default value of the counter is 0, when the CPU reads the configuration information, the count of the counter is sequentially increased, when the count of the counter reaches a count threshold, the flag position 1 of the channel management unit 12 is directly switched to be connected with the connection channel 14, so that the LOCAL BUS of the CPU is in a state of communicating with the BOOT FLASH, and meanwhile, the processor reduces the read-write cycle of the CPU to a speed capable of being matched with the BOOT FLASH according to the read configuration information.
According to the communication connection device provided by the embodiment of the invention, the bus time sequence of the processor is analyzed through the time sequence analysis unit, the configuration information of the processor is sent to the processor through the configuration channel, and the read-write speed of the processor is adjusted according to the configuration information, so that the processor can be in normal communication connection with the slow equipment; specifically, the channel management unit switches the communication connection to the connection with the configuration channel, and transmits the configuration information of the processor to the processor through the timing analysis unit, after the configuration information is transmitted, the channel management unit switches the communication connection to the connection channel and loads the information on the slow equipment to the processor through the time sequence analysis unit, the read-write period of the processor is prolonged through the configuration information, so that the read-write period of the CPU is matched with the BOOT FLASH, thereby solving the problem of non-matching time sequences of the CPU and the slow equipment in the prior art, realizing flexible configuration of the communication connecting device, quickly realizing communication between the CPU and the slow equipment, all units provided by the communication connecting device can be realized through a CPLD logic device in a single board, so that an additional configuration chip can be further saved, and the hardware cost is reduced.
Second embodiment:
referring to fig. 2, fig. 2 is another structural diagram of a communication connection device provided in this embodiment, the device includes a timing analysis unit 11, a channel management unit 12, a configuration channel 13, a connection channel 14, and a configuration unit 15, wherein,
the timing analysis unit 11 is externally connected with a processor, and the connecting channel 14 is externally connected with slow equipment; when the processor is powered on, the channel management unit 12 switches the communication connection to the configuration channel 14, and transmits the configuration information to the processor through the timing analysis unit 11 by the channel management unit 12; after the transmission of the configuration information is completed, the channel management unit 12 switches the communication connection to the connection channel 14, and loads the information on the slow device to the processor through the timing analysis unit 11 by the channel management unit 12, and the configuration unit 15 is connected to the configuration channel 13 and is used for storing the configuration information of the processor.
In this embodiment, the configuration unit 15 may be specifically disposed inside the communication connection device 1, or may be disposed outside the communication connection device 1, and the configuration unit may be a storage unit on a single board.
In this embodiment, the timing analysis unit 11 is specifically connected to a BUS of the processor, the timing information of the processor is obtained through the BUS, the timing analysis unit 11 sets an adjustment instruction according to a difference between a read-write rate of the processor and a slow device for the received read-write rate of the timing analysis processor, the adjustment instruction is stored in the configuration unit 15, when the processor is powered on, the processor sends a read request, the timing analysis unit 11 analyzes signals of an address latch signal AE, a chip select CS, a read OE, a write WR, an address ADDR, DATA and the like according to the read request, and analyzes the above information, specifically, the communication connection device 1 loads a corresponding CPU chip manual according to a type of the CPU, the LOCAL BUS timing graph provided by the CPU chip is realized through a logic code, when an analyzed CPU BUS ALE signal is low, the communication connection device 1 outputs signals to latch ADD address information of the CPU, when CS and OE signals are low level, the configuration channel 13 reads corresponding DATA from the configuration unit 15 according to the ADDR address information, the DATA is an adjusting instruction for adjusting the CPU and is sent to the CPU through the channel management unit 12 and the timing analysis unit 11, and finally the CPU performs configuration adjustment according to the received adjusting instruction.
In this embodiment, a FLAG bit CNT _ FLAG is further set in the path management unit 12, and the FLAG bit value CNT _ FLAG is set according to whether the configuration times preset for the CPU are completed, that is, the times for the CPU to receive the configuration information, and the more complicated the register configuration for the CPU, the more the configuration times. The switch of the channel management unit 12 between the configured channel and the connected channel is specifically performed according to whether the FLAG bit CNT _ FLAG is set to 0 or 1, and preferably, the default set value of the device is 0, and corresponds to the configured channel 13, and when the set value is 1, corresponds to the connected channel, that is, the FLASH channel. After the channel management unit 12 finishes reading the processor configuration information in the configuration unit 15 through the configuration channel 13, the channel management unit 12 sets the CNT _ FLAG bit to 1 and switches the CNT _ FLAG bit to be connected with the FLASH channel, thereby realizing that the processor communicates with the BOOT FLASH through the FLASH channel.
In this embodiment, the CPU chip manual loaded by the channel management unit 12 usually provides a configurable internal register address and related configuration information, where the configuration information usually includes a CPU bus interface rate, a port allocation, a core frequency, and the like, and the configuration unit 15 sets an adjustment instruction according to the configuration information, where the adjustment instruction is to adjust the configuration information of the CPU to match with the slow device BOOT FLASH, and the adjustment instruction is specifically stored in the configuration unit 15, for example, to store an adjustment instruction for reducing the CPU bus interface rate. When the CPU is powered on, the CPU bus reads the adjustment instruction from the configuration unit 15, and the CPU configures the relevant registers inside the CPU according to the read configuration information, thereby extending the bus read-write cycle and reducing the speed of matching with the BOOT FLASH.
The third embodiment:
referring to fig. 3, fig. 3 is a structural diagram of the communications board provided in this embodiment, where the communications board 3 includes a processor 31, a slow device 32 and a communications connection device 1, where the communications connection device 1 is configured to provide configuration information to the processor, the processor 31 configures according to the configuration information provided by the communications connection device 1, and after the configuration is completed, the processor 31 is connected to the slow device 32 through the communications connection device 1, so that the read/write rates of the processor 31 and the slow device are matched.
In this embodiment, specifically, the channel management unit 12 in the communication connection device 1 switches the communication connection to the configuration channel 13, and the channel management unit 12 transmits the configuration information to the processor via the timing analysis unit 11, the processor 31 performs configuration according to the configuration information sent by the timing analysis unit 11, after the configuration is completed, the configuration completed information is fed back to the communication connection device 1, the channel management unit 12 performs channel switching according to the information fed back by the processor 31, specifically, the channel management unit 12 switches the configuration channel 13 to the connection channel 14 for connection, and the information on the slow device is loaded to the processor 31 via the timing analysis unit 11 via the connection channel 14.
In the present embodiment, the timing analysis unit 11 analyzes the LOCAL BUS timing of the processor 31, and configures the processor 31 by the analog address and the configuration information provided by the configuration unit 15. That is, the read-write cycle of the processor 31 is extended by directly outputting the configuration information through the communication connection device 1, and then the read-write cycle of the processor 31 is matched with the BOOT FLASH.
The channel management unit 12 provided in this embodiment is further provided with a counter, and a count threshold is set for the counter, the counter defaults to 0 at the power-on initial time, and the flag bit of the counter defaults to 0. When the processor 31 reads the configuration information, the count of the counter is sequentially increased along with the number of times of reading the configuration information, when the counter is full, the channel management unit 12 sets the flag position in the counter to 1, and the channel management unit 12 switches the channel, so that the bus of the processor 31 is in a state of communicating with the BOOT FLASH.
Configuration unit 15 provides configuration information, which consists of a plurality of bytes and requires a plurality of processor 31 read and write cycles to complete, and an analog bus address ADDR. The counter is increased by 1 every time the counter is read, the mark position is 1 when the configuration is completed, the read-write period of the processor 31 is reduced to the speed which can be matched with the BOOT FLASH, the channel management unit 12 switches the switch to the FLASH channel, and the bus of the processor 31 is in normal communication with the BOOT FLASH.
In this embodiment, the communication connection device 1 in the communication board 3 may be specifically implemented by a CPLD in the board, preferably, the function implemented by each unit of the communication connection device 1 in this embodiment is implemented by compiling a program code to combine and connect each logic unit in the CPLD, the CPLD on the board stores the compiled configuration code, and after the processor 31 is powered on, the processor 31 directly reads the corresponding configuration code from the CPLD to combine and connect each logic unit in the CPLD, so that an additional external interface configuration chip may be omitted, and the hardware design cost when designing the communication board may also be reduced.
The fourth embodiment:
referring to fig. 4, fig. 4 is a flowchart of a communication connection method provided in this embodiment, where the processing steps of the method specifically include:
s401, after the processor is powered on, configuration information is obtained through a configuration channel.
In the step, the configuration information is a BUS interface speed adjusting instruction of the processor, the communication connection device analyzes the time sequence through logic codes according to a LOCAL BUS time sequence chart provided by a CPU chip manual, latches the ADDR address information of the CPU when a CPU BUS ALE signal is low, and provides the DATA adjusting instruction information corresponding to the ADDR address to the CPU through the configuration unit when CS and OE signals are low.
In this embodiment, after the processor is powered on, the method further includes acquiring a configuration request of the processor, setting configuration information of the processor according to the configuration request, and storing the configuration information in the configuration unit; when analyzing the time sequence of the CPU, the analysis is specifically performed according to the time sequence chart provided in the CPU chip manual loaded by the communication connection device, the corresponding register address, and the related configuration information.
S402, sending the configuration information to the processor for configuration.
In the step, sending the configuration information to the processor specifically includes latching the processed ADDR address information in advance, reading the corresponding configuration information from the configuration channel, and transmitting the configuration information to the processor for configuration, and the CPU configures the relevant registers inside the CPU according to the read configuration information, thereby achieving the purposes of prolonging the bus read-write period and reducing the speed of matching with the BOOT FLASH.
In this embodiment, the method further includes setting a counter and a count threshold, and switching the processor to be connected to the connection channel by determining the count value of the read configuration information and the count threshold.
And S403, after the configuration information is sent, switching the processor to be in communication connection with the slow equipment through a connection channel.
In this step, a counter and a counting threshold are further provided, where the counter is configured to count the actual number of times of reading the configuration information, determine the actual number of times and the counting threshold, and implement, according to a result of the determination, switching of communication connection between the configuration channel and the connection channel by the processor.
Specifically, the actual times of reading the configuration information are counted by a counter, wherein the default value of the counter is 0, when the CPU reads the configuration information, the counting of the counter is sequentially increased, after the counting of the counter reaches a counting threshold value, the flag position of the counter is directly set to 1, the processor is switched to be connected with the connecting channel, the LOCAL BUS BUS of the CPU is in a state of communicating with the BOOT FLASH, and meanwhile, the processor reduces the reading and writing period of the CPU to a speed capable of being matched with the BOOT FLASH according to the read configuration information.
In this embodiment, the connection channel includes a FLASH channel, the FLASH channel is externally connected to the BOOT FLASH, and the system version information on the BOOT FLASH is loaded to the processor through the timing analysis unit through the FLASH channel.
In this embodiment, the communication connection method provided above may also be implemented by directly setting a program code, specifically, the program code is stored in a CPLD on a single board, after the CPU is powered on, the processor reads a BOOT program code stored in the CPLD to initialize and configure the CPU, and connects logic units in the CPLD with each other, so as to extend the read-write cycle of the CPU through a configuration instruction, and then match the read-write cycle of the CPU with the BOOT FLASH.
Fifth embodiment:
referring to fig. 5, fig. 5 is another flowchart of the communication connection method provided in this embodiment, and the processing steps of the method are as follows:
s501, the CPU is electrified and initialized, and a configuration instruction is read.
S502, the timing analysis unit analyzes the LOCAL BUS timing of the CPU, and the CPU is configured through the simulation address and the configuration instruction provided by the configuration unit.
In this step, the timing analysis specifically includes signals such as an address latch signal ALE, a chip select CS, a read OE, a write WR, an address ADDR, and DATA. Analyzing the LOCAL BUS BUS timing sequence provided by the CPU chip manual is realized by logic codes, when the CPU BUS ALE signal is low, the ADDR address information of the CPU is latched, when the CS signal and the OE signal are low, the DATA configuration command information corresponding to the ADDR address is provided for the CPU through the configuration unit 40, namely, the CPLD directly outputs the configuration instruction to prolong the read-write period of the CPU, and then the read-write period of the CPU is matched with the BOOT FLASH.
S503, the channel management unit is responsible for managing the configuration channel and the FLASH channel, and switching is carried out by judging the CNT _ FLAG FLAG bit value in the channel management unit.
In this embodiment, a counter is provided inside the path management unit, the counter defaults to 0 at power-on initial time, and the CNT _ FLAG bit defaults to 0. When a configuration instruction is read for the CPU, the counting of the counter is sequentially increased, when the counter is full, the CNT _ FLAG FLAG bit position is 1, the channel management unit switches the channel, the specific CNT _ FLAG FLAG bit value is set according to whether the configuration frequency preset for the CPU is finished, and when the configuration of a register of the CPU is more complicated, the configuration frequency is more. Setting 0 and 1 are respectively corresponding to the configuration channel and the FLASH channel. After the single board is powered on, CNT _ FLAG defaults to set 0, and the CPU bus reads the information of the configuration unit 40 by using the configuration channel. After the configuration unit is read, the CNT _ FLAG FLAG bit is set to be 1, and the CPU LOCAL BUS is switched to a FLASH channel to be communicated with the BOOT FLASH.
S504, the configuration unit stores configuration information in the ADDR to be read and written by the CPU.
Usually, the CPU chip manual provides configurable internal register addresses and related configuration information, and bus interface rate, port allocation, core frequency, etc. are commonly used. Configuration unit 40 provides configuration instructions that reduce the rate of the CPU bus interface. In step S503, after the CPU is powered on, the LOCAL BUS reads the configuration information from the configuration channel, and the CPU configures the relevant registers inside the CPU according to the read configuration information, thereby extending the BUS read-write cycle and reducing the speed that can be matched with the BOOT FLASH.
And S505, after the CPU reads the configuration unit information, the channel management unit switches the communication connection to a FLASH channel, and the CPU loads BOOT FLASH system version information through the FLASH channel.
In this embodiment, the above processing procedure can be directly implemented by the configuration code stored in the CPLD on the single board, and an additional configuration chip can be omitted by storing the configuration code using the CPLD, thereby reducing the hardware cost.
Through the implementation of the communication connection device, the communication connection method and the communication single board provided by the embodiment of the invention, the configuration information of the processor is obtained from the configuration channel through the channel management unit, the configuration information is transmitted to the processor through the time sequence analysis unit, the processor is configured, and after the transmission is finished, the channel management unit is switched to be connected with the connection channel, the configuration information is used for adjusting the time sequence of the processor to be matched with the memory in the slow device, so that the problem that the high-performance processor and the slow device cannot communicate due to the mismatching of the time sequences is solved, and the communication connection device has the advantages of flexible configuration and convenience in updating in the debugging and using processes.
Furthermore, compared with the prior art, the configuration information for initializing the processor provided by the embodiment of the invention is not solidified in the processor, but is the configuration program written according to the type of the slow device communicating with the processor, and as most of the current single boards use logic devices such as CPLDs (complex programmable logic devices), the CPLDs are used for storing the configuration program, so that an additional configuration chip can be saved, and the hardware cost is reduced.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the invention described above may be implemented in a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented in program code executable by a computing device, such that they may be stored on a computer storage medium (ROM/RAM, magnetic disk, optical disk) and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A communication connection device, comprising: the system comprises a time sequence analysis unit, a channel management unit, a configuration channel and a connection channel;
the time sequence analysis unit is externally connected with a processor, and the connecting channel is externally connected with a slow device; when the processor is powered on, the channel management unit switches the communication connection to the configuration channel and transmits configuration information to the processor through the time sequence analysis unit; after the transmission of the configuration information is completed, the channel management unit switches the communication connection to the connection channel, and the information on the slow equipment is loaded to the processor through the time sequence analysis unit by the channel management unit; the configuration information is configuration information of a processor, and the configuration information is used for adjusting the time sequence of the processor to be matched with a memory in the slow device.
2. The communication connection device of claim 1, further comprising a configuration unit coupled to the configuration channel for storing configuration information of the processor.
3. The communication connection device according to claim 1 or 2, wherein the connection channel comprises a FLASH channel, the FLASH channel is externally connected to a BOOT FLASH, and system version information on the BOOT FLASH is loaded to the processor through the timing analysis unit by the FLASH channel.
4. The communication connection apparatus according to claim 1 or 2, wherein transmitting the configuration information of a processor to the processor via the timing resolution unit comprises: the time sequence analysis unit latches ADDR address information of the processor, reads corresponding configuration information through the configuration channel, and transmits the configuration information to the processor for configuration.
5. The communication connection device according to claim 1 or 2, wherein a counter and a count threshold are set in the channel management unit, and the channel management unit determines whether the count value of the configuration information read by the channel management unit and the count threshold are read, and adjusts the channel management unit and switches the communication connection between the configuration channel and the connection channel according to the determination result.
6. A communications board, comprising: a processor, a slow device, and a communication link apparatus as claimed in any one of claims 1 to 5.
7. A method for communication connection, comprising:
after the processor is powered on, acquiring configuration information of the processor through a configuration channel; the configuration information is configuration information of a processor, and the configuration information is used for adjusting the time sequence of the processor to be matched with a memory in slow equipment;
sending the configuration information to the processor for configuration;
and after the configuration information is sent, switching the processor to be in communication connection with the slow equipment through a connection channel.
8. The communication connection method of claim 7, wherein after powering on the processor, before obtaining configuration information of the processor through the configuration channel, further comprising: and acquiring the configuration request of the processor, setting the configuration information of the processor according to the configuration request, and storing the configuration information in a configuration unit.
9. The communication connection method according to claim 7 or 8, wherein the sending the configuration information to the processor for configuration comprises: the address information of the ADDR of the processor is latched in advance, corresponding configuration information is read through the configuration channel, and the configuration information is transmitted to the processor for configuration.
10. The communication connection method according to claim 7 or 8, wherein switching the processor to be in communication connection with the slow device through the connection channel comprises:
setting a counter and a counting threshold, wherein the counter is used for counting the actual times of reading the configuration information;
judging the actual times and the counting threshold value;
and switching communication connection between the configuration channel and the connection channel by the processor according to the judgment result.
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| CN201610533990.4A CN107590086B (en) | 2016-07-08 | 2016-07-08 | Communication connection device and method and communication single board |
| PCT/CN2017/091501 WO2018006777A1 (en) | 2016-07-08 | 2017-07-03 | Communication connection apparatus and method, and communication board |
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| JPS5818032B2 (en) * | 1978-09-20 | 1983-04-11 | 沖電気工業株式会社 | Communication control device |
| CN1192313C (en) * | 2002-02-06 | 2005-03-09 | 华为技术有限公司 | Regulation method of peripheral control signal time sequence |
| CN100543708C (en) * | 2007-11-28 | 2009-09-23 | 中兴通讯股份有限公司 | A kind of control method of processor accessing slow memory |
| CN101989244B (en) * | 2009-08-05 | 2013-01-23 | 华为技术有限公司 | Signal conversion device and method as well as communication equipment |
| JP2013500510A (en) * | 2009-11-12 | 2013-01-07 | 株式会社日立製作所 | Disk array system and method for adding hard disk drive in disk array system |
| CN102073612A (en) * | 2009-11-20 | 2011-05-25 | 英业达股份有限公司 | Architecture for converting CPU (Central Processing Unit) socket into low-speed bus |
| TWI547784B (en) * | 2011-04-22 | 2016-09-01 | 緯創資通股份有限公司 | Method of dynamically adjusting bus clock and device thereof |
| CN105094295B (en) * | 2014-05-12 | 2018-07-03 | 联想(北京)有限公司 | A kind of information processing method and electronic equipment |
-
2016
- 2016-07-08 CN CN201610533990.4A patent/CN107590086B/en active Active
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2017
- 2017-07-03 WO PCT/CN2017/091501 patent/WO2018006777A1/en active Application Filing
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| Publication number | Publication date |
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| CN107590086A (en) | 2018-01-16 |
| WO2018006777A1 (en) | 2018-01-11 |
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