CN107579075B

CN107579075B - Display device

Info

Publication number: CN107579075B
Application number: CN201710067676.6A
Authority: CN
Inventors: 李冠锋; 吴湲琳
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2016-07-05
Filing date: 2017-02-07
Publication date: 2020-11-27
Anticipated expiration: 2037-02-07
Also published as: CN112542468A; CN107579075A

Abstract

The invention provides a display device, comprising a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a first surface and a second surface, and the second surface is opposite to the first surface; the first conducting layer is arranged on the first surface; the second conducting layer is arranged on the second surface; the processing unit is arranged on the second surface and is electrically connected with the second conducting layer; and the first connecting part is at least partially arranged in the substrate and penetrates from the first surface to the second surface, wherein the first conducting layer is electrically connected with the second conducting layer through the first connecting part.

Description

Display device

Technical Field

The present invention relates to a display device, and more particularly, to a display device having a connection portion in a substrate.

Background

With the development of digital technology, display devices have been widely used in various aspects of daily life, for example, they have been widely used in modern information devices such as televisions, notebooks, computers, mobile phones, smart phones, and the like. In the current display device, the processing unit and the display unit are disposed on the same surface of the substrate, and the boundary of the non-display area is large, so that the effective display space is limited.

Disclosure of Invention

Some embodiments of the present invention provide a display device, comprising a substrate having a first surface and a second surface, the second surface being opposite to the first surface; the first conducting layer is arranged on the first surface; the second conducting layer is arranged on the second surface; the processing unit is arranged on the second surface and is electrically connected with the second conducting layer; and the first connecting part is at least partially arranged in the substrate and penetrates from the first surface to the second surface, wherein the first conducting layer is electrically connected with the second conducting layer through the first connecting part.

In order to make the features and advantages of the embodiments of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a cross-sectional view of a display device according to some embodiments of the invention;

FIGS. 2A-2E are schematic diagrams of stages in a fabrication process for forming a connection in a substrate, according to some embodiments of the invention, wherein FIGS. 2A-2D are perspective views and FIG. 2E is a cross-sectional view;

FIGS. 3A-3F are schematic diagrams of stages in a fabrication process for forming a connection in a substrate, according to some embodiments of the invention, wherein FIGS. 3A-3E are perspective views and FIG. 3F is a cross-sectional view;

FIGS. 4A-4E are cross-sectional views of stages in a fabrication process for forming a substrate with through holes and blind vias, in accordance with some embodiments of the present invention;

FIGS. 5A-5B are cross-sectional views of a substrate and a through-hole, in accordance with some embodiments of the present invention;

FIG. 6A is a cross-sectional view of a display device according to some embodiments of the inventions;

FIG. 6B is a top view of the circuit configuration of the display device shown in FIG. 6A according to some embodiments of the present invention;

FIG. 6C is a schematic cross-sectional view of some embodiments, taken along line C-C' of the display device shown in FIG. 6B;

FIG. 6D is a schematic cross-sectional view of the display device shown in FIG. 6B along line D-D' according to some embodiments;

FIG. 6E is a schematic cross-sectional view of some embodiments taken along line E-E' of the display device shown in FIG. 6B;

FIG. 6F is a top view of a display device according to some embodiments of the invention, the variation shown in FIG. 6B;

FIG. 7A is a cross-sectional view of a display device according to some embodiments of the inventions;

FIG. 7B is a top view of the circuit configuration of the display device shown in FIG. 7A according to some embodiments of the present invention;

FIG. 7C is a schematic cross-sectional view of some embodiments of the display device shown in FIG. 7B along line F-F';

FIG. 7D is a schematic cross-sectional view of some embodiments, taken along line G-G' of the display device shown in FIG. 7B;

FIG. 7E is a schematic cross-sectional view of the display device shown in FIG. 7B taken along line H-H' according to some embodiments;

FIG. 7F is a top view of a display device according to some embodiments of the invention, the variation shown in FIG. 7B;

FIG. 8 is a schematic circuit diagram of a demultiplexer according to some embodiments of the present invention;

FIG. 9 is a top view of a display device according to some embodiments of the inventions;

FIG. 10A is a schematic cross-sectional view of the display device shown in FIG. 9 taken along line A-A' of the display device according to some embodiments;

FIG. 10B is a schematic cross-sectional view of some embodiments, taken along line B-B' of the display device shown in FIG. 9;

FIG. 11A is a partial cross-sectional view of a display device according to some embodiments of the inventions;

FIG. 11B is a partial top view of the display device of FIG. 11A in accordance with some embodiments of the present invention;

FIG. 12 is a partial cross-sectional view of a display device according to some embodiments of the invention;

FIG. 13 is a partial cross-sectional view of a display device according to some embodiments of the invention;

FIG. 14A is a partial cross-sectional view of a display device according to some embodiments of the inventions;

FIG. 14B is a partial top view of the display device of FIG. 14A in accordance with some embodiments of the present invention;

FIG. 15A is a partial cross-sectional view of a display device according to some embodiments of the inventions;

FIG. 15B is a partial top view of the display device shown in FIG. 15A in accordance with some embodiments of the present invention;

FIG. 16 is a cross-sectional view of a display device according to some embodiments of the invention;

FIG. 17 is a cross-sectional view of a display device according to some embodiments of the invention;

fig. 18 is a cross-sectional view of a display device according to some embodiments of the invention.

Description of the symbols

10-a processing unit;

20-a substrate;

20A-a first surface;

20B to a second surface;

30-a first connection;

41-a first conductive layer;

42-a second conductive layer;

50 display element layers;

100 to a first carrier substrate;

101 to a second carrier substrate;

110-columns;

120 to a substrate;

120A to a first surface;

120B to a second surface;

130-a first connection;

130A-via hole;

140 to a display element layer;

141 to a processing unit;

150-buffer layer;

160-conductive columns;

180-a semi-permeable membrane photomask;

190-blind holes;

200-through holes;

210-active area;

220-bending area;

230 to a gate driving circuit region;

240-metal material;

240A to a conductive layer;

240B to a first connection;

251 to a first conductive layer;

251a to a first section;

251b to a second section;

252 to a second conductive layer;

260-display element layer;

270 to a processing unit;

290 to a gate drive circuit;

300-space;

306A to a first touch transmission part;

306 SD-source/drain layer

303 to a semiconductor layer;

306G to a grid;

320-insulating layer;

325A to an insulating layer;

325B insulating layer;

330-doped region;

340-channel area;

350 to a gate layer;

350A-a conductive portion;

360-contact hole;

360C-contact holes;

370-pixel driving circuit;

380A to a second touch transmission part;

380 SD-source/drain;

380C-contact hole;

400-active layer;

410 insulating layer

420-capacitance;

430-insulating layer;

435 pixel definition layer;

440-a first electrode;

440A to a third touch transmission section;

450 to a light emitting layer;

460-a second electrode;

500-packaging layer;

510A-touch control electrodes;

510B-touch signal lines;

520 touch transmission part;

530-touch signal lines;

530A-connecting part;

540-conductive ink;

550-a light-emitting element;

550C-contact holes;

600 to a processing unit;

610-a substrate;

610A to a first surface;

610B to a second surface;

620 to a first connection;

631 — a first conductive layer;

632 to a second conductive layer;

640 to a display element layer;

651 to a second connecting portion;

650A-display signal line;

650B output signal circuit;

660-demultiplexer;

670 data lines;

690-a second insulating layer;

691 insulating layer;

692 to an insulating layer;

700 to a first insulating layer;

710 to a processing unit;

720-conducting wire;

721 to a first conductive layer;

722 to a second conductive layer;

730-a first connection;

740-a substrate;

740A-a first surface;

740B-a second surface;

750 to a display element;

751 to a second connection section;

760 to a gate driving circuit;

760A to display signal lines;

760B to an output signal circuit;

770-a demultiplexer;

780-data line;

790 to a first insulating layer;

800-a second insulating layer;

810 to a processing unit;

820-a demultiplexer;

1000-display device;

2000-display device;

2000P-part of the display device;

4000-display device;

4000A-touch area;

4000B-peripheral area;

5000-display device;

6000-display device;

A. b, C-a first connection;

d1, D2, Dn-first connection part;

G1-Gn first connection part;

area A1-A5;

P1-P3-projection;

r-a reference plane;

T1-T4 thin film transistor;

Y0-Y5-data line.

Detailed Description

The following describes an element substrate, a display device, and a method for manufacturing a display device according to some embodiments of the present invention in detail. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of embodiments of the invention. The specific elements and arrangements described below are merely illustrative of some embodiments of the invention for simplicity and clarity. These are, of course, merely examples and are not intended to be limiting. Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely provided for a simplified and clear description of some embodiments of the present invention, and are not intended to represent any correlation between the different embodiments and/or structures discussed. Furthermore, when a first material layer is located on or above a second material layer, the first material layer and the second material layer are in direct contact. Alternatively, one or more further layers of material may be provided, in which case there may not be direct contact between the first and second layers of material.

In addition, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used in embodiments to describe one element's relative relationship to another element of the figures. It will be understood that if the device of the drawings is turned over with its top and bottom reversed, elements described as being on the "lower" side will be turned over to elements on the "higher" side.

As used herein, the terms "about", "approximately", "substantial" and "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given herein are approximate quantities, i.e., the meanings of "about", "about" and "about" are intended to be implied unless otherwise indicated.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers and/or sections. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of some embodiments of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Some embodiments of the invention can be understood with reference to the accompanying drawings, which are also to be considered part of the description of the embodiments of the invention. It is to be understood that the drawings of the embodiments of the present invention are not to scale of actual devices or elements. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. Furthermore, the structures and devices in the drawings are schematically depicted in order to clearly illustrate the features of the embodiments of the present invention.

In some embodiments of the invention, relative terms such as "lower", "upper", "horizontal", "vertical", "lower", "upper", "top", "bottom", and the like, are to be understood as referring to the segment and the relative figures as drawn. These relative terms are for convenience of description only and do not imply that the described apparatus should be constructed or operated in a particular orientation. Terms concerning bonding, connecting, and the like, such as "connected," "interconnected," and the like, may refer to two structures as being in direct contact, or alternatively, to two structures not being in direct contact, unless expressly defined otherwise, wherein another structure is disposed between the two structures. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed.

It is noted that the term "substrate" may include devices already formed on a transparent substrate and various layers overlying the substrate, on which any desired transistor devices may have been formed, but is only illustrated as a flat substrate for simplicity of the drawing.

Referring first to fig. 1, fig. 1 is a cross-sectional view of a display device 1000 according to some embodiments of the invention. The display device 1000 includes a processing unit 10, a substrate 20, and a display element layer 50. The processing unit 10 may comprise, for example, an Integrated Circuit (IC), a microprocessor, a memory device, other signal processing devices, or any combination thereof. The substrate 20 may be a transparent substrate, such as a glass substrate, a ceramic substrate, a plastic substrate, or any other suitable substrate. The substrate 20 may be a rigid substrate or a flexible substrate. The display element layer 50 may include gate driving circuitry, data lines, thin film transistors, light emitting layers, capacitors, inductors, passive microelectronic elements, active microelectronic elements, or any combination thereof.

In some embodiments, as shown in fig. 1, the substrate 20 has a first surface 20A and a second surface 20B, the second surface 20B being opposite to the first surface 20A. The first conductive layer 41 is disposed on the first surface 20A, and the second conductive layer 42 is disposed on the second surface 20B. The processing unit 10 is disposed on the second surface 20B and electrically connected to the second conductive layer 42. The first connecting portion 30 is at least partially disposed in the substrate 20 and penetrates from the first surface 20A to the second surface 20B. The first conductive layer 41 is electrically connected to the display element layer 50. The processing unit 10 is electrically connected to the first conductive layer 41 through the first connection portion 30, thereby transmitting a signal of the processing unit 10 to the display element layer 50.

Referring to fig. 2A to 2E, fig. 2A to 2E illustrate a process for forming a connection portion penetrating through a substrate in the substrate according to some embodiments of the present invention. The following fabrication process may be applied to form the first connection portion in the substrate according to some embodiments of the present invention. First, referring to fig. 2A, a first carrier substrate 100 is provided, and a plurality of pillars 110 are disposed on the first carrier substrate 100.

Next, referring to fig. 2B, a substrate 120 is deposited on the first carrier substrate 100 by a deposition process such that the pillars 110 protrude from the substrate 120. The material of the substrate 120 may be, for example, glass, a photosensitive material, a polymer resin, or other suitable materials. The substrate 120 may be a rigid substrate or a flexible substrate.

Next, the first carrier substrate 100 provided with the pillars 110 is removed, and a substrate 120 having a plurality of via holes 130A is formed. The substrate 120 is then transferred to another flat second carrier substrate 101, as shown in FIG. 2C.

Next, as shown in fig. 2D, a conductive material is filled into the plurality of via holes 130A by a deposition process to form the first connection portion 130. And a display device layer 140 is formed on the substrate 120. Then, the second carrier substrate 101 is removed.

Finally, as shown in fig. 2E, the processing unit 141 is provided, and the edge of the substrate 120 is bent. According to other embodiments, the edge of the substrate 120 may not be bent. In this embodiment, the substrate 120 has a plurality of first connecting portions 130, and the processing unit 141 can be electrically connected to the display device layer 140 or other electronic devices through the first connecting portions 130.

Referring to fig. 3A to 3F, fig. 3A to 3F illustrate a process for forming a connection portion penetrating through a substrate in the substrate according to some embodiments of the present invention. The following fabrication process may be applied to form the first connection portion in the substrate according to some embodiments of the present invention. First, referring to fig. 3A, a first carrier substrate 100 is provided, and a buffer layer 150 is disposed on the first carrier substrate 100. Buffer layer 150 may be silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

Next, as shown in fig. 3B to fig. 3C, a plurality of conductive pillars 160 are formed on the buffer layer 150 from a conductive material by deposition and photolithography processes. The substrate 120 is formed on the buffer layer 150 by a deposition process and covers the conductive pillar 160. The conductive posts 160 may be metal posts. The substrate 120 may be a rigid substrate or a flexible substrate.

Next, as shown in fig. 3D, the buffer layer 150 and the first carrier substrate 100 are removed, and the substrate 120 is moved to the second carrier substrate 101. The substrate 120 has a plurality of conductive posts 160 therein.

Next, as shown in fig. 3E, a display element layer 140 is fabricated on the substrate 120.

Finally, as shown in fig. 3F, the processing unit 141 is provided, and the edge of the substrate 120 is bent. According to other embodiments, the edge of the substrate 120 may not be bent. In this embodiment, the substrate 120 has a plurality of first connecting portions 160 formed by conductive pillars, and the processing unit 141 can be electrically connected to the display element layer 140 or other electronic elements through the first connecting portions 160.

Referring to fig. 4A-4E, fig. 4A-4E are cross-sectional views of the fabrication process at various stages in forming a blind via 190 and a through via 200 in a substrate, in accordance with some embodiments of the present invention. First, as shown in fig. 4A, a substrate 120 is provided, and the substrate 120 includes an active region 210, a bending region 220, and a gate driving circuit region 230. In some embodiments, the substrate 120 is patterned using a semi-permeable membrane photomask (half-tone mask)180 such that the substrate 120 has blind vias 190 and through vias 200. As shown in fig. 4A, the through hole 200 penetrates through the substrate 120, and the blind via 190 does not penetrate through the substrate 120. In some embodiments, the blind via 190 is disposed in the bending region 220, and the through hole 200 is disposed in the gate driving circuit region 230, but not limited thereto. The depth of the blind hole 190 is not particularly limited, and in some embodiments, the depth of the blind hole 190 is less than half the thickness of the substrate 120.

Next, as shown in fig. 4B to 4C, a conductive material (e.g., a metal material) 240 is deposited into the blind via 190 and the through via 200. In some embodiments, when the conductive material 240 fills the through hole 200 to a half depth, the substrate 120 is flipped over and the deposition of the conductive material 240 is continued until the conductive material 240 fills the through hole 200. As shown in fig. 4C, a first connection portion 240B made of a conductive material filling the through hole 200 and a conductive layer 240A made of a conductive material filling the blind via 190 can be formed. Furthermore, a first conductive layer 251 is formed on the first surface 120A of the substrate 120 as a first conductive pad, and a second conductive layer 252 is formed on the second surface 120B of the substrate 120 as a second conductive pad.

Next, as shown in fig. 4D to 4E, the display element layer 260 is formed on the surface (the first surface 120A) of the substrate 120 on which the first conductive layer 251 is provided, and the processing unit 270 is provided on the surface (the second surface 120B) of the substrate 120 on which the second conductive layer 252 is provided. The display element layer 260 is electrically connected to the first conductive layer 251. The processing unit 270 is electrically connected to the second conductive layer 252.

In some embodiments, the conductive layer 240A, the first connection portion 240B, the first conductive layer 251, and the second conductive layer 250 may be formed of the same conductive material 240. In some embodiments, the conductive material 240 may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys thereof, combinations thereof, or other metal materials with good conductivity.

Fig. 5A is a cross-sectional view of the substrate 120 and the first connection portion 240B according to some embodiments of the invention. As shown in fig. 5A, the first connection portion 240B has a first area a1 along the first surface 120A of the substrate 120 and a second area a2 along the second surface 120B of the substrate. In some embodiments, the first area a1 and the second area a2 are different, for example, the first area a1 is larger than the second area a2, which increases the yield of the first connection manufacturing process and reduces the connection fracture probability.

Fig. 5B is a cross-sectional view of the substrate 120 and the first connection portion 240B according to some embodiments of the invention. As shown in fig. 5B, the first connection portion 240B has a first area A3 along the first surface 120A of the substrate 120 and a second area a5 along the second surface 120B of the substrate. The first area A3 and the second area a5 may be the same or different. The first connection portion 240B has a third area a4 along a reference plane R. According to some embodiments, the reference plane R is located between the first surface 120A and the second surface 120B and is parallel to the first surface 120A. According to some embodiments, the reference plane R may be located at one-half of the distance D between the first surface 120A and the second surface 120B, as shown in fig. 5B. According to some embodiments, the first area A3 and the third area a4 may be different, for example, the first area A3 is larger than the third area a4, which may increase the yield of the first connection manufacturing process and reduce the connection fracture probability.

Referring to fig. 6A, fig. 6A is a cross-sectional view of a display device 5000 according to some embodiments of the present invention. The display device 5000 includes a processing unit 600, a substrate 610, and a display element layer 640. The substrate 610 has a first surface 610A and a second surface 610B, and the second surface 610B is opposite to the first surface 610A. The first surface 610A is generally referred to as the front side of the substrate and the second surface 610B is generally referred to as the back side of the substrate. The display element layer 640 is disposed on the first surface 610A. A first conductive layer 631 is disposed on the first surface 610A, and a second conductive layer 632 is disposed on the second surface 610B. The processing unit 600 is disposed on the second surface 610B and electrically connected to the second conductive layer 632. The first connection portion 620 is at least partially disposed in the substrate 610 and penetrates from the first surface 610A to the second surface 610B. The first conductive layer 631 is electrically connected to the second conductive layer 632 through the first connection part 620, thereby transmitting a signal of the processing unit 600 to the display element layer 640. The processing unit 600 includes, for example, an Integrated Circuit (IC), a microprocessor, a memory device, other signal-processing devices, or any combination thereof.

Referring to fig. 6B, fig. 6B is a top view of the circuit configuration of the display device 5000 shown in fig. 6A according to some embodiments of the present invention. For simplicity, fig. 6B only shows the processing unit 600, the first connection portion 620 and other circuits in the display device layer 640. As shown in fig. 6B, the display element layer 640 includes a gate driving circuit 650 and a data line 670, wherein the gate driving circuit 650 includes a display signal line 650A (e.g., an input signal circuit) extending in a first direction (e.g., a Y direction) and an output signal line 650B (e.g., a scan line) extending in a second direction (e.g., an X direction). The gate driving circuit 650 and the data line 670 are disposed on the first surface 610A. In some embodiments, the processing unit 600 is electrically connected to the display signal line 650A of the gate driving circuit 650 via the plurality of first connection parts 620 and the first conductive layer 631. Thus, the signal of the processing unit 600 is transmitted to the data line 670 extending in the first direction (Y direction) via the output signal circuit 650B of the gate driving circuit 650. In this embodiment, the extending direction of the first connecting portion 620 is perpendicular to the first direction and the second direction.

Fig. 6C is a schematic cross-sectional view taken along line C-C ', fig. 6D is a schematic cross-sectional view taken along line D-D ', and fig. 6E is a schematic cross-sectional view taken along line E-E ' of the display device 5000 shown in fig. 6B. As shown in fig. 6C, a first insulating layer 700 is disposed on the first conductive layer 631, a second insulating layer 690 is disposed on the first insulating layer 700, and a data line 670 is disposed on the second insulating layer 690. As shown in fig. 6D, the second connection portion 651 is at least partially disposed within the first insulating layer 700 and penetrates the first insulating layer 700. The display signal line 650A is disposed on the first insulating layer 700. The gate driving circuit 650 is electrically connected to the first conductive layer 631. For example, the display signal line 650A of the gate driver circuit 650 is electrically connected to the first conductive layer 631 via the second connection portion 651. As shown in fig. 6E, the second connection portion 651 is disposed in the first insulating layer 700 and the second insulating layer 690 and penetrates through the first insulating layer 700 and the second insulating layer 690. The data line 670 is electrically connected to the first conductive layer 631 via the second connection portion 651.

Referring again to fig. 6C, in some embodiments, the (maximum) width of the first conductive layer 631 in the C-C 'direction is greater than the (maximum) width of the first connection portion 620 in the C-C' direction, and the (maximum) width of the second conductive layer 632 in the C-C 'direction is greater than the (maximum) width of the first connection portion 620 in the C-C' direction. The first conductive layer 631 and the second conductive layer 632 can be conductive pads, and have a larger width to ensure the conductive effect. In some embodiments, the position of the processing unit 600 corresponds to the position of the first connection portion 620, for example, when viewed from a direction perpendicular to the first surface 610A of the substrate 610, the processing unit 600 at least partially overlaps the first connection portion 620, and the first connection portion 620 at least partially overlaps the second conductive layer 632 or a portion of the first conductive layer 631.

Fig. 6F is a modification of fig. 6B. As shown in fig. 6F, the display device 5000 further includes a demultiplexer 660 disposed on the first surface 610A and electrically connected to the first conductive layer 631. A signal line from the processing unit 600 may be selectively distributed to one of a plurality of outputs via a demultiplexer 660. For example, as shown in FIG. 6F, one signal line from the processing unit 600 can be selectively allocated to one of three data lines via the demultiplexer 660. Thus, originally, three data lines 670 in fig. 6B need to be matched with three first connection portions 620, and by the design of fig. 6F, three data lines 670 only need to be matched with one first connection portion 620, so that the number of the first connection portions 620 can be reduced. The corresponding cross-sectional view of fig. 6F is similar to that of fig. 6C to 6E, and is not repeated herein.

Referring to fig. 7A, fig. 7A is a cross-sectional view of a display device 6000 according to other embodiments of the present invention. The display device 6000 includes a processing unit 710, a substrate 740, and a display element layer 750. The substrate 740 has a first surface 740A and a second surface 740B, the second surface 740B being opposite to the first surface 740A. The display element layer 750 is disposed on the first surface 740A. A first conductive layer 721 is disposed on the first surface 740A, and a second conductive layer 722 is disposed on the second surface 740B. The processing unit 710 is disposed on the second surface 740B and electrically connected to the second conductive layer 722. The first connection portion 730 is at least partially disposed in the substrate 740 and penetrates from the first surface 740A to the second surface 740B. The first conductive layer 721 is electrically connected to the second conductive layer 722 through the first connection portion 730, so that a signal of the processing unit 710 is transmitted to the display element layer 750.

In this embodiment, the processing unit 710 and the first connection portion 730 do not overlap but are separated from each other as viewed from a direction perpendicular to the first surface 740A of the substrate 740. The processing unit 710 is electrically connected to the first connection portion 730 through the conductive wire 720 and the second conductive layer 722, and the first connection portion 730 is electrically connected to the display element layer 750 through the first conductive layer 721.

Referring to fig. 7B, fig. 7B is a top view of a circuit configuration of a display device 6000 according to some embodiments of the invention, as shown in fig. 7A. For simplicity, fig. 7B only shows the processing unit 710, the conductive lines 720, the first connection portion 730, and other circuits in the display element layer 750. As shown in fig. 7B, the display element layer 750 includes a gate driving circuit 760 and a data line 780, wherein the gate driving circuit 760 includes a display signal line 760A (e.g., an input signal circuit) extending along a first direction (e.g., a Y direction) and an output signal line 760B (e.g., a scan line) extending along a second direction (e.g., an X direction). In some embodiments, the processing unit 710 is connected to the first connection 730 via a plurality of wires 720. In this embodiment, the processing unit 710 is electrically connected to the display signal line 760A of the gate driving circuit 760 through the conductive line 720 and the first connection portion 730 in sequence.

Fig. 7C is a schematic cross-sectional view taken along line F-F ', fig. 7D is a schematic cross-sectional view taken along line G-G ', and fig. 7E is a schematic cross-sectional view taken along line H-H ' of the display device 6000 shown in fig. 7B. As shown in fig. 7D, a first insulating layer 790 is disposed on the first conductive layer 721. The second connection portion 751 is at least partially disposed within the first insulating layer 790 and penetrates the first insulating layer 790. The display signal line 760A is provided on the first insulating layer 790. The gate driver circuit 760 is electrically connected to the first conductive layer 721. For example, the display signal line 760A of the gate driver circuit 760 is electrically connected to the first conductive layer 721 through the second connection portion 751.

As shown in fig. 7E, the second insulating layer 800 is disposed on the first insulating layer 790. The second connection portion 751 is disposed in the first and second insulating

layers

790 and 800 and penetrates the first and second insulating

layers

790 and 800. The data line 780 is electrically connected to the first conductive layer 721 via a second connection portion 751. According to some embodiments, the first connection portion 730 and the second connection portion 751 may at least partially overlap. As shown in fig. 7A and 7C, the first connection portion 730 is not disposed directly above the processing unit 710 when viewed from a direction perpendicular to the substrate 740, and the processing unit 710 is electrically connected to the first connection portion 730 through a wire 720.

Fig. 7F is a modification of fig. 7B. As shown in fig. 7F, the display device 6000 further includes a demultiplexer 770 disposed on the second surface 740B of the substrate 740 and electrically connected to the second conductive layer 722. One signal line from the processing unit 710 may be selectively distributed to one of a plurality of outputs via a demultiplexer 770. For example, as shown in FIG. 7F, a signal line from the processing unit 710 can be selectively distributed to one of three data lines via the demultiplexer 770. Thus, originally, three data lines 780 in fig. 7B need to be matched with three first connecting portions 730, and by the design of fig. 7F, three data lines 780 only need to be matched with one first connecting portion 730, so that the number of the first connecting portions 730 can be reduced. The corresponding cross-sectional view of fig. 6F is similar to that of fig. 6C to 6E, and is not repeated herein.

Referring to fig. 8, fig. 8 is a circuit diagram of demultiplexer 820 according to some embodiments of the present invention. The de-multiplexers 660, 770 in fig. 6F and 7F may have circuits such as the de-multiplexer 820 in fig. 8. The circuit and principle of the demultiplexer in fig. 6F and fig. 7F are similar, and the following description will be made only by taking the case of fig. 6F as an example. As shown in FIG. 8, the processing unit 810 is coupled to the first connections A, B, C, D1, D2 Dn, G1 Gn. The first connection portion A, B, C can be used as a clock generator of the demultiplexer 820, the first connection portion D1 is coupled to the sources of the data lines Y0, Y1, and Y2, and the first connection portion D2 is coupled to the sources of the data lines Y3, Y4, and Y5. In some embodiments, n first connections are coupled to the sources of the data lines, but for simplicity, only the data lines corresponding to the first connections D1 and D2 are shown. The first connections G1-Gn are coupled to the source of the gate driving circuit (not shown). As shown in fig. 8, the first connection portion a is coupled to the gates of the data lines Y0 and Y3, the first connection portion B is coupled to the gates of the data lines Y1 and Y4, and the first connection portion C is coupled to the gates of the data lines Y2 and Y5. In this embodiment, the signal combination of the clock pulse generator (i.e., the first connection A, B, C) can control the switching of the three data lines Y0, Y1 and Y2 by using one first connection D1. Thereby, the number of the first connection portions can be reduced.

According to some embodiments, the processing unit is disposed on a back side of the substrate. According to some embodiments, the processing unit on the back side of the substrate is electrically connected to the display element layer on the front side of the substrate for signal transmission by the first connection portion penetrating through the substrate. Thus, the processing units do not occupy additional area on the front surface of the substrate, thereby forming a narrow-border or borderless (borderless) display device.

Fig. 9 is a top view of a display device 2000 according to some embodiments of the present invention. For clarity of the arrangement of the elements, the display device 2000 shown in fig. 9 only shows the pixel driving circuit 370, the gate driving circuit 290 and the processing unit 270. As shown in fig. 9, the gate driving circuit 290 is disposed at both sides of the display device 2000 and extends along the first direction (Y direction). The processing unit 270 may be disposed at another side of the display device 2000, may be different from the side where the gate driving circuits 290 are disposed, may be disposed between the two gate driving circuits 290, and may extend along the second direction (X direction). Fig. 9 shows two gate driving circuits. However, it is obvious to those skilled in the art that the display device 2000 may include only one gate driving circuit.

Referring to fig. 10A, fig. 10A is a schematic cross-sectional view of the display device 2000 shown in fig. 9 according to some embodiments. As shown in fig. 10A, the gate driving circuit 290 is disposed on the substrate 120 and disposed on both sides of the substrate 120. In some embodiments, the pixel driving circuit 370 and the gate driving circuit 290 are located at different layers, for example, the gate driving circuit 290 and the pixel driving circuit 370 may be disposed on the first surface 120A of the substrate 120, and the pixel driving circuit 370 is disposed above the gate driving circuit 290. In this embodiment, the space 300 between the gate driving circuit 290, the substrate 120 and the pixel driving circuit 370 can be used for disposing the circuit of other electronic components. In some embodiments, the space 300 may be used to arrange touch or sensing circuits.

Referring to fig. 10B, fig. 10B is a schematic cross-sectional view of the display device 2000 shown in fig. 9 along a line B-B' according to some embodiments. As shown in fig. 10B, the processing unit 270 is disposed on the second surface 120B of the substrate 120. In some embodiments, the processing unit 270 may at least partially overlap the first connection portion 240B. For example, the processing unit 270 is disposed directly below the first connection portion 240B, the first conductive layer 251, and the second conductive layer 252. In other embodiments, the processing unit 270 is not disposed directly below the first connection portion 240B, and the processing unit 270 may be electrically connected to the first connection portion 240B through an additional wire (not shown). For example, fig. 10B may take the form of fig. 7A, with the processing unit 710 electrically connected to the first connection portion 730 via the wire 720. That is, in fig. 10B, the processing unit 270 may be electrically connected to the first connection portion 240B through a conductive line (not shown) similar to the conductive line 720 and the second conductive layer 252. According to some embodiments, the processing unit 270 disposed on the second surface 120B of the substrate may be electrically connected to the gate driving circuit 290 disposed on the first surface 120A of the substrate through the first connection portion 240B. According to some embodiments, the processing unit 270 disposed on the second surface 120B of the substrate may be electrically connected to the touch circuit or the sensing circuit disposed on the first surface 120A of the substrate through the first connection portion 240B. The touch circuit or the sensing circuit may be disposed in the space 300.

According to some embodiments, the gate driving circuit 290 and the pixel driving circuit 370 at least partially overlap. With this arrangement, the gate driving circuit 290 does not occupy an additional area on the substrate, and thus the display device 2000 having a narrow boundary or no boundary can be formed. According to some embodiments, the processing unit 270 is disposed on the second surface 120B of the substrate 120 without occupying the area of the first surface 120A of the substrate 120, and thus the display device 2000 having a narrow boundary or no boundary may be formed.

Referring to fig. 11A, fig. 11A is a detailed circuit diagram of a portion 2000P of the display device of fig. 10A according to an embodiment of the present invention. Fig. 11A shows only a part 2000P of the display device 2000, and the part 2000P includes a portion of the gate driver circuit 290, the pixel driver circuit 370, and the light emitting element 550. The gate driving circuit 290, the pixel driving circuit 370, and the light emitting element 550 may be disposed on the first surface 120A of the substrate 120. The pixel driving circuit 370 may include thin film transistors T1, T2, T3. T1 may be a switch transistor, T2 may be a drive transistor, and T3 may be a reset (reset) transistor. The gate driving circuit 290 may include an output transistor T4. Fig. 11A shows only three transistors in the pixel drive circuit 370. Those skilled in the art will appreciate that the pixel driving circuit may comprise more transistors according to actual requirements.

The first conductive layer 251 is disposed on the first surface 120A of the first substrate 120. The second conductive layer 252 and the processing unit 270 are disposed on the second surface 120B of the first substrate 120. The first conductive layer 251 may include a first portion 251a and a second portion 251 b. The first portion 251a may be located below the output transistor T4, and may be used for shielding the semiconductor layer 303 in the T4. The second portion 251B of the first conductive layer 251 may be located at a corresponding position of the first connection portion 240B, and electrically connected to the processing unit 270 through the first connection portion 240B. According to some embodiments, the first portion 251a and the second portion 251b may be the same layer. In the present specification, the meaning that the a layer and the B layer are the same layer means that the a layer and the B layer can be patterned by the same manufacturing process using the same material. That is, the first portion 251a and the second portion 251b may be patterned using conductive layers of the same material by the same fabrication process.

In fig. 11A, the processing unit 270 is located at a corresponding position of the first connection portion 240B, that is, the processing unit 270 at least partially overlaps the first connection portion 240B. However, according to other embodiments, the processing unit 270 may not overlap the first connection portion 240B. For example, as shown in fig. 7A, the processing unit 270 may be electrically connected to the first connection portion 240B through another conductive wire (not shown, similar to the conductive wire 720 of fig. 7A) and the second conductive layer 252.

The insulating layer 320 is on the first conductive layer 251. The output transistor T4 is located on the insulating layer 320, and includes a semiconductor layer 303, a gate layer 350, and a source/drain layer 306 SD. The semiconductor layer 303 is located on the insulating layer 320, the insulating layer 325A is located between the semiconductor layer 303 and the gate layer 350, and the insulating layer 325B is located between the gate layer 350 and the source/drain layer 306 SD. Semiconductor layer 303 may include channel region 340 and doped region 330.

According to some embodiments, the transistors in the gate driving circuit 290 and the transistors in the pixel driving circuit 370 may have the same layer. For example, in fig. 11A, the source/drain layer 306SD of the output transistor T4 and the gate 306G of T1, T2, T3 in the pixel driving circuit 370 may be the same layer. That is, the source/drain 306SD of the transistor T4 and the gate 306G of the transistors T1, T2, T3 may be patterned from conductive layers of the same material by the same fabrication process.

T4 may be electrically connected with the switching transistor T1 to output the signal of the gate driving circuit 290 to T1. The switching transistor T1 may be electrically connected with the driving transistor T2. In fig. 11A, the transistor T4 in the gate driving circuit 290 is shown as a top-gate transistor, and the transistors T1, T2 and T3 in the pixel driving circuit 370 are shown as bottom-gate transistors. However, the present invention is not limited thereto. T4 may also be a bottom gate transistor, T1, T2, T3 may also be a top gate transistor. The active layers in T1, T2, T3, and T4 may be semiconductors, such as amorphous silicon, polysilicon, and metal oxides. An example of the metal oxide may be Indium Gallium Zinc Oxide (IGZO). According to some embodiments of the invention, the active layer 400 in T1, T2, T3 may be IGZO and the active layer 303 in T4 may be polysilicon.

The light emitting element 550 may be disposed on the pixel driving circuit 370. The insulating

layers

410, 430 may be positioned between the light emitting element 550 and the pixel driving circuit 370. The light-emitting element 550 includes a first electrode 440, a light-emitting layer 450, and a second electrode 460. The light emitting layer 450 is disposed between the first electrode 440 and the second electrode 460, and is located in the opening of the pixel defining layer 435. The second electrode may cover the pixel defining layer 435. The first electrode 440 may be an anode and the second electrode 460 may be a cathode. Alternatively, the first electrode 440 may be a cathode and the second electrode 460 may be an anode. The first electrode 440 of the light emitting element 550 may be electrically connected to the driving transistor T2 through a contact hole 550C (which may be located in the insulating layers 410, 430).

In some embodiments, light-emitting layer 450 may comprise an organic light-emitting diode layer, such that display device 2000 constitutes an organic light-emitting diode display device. In some embodiments, light-emitting layer 450 may comprise an inorganic light-emitting diode layer, which may comprise micro light-emitting diodes, for example, such that display device 2000 constitutes a micro light-emitting diode display device.

Referring to fig. 11B, fig. 11B is a top view of a portion (2000P) of the display device shown in fig. 11A. Fig. 11B shows only the gate driver circuit 290, the pixel driver circuit 370, the light-emitting layer 450, and the substrate 120 in blocks to clearly show the positional relationship therebetween. Fig. 11B shows only a part of the pixel drive circuit 370. The projection of the gate driving circuit 290 on the first surface 120A of the substrate 120 is defined as a first projection P1, the projection of the pixel driving circuit 370 on the first surface 120A is defined as a second projection P2, and the projection of the light emitting layer 450 on the first surface 120A is defined as a third projection P3. In some embodiments, as shown in fig. 11B, in a portion 2000P of the display device, the first projection P1 at least partially overlaps the second projection P2. In some embodiments, the third projection P3 at least partially overlaps the second projection P2, and the first projection P1 and the third projection P3 are separated from each other.

Referring to fig. 12, fig. 12 shows a detailed circuit of a portion 2000P of the display device of fig. 10A, in accordance with further embodiments of the present invention. Fig. 12 is a modification of fig. 11A, and differs from fig. 11A in that the display device is further provided with a conductive portion 350A between the insulating

layers

325A and 325B. The gate driving circuit 290 may be electrically connected to the reset transistor T3 through the conductive portion 350A and the contact hole 360C (located in the insulating layer 325B). The conductive portions 350A and the gate layer 350 of the output transistor T4 may be the same layer.

Referring to fig. 13, fig. 13 shows a detailed circuit of a portion 2000P of the display device of fig. 10A, in accordance with further embodiments of the present invention. Fig. 13 shows a variation of fig. 11A, which is different from fig. 11A in that the gate 308G of the driving transistor T2 and the gate 306G of the reset transistor T3 are different layers, and an insulating layer 691 separates the gate 308G and the gate 306G. An insulating layer 692 is between the active layer 400 and the gate 308G. The gate 306G of the reset transistor T3 and the source/drain 306SD of the output transistor T4 may be the same layer.

Referring to fig. 14A, fig. 14A shows a detailed circuit of a portion 2000P of the display device of fig. 10A, in accordance with further embodiments of the present invention. Fig. 14A is a modification of fig. 11A, and differs from fig. 11A in that the position of the light-emitting layer 450 at least partially overlaps with the gate driver circuit 290, and the position of the light-emitting layer 450 and the pixel driver circuit 370 are separated from each other. That is, the third projection P3 at least partially overlaps the first projection P1, and the third projection P3 and the second projection P2 are separated from each other, as shown in the top view of fig. 14B.

Referring to fig. 15A, fig. 15A shows a detailed circuit of a portion 2000P of the display device of fig. 10A, in accordance with further embodiments of the present invention. Fig. 15A is a variation of fig. 11A, and differs from fig. 11A in that the pixel driving circuit region 370 may overlap with the light emitting layer 450 and the gate driving circuit 290 at the same time. That is, at least a portion of the first projection P1, the second projection P2, and the third projection P3 overlap, as shown in the top view of fig. 15B.

Referring to fig. 16, fig. 16 is a partial cross-sectional view of a display device 4000 according to some embodiments of the invention. The display device 4000 is a touch display device. Fig. 16 has similar elements to those in fig. 11A, for example, the display device 4000 in fig. 16 includes a pixel driving circuit 370, a light emitting element 550, a processing unit 270, a first connecting portion 240B, a first conductive layer 251, a second conductive layer 252, and the like, which are not described herein again. The pixel driving circuit 370 may include, for example, a switch transistor T1, a driving transistor T2, and a reset transistor T3, which are not described herein again. As shown in fig. 16, the display device 4000 further includes an encapsulation layer 500, a touch electrode 510A, a touch signal line 510B, and a touch transmitting portion 520. The touch electrode 510A is located in the touch area 4000A of the display device 4000, and the touch signal line 510B and the touch transmitting portion 520 are located in the peripheral area (non-touch area) 4000B of the display device 4000.

The encapsulation layer 500 is disposed over the light emitting element 550, and the touch electrode 510A and the touch signal line 510B are disposed on the encapsulation layer 500. The encapsulation layer 500 may include a multi-layer structure, such as a structure including an inorganic layer/an organic layer/an inorganic layer. The touch electrode 510A and the touch signal line 510B are disposed on the first surface 120 of the substrate 120, and the touch electrode 510A is electrically connected to the first conductive layer 251 through the touch signal line 510B and the touch transmitting portion 520. Thus, the processing unit 270 can perform signal transmission with the touch signal line 510B through the first connection portion 240B and the touch transmission portion 520.

The touch electrode 510A and the touch signal line 510B may be the same material or may be different materials. The materials of the touch electrode 510 and the touch signal line 510B may include Indium Tin Oxide (ITO), tin oxide (SnO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Antimony Tin Oxide (ATO), Antimony Zinc Oxide (AZO), a metal, or a combination thereof.

The touch transmission 520 may include a first touch transmission 306A, a second touch transmission 380A, and a third touch transmission 440A. In some embodiments, the first touch transmitting portion 306A, the second touch transmitting portion 380A and the third touch transmitting portion 440A may be the same layer as an electrode layer of a transistor in the pixel driving circuit 370, or may be the same layer as an electrode layer in the light emitting element 550, so as to simplify the manufacturing process. For example, as shown in fig. 16, the first touch transmitting part 306A may be the same layer as the gate 306G of the transistor (T1, T2, or T3) in the pixel driving circuit 370, and the second touch transmitting part 380A may be the same layer as the source/drain 380SD of the transistor (T1, T2, or T3). The third touch transmitting portion 440A may be the same layer as the first electrode 440 in the light emitting element 550. The touch electrode 510A is electrically connected to the first conductive layer 251 through the touch signal line 510B and the touch transmitting portion 520.

Referring to fig. 17, fig. 17 is a cross-sectional view of a display device 4000 according to further embodiments of the present invention. Fig. 17 is a variation of fig. 16, and differs from fig. 16 in that the display device 4000 of fig. 17 further includes a touch signal line 530 and a connection portion 530A. The touch signal line 530 may be disposed between the insulating layer 325A and the insulating layer 325B, and the connection portion 530A may penetrate the insulating layer 325A and the insulating layer 320. The touch electrode 510A is electrically connected to the first conductive layer 251 via a touch signal line 510B, a touch transmitting portion 520, a touch signal line 530, and a connecting portion 530A.

Referring to fig. 18, fig. 18 is a cross-sectional view of a display device 4000 according to further embodiments of the present invention. Fig. 18 is a variation of fig. 16, and the difference from fig. 16 is that, as shown in fig. 18, the display device 4000 further includes a conductive ink 540 disposed between the touch signal line 510B and the third touch transmitting portion 440A. The conductive ink 540 may extend through the encapsulation layer 500 and a portion of the pixel definition layer 435.

According to some embodiments, the processing unit is disposed on a back side of the substrate. According to some embodiments, the processing unit on the back side of the substrate is electrically connected to the display element layer or the touch electrode layer on the front side of the substrate for signal transmission by the first connection portion penetrating through the substrate. In this way, the processing unit does not occupy an additional area on the front surface of the substrate, and thus a display device with a narrow boundary or no boundary can be formed. According to some embodiments, the gate driving circuit and the pixel driving circuit at least partially overlap. Thus, the gate driving circuit does not occupy an additional area on the substrate, and thus a display device having a narrow boundary or no boundary can be formed.

Although embodiments of the present invention and their advantages have been disclosed, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, or steps described in the specification. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes combinations of the respective claims and embodiments.

Claims

1. A display device, comprising:

a substrate having a first surface and a second surface, the second surface being opposite to the first surface;

a first conductive layer disposed on the first surface;

a second conductive layer disposed on the second surface;

the processing unit is arranged on the second surface and is electrically connected with the second conducting layer;

the first connecting part is at least partially arranged in the substrate and penetrates from the first surface to the second surface, and the first conducting layer is electrically connected with the second conducting layer through the first connecting part;

a touch electrode disposed on the first surface;

a touch transmission part, wherein the touch electrode is electrically connected with the first conductive layer through the touch transmission part;

a pixel driving circuit disposed on the first surface;

a pixel defining layer; and

and the touch transmission part penetrates through the pixel definition layer or the insulating layer.

2. The display device of claim 1, further comprising: a demultiplexer disposed on the first surface and electrically connected to the first conductive layer.

3. The display device of claim 1, further comprising: a demultiplexer disposed on the second surface and electrically connected to the second conductive layer.

4. The display device of claim 1, further comprising: and a gate drive circuit arranged on the first surface and electrically connected with the first conductive layer.

5. The display device of claim 4, further comprising: and a display signal line disposed on the first surface, wherein the gate driving circuit is electrically connected to the first conductive layer via the display signal line.

6. The display device of claim 5, further comprising:

a first insulating layer disposed on the first conductive layer; and

a second connecting portion at least partially disposed in the first insulating layer and penetrating the first insulating layer,

the display signal line is arranged on the first insulating layer and is electrically connected with the first conductive layer through the second connecting part.

7. The display device according to claim 6, wherein the processing unit at least partially overlaps the first connection portion.

8. The display device according to claim 6, wherein the first connection portion and the second connection portion at least partially overlap.

9. The display device of claim 4, wherein the gate driving circuit has a first projection on the first surface, the pixel driving circuit has a second projection on the first surface, and the first projection and the second projection at least partially overlap.

10. The display device of claim 9, further comprising: and the light-emitting element is arranged on the first surface and comprises a light-emitting layer, and the light-emitting layer has a third projection on the first surface.

11. The display device of claim 10, wherein the second projection and the third projection at least partially overlap, and the first projection and the third projection are separated from each other.

12. The display apparatus of claim 10, wherein at least a portion of the first projection, the second projection, and the third projection overlap.

13. The display device according to claim 1, wherein the first connection portion has a first area along the first surface and a second area along the second surface, the first area and the second area being different.

14. The display device as set forth in claim 1,

the first connecting portion has a first area along the first surface, the first connecting portion has a third area along a reference plane, the reference plane is located between the first surface and the second surface and parallel to the first surface, and the first area and the third area are different.

15. The display device of claim 1, further comprising:

a light emitting element;

the packaging layer is arranged between the light-emitting element and the touch electrode; and

wherein the touch transmission part penetrates through the packaging layer.

16. The display device according to claim 1, wherein the touch electrode is located in a touch area, and the touch transmitting part is located in a non-touch area.

17. The display device of claim 1, the pixel driving circuit further comprising:

and the grid electrode, wherein the touch transmission part comprises a first touch transmission part, and the first touch transmission part and the grid electrode are in the same layer.

18. The display device of claim 1, the pixel driving circuit further comprising:

and a source/drain, wherein the touch transmission part comprises a second touch transmission part, and the second touch transmission part and the source/drain are in the same layer.