CN107578795A - A kind of flash memory device for avoiding data from disturbing - Google Patents
A kind of flash memory device for avoiding data from disturbing Download PDFInfo
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Abstract
The invention provides a kind of flash memory device for avoiding data from disturbing, applied to the reparation of flash memory device, wherein storage array includes multiple memory cell, wherein, flash memory device includes, data-reading unit, to the reading data in corresponding memory cell in lasting reading storage array and exports；Data repair address and form unit, and storage address corresponding to the reading data being read is formed to lasting；Data detecting unit, to be detected to reading data, read with detection and disturbed corresponding to data in storage address with the presence or absence of data and export testing result；Controller, the storage address corresponding to locking when data interference in storage address be present；Controller carries out data ELIMINATION OF ITS INTERFERENCE operation to the memory cell corresponding to locked storage address.The beneficial effect of its technical scheme is, can detect memory cell with the presence or absence of interference, and repairs operation or data write-in reparation operation to current memory cell progress data erasing in interference.
Description
Technical field
The present invention relates to technical field of data storage, more particularly to a kind of flash memory device for avoiding data from disturbing.
Background technology
Memory (Memory) is to be used to protect stored memory device in modern information technologies, and it is widely used in pen
Note originally, on smart mobile phone and various terminal equipment, includes non-volatile flash memory device again wherein in the classification of memory, non-
The multiple memory cell lined up on the model that the flash memory device of volatibility is made up of wordline (WL) and bit line (BL), it
Non-transformer can also maintain to have stored data in the case of supplying.This flash memory device can carry out number repeatedly to memory cell
According to programming operation and data erasing operation.And data program operation or data erasing operation process are being performed to memory cell
In, reduction that may be to the threshold voltage of no selected memory cells or no selected unprogrammed storage
The rise of the threshold voltage of unit and caused " data interference " phenomenon, and then influence the normal use of flash memory device.
The content of the invention
For the above mentioned problem existing for memory cell is programmed or wiped in the prior art, a kind of purport is now provided
Detected to the memory cell do not wiped or programmed, avoid the disturbed flash memory device of data.
Concrete technical scheme is as follows：
A kind of flash memory device for avoiding data from disturbing, applied to the reparation of flash memory device, the flash memory device includes storage
Array, the storage array include multiple memory cell, and each memory cell corresponds to a storage address, its feature respectively
It is, the flash memory device includes：
Data-reading unit, it is connected with the storage array, to corresponding described in the lasting reading storage array
Reading data in memory cell, and by the reading data output；
Data repair address and form unit, and institute corresponding to data is read to the lasting memory cell being read that formed
State storage address；
Data detecting unit, it is connected with the data-reading unit, to be detected to the reading data, with detection
Disturbed corresponding to the reading data in the storage address with the presence or absence of data, and to export testing result；
Controller, repair address with data respectively and form unit, the data detecting unit and the digital independent list
Member connection, the controller are described corresponding to locking when the testing result represents data interference to be present in the storage address
Storage address；
The controller carries out data ELIMINATION OF ITS INTERFERENCE to the memory cell corresponding to the locked storage address
Operation.
Preferably, when data interference be present in the storage address that the testing result represents corresponding, the control
Device processed sends a locking signal to the data and repairs address formation unit；
The data repair address and form unit according to the locking signal, to be carried out to the current storage address
Locking, and the locked storage address is sent to the controller；
Controller memory cell according to corresponding to the testing result and the locked storage address
Carry out erasing and repair operation or write-in reparation operation, to realize that the data ELIMINATION OF ITS INTERFERENCE operates.
Preferably, the data-reading unit includes：
Column decoder, it is connected with the controller, to the corresponding life of decoding column address exported according to the controller
Into a selection signal；
Sense amplifier, one end are connected with the column decoder, and the other end is connected with the storage array, to according to institute
The reading data preserved corresponding to selection signal reading in the storage address are stated, and by the data output that reads to institute
State data detecting unit.
Preferably, the controller to the data detection device obtain it is described reading data after, output one first
Drive signal and one second drive signal；
The data detection device includes：
First data validator, one end are connected with the data-reading unit, and the other end is connected with the controller, are being connect
Receive after the controller exports first drive signal or second drive signal and be activated；
First register, it is connected with first data validator, described the after being activated by first drive signal
One data validator by it is described reading data compared with default first reference voltage, to export one first comparative result
And it is stored in first register；
Second register, it is connected with first data validator, described the after being activated by second drive signal
One data validator by it is described reading data compared with default second reference voltage, to export one second comparative result
And it is stored in two register；
First data comparator, described first data comparator one end and first register and second deposit
Device is connected, and the other end is connected with the controller；
The controller compares to preserve described first respectively in first register and second register
As a result and after second comparative result, one first comparison signal of output is to first data comparator, with described in activation
First data comparator；
The controller after being activated, to meet that the reading data are more than described the in first comparative result
One reference voltage, and described in second comparative result meets that the reading data are formed when being less than second reference voltage
Testing result, and the testing result is exported to the controller, the testing result is representing to depositing described in current
Storage unit write the operation signal of reparation.
Preferably, the controller to the data detection device obtain it is described reading data after, output one first
Drive signal and one the 3rd drive signal；
The data detection device includes：
Second data validator, one end are connected with the data-reading unit, and the other end is connected with the controller, are being connect
Receive controller output first drive signal or the 3rd drive signal after be activated；
One or three register, it is connected with second data validator, described in after being activated by first drive signal
Second data validator is detected the reading data to generate one the 3rd testing number with default first reference voltage
According to, and the described 3rd detection data are stored in the 3rd register；
4th register, it is connected with second data validator, described the after being activated by the 3rd drive signal
Two data validators are detected the reading data with default 3rd reference voltage to generate one the 4th detection data,
And the described 4th detection data are stored in the 4th register；
Second data comparator, described second data comparator one end and the 3rd register and the 4th deposit
Device is connected, and the other end is connected with the controller；
The controller compares to preserve the described 3rd respectively in the 3rd register and the 4th register
As a result one second comparison signal is exported and after the 4th comparative result to second data comparator, to activate described the
Two data comparators；
Second data comparator after activation in the 3rd comparative result meeting that the reading data are less than
First reference voltage, and second comparative result meets shape when the reading data are more than second reference voltage
Exported into the testing result, and by the testing result to the controller, the testing result is representing to current
The memory cell wipe the operation signal of reparation.
Preferably, first reference voltage is the erasing voltage higher than the flash cell, and is less than the flash memory
The write-in voltage of unit；And/or
Second reference voltage be higher than first reference voltage, and less than the flash cell said write
Voltage.
Preferably, the 3rd reference voltage is less than first reference voltage.
Preferably, the storage array includes tactic bit line and tactic wordline is formed；
The memory cell is formed by a wordline and a bit line, and each the memory cell is described
Bit line is connected with the sense amplifier, the sense amplifier to pass through the bit line read corresponding to the memory cell
In the reading data.
Preferably, in addition to a line decoder, described line decoder one end are connected with the controller, the other end with it is each
The wordline connection of the memory cell；
The controller is to according to the locked storage address one word line position signal of output to the row decoding
Device, the bit line of line decoder memory cell according to corresponding to the word line position signal activation；
The further controller carries out the erasing to the memory cell of activation according to the testing result and repaiied
Multiple operation carries out said write reparation operation.
Above-mentioned technical proposal has the following advantages that or beneficial effect：Data inspection can be carried out to the memory cell in storage array
Survey, and then judge current memory cell with the presence or absence of interference, and the current memory cell is carried out when storing and disturbing
Operation is repaired in data erasing or operation is repaired in data write-in, avoids the data of memory cell from being disturbed.
Brief description of the drawings
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is a kind of structural representation of the embodiment for the flash memory device for avoiding data from disturbing of the present invention；
Fig. 2 is the flow on data detection device in a kind of flash memory device embodiment for avoiding data from disturbing of the present invention
Figure；
Fig. 3 is the flow on data detection device in a kind of flash memory device embodiment for avoiding data from disturbing of the present invention
Figure；
Fig. 4 is relation between the first reference voltage, the second reference voltage and the 3rd reference voltage in the embodiment of the present invention
Schematic diagram.
Reference represents：
1st, storage array；2nd, data-reading unit；3rd, data repair address and form unit；4th, data detecting unit；5th, control
Device processed；6th, column decoder；
21st, the first data validator；22nd, the first register；23rd, the second register；24th, the first data comparator；
25th, cowherb data validator；26th, the 3rd register；27th, the 4th register；28th, the second data comparator.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained on the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as limiting to the invention.
Technical scheme includes a kind of flash memory device for avoiding data from disturbing.
As shown in figure 1, a kind of embodiment for the flash memory device for avoiding data from disturbing, applied to the reparation of flash memory device, institute
Stating flash memory device includes storage array 1, and the storage array 1 includes multiple memory cell, and each memory cell is right respectively
Answer a storage address, it is characterised in that the flash memory device includes：
Data-reading unit 2, it is connected with the storage array 1, to corresponding to lasting read in the storage array 1
Reading data in memory cell, and data output will be read；
Data repair address and form unit 3, and storage corresponding to data is read to the lasting memory cell being read that formed
Address (RFBKADD)；
Data detecting unit 4, it is connected with data-reading unit 2, to be detected to reading data, to detect reading number
Disturbed according to whether there is data in corresponding storage address, and to export testing result；
Controller 5, address formation unit 3, data detecting unit 4 and data-reading unit 2 are repaired with data respectively and is connected
Connect, the storage address corresponding to locking when testing result represents data interference to be present in storage address of controller 5；
Controller 5 carries out data ELIMINATION OF ITS INTERFERENCE operation to the memory cell corresponding to locked storage address.
Wiped or programmed for the memory cell of the prior art in storage array 1 and during write operation,
The problem of causing data to disturb the memory cell for not carrying out write operation or the memory cell for not carrying out erasing operation；
In the present invention, data are read by being obtained in memory cell of the data-reading unit 2 in storage array 1, and will
Data output is read to data detecting unit 4, data detecting unit 4 to reading data by being detected and being exported detection knot
Fruit, wherein the purpose detected is to judge that memory cell corresponding to current storage address is disturbed with the presence or absence of data；
Wherein data are repaired address formation unit 3 and deposited to lasting formed corresponding to the memory cell being read reading data
Store up address；
If when interference be present, repair address and form unit and locked current storage address, and by the storage of locking
Address exports to controller 5, controller 5 and finds corresponding memory cell, and further basis according to locked storage address
Testing result carries out erasing reparation operation to the memory cell or progress data write-in is repaired and operated.
Such scheme can avoid data interference problem existing for the memory cell not wiped or programmed.
In a kind of preferably embodiment, data interference be present in the storage address that testing result represents corresponding
When, controller 5 sends a locking signal to data and repairs address formation unit 3；
Data repair address and form unit 3 according to locking signal, to be locked to current storage address, and will be by
The storage address of locking is sent to controller 5；
The memory cell according to corresponding to testing result and locked storage address of controller 5 carries out erasing and repairs operation
Or operation is repaired in write-in, to realize that data ELIMINATION OF ITS INTERFERENCE operates.
In above-mentioned technical proposal, the locking signal of generation also can be just in the state that data reparation address formation unit 3 powers off
Often preserve.
In a kind of preferably embodiment, data-reading unit 2 includes：
Column decoder 6, it is connected with controller 5, the decoding column address (CADD) to be exported according to controller 5 corresponds to
Generate a selection signal (YSEL)；
Sense amplifier, one end are connected with column decoder 6, and the other end is connected with storage array 1, to according to selection signal
The reading data preserved corresponding to reading in storage address, and data output will be read to data detecting unit 4.
In above-mentioned technical proposal, the selectable output decoding column address of controller 5 is read with final control data reading unit 2
Reading data in memory cell corresponding to taking.
In a kind of preferably embodiment,
Controller 5 to after data detection device obtains and reads data (SNDAT), export one first drive signal and
One second drive signal；
As shown in Fig. 2 data detection device includes：
First data validator 21, one end are connected with data-reading unit 2, and the other end is connected with controller 5, are controlled receiving
Device 5 processed is activated after exporting the first drive signal (XCON1) or the second drive signal (XCON2)；
First register 22, it is connected with the first data validator 21, the first data after being activated by the first drive signal are true
Data will be read compared with default first reference voltage (VREF1) by recognizing device 21, to export one first comparative result simultaneously
It is stored in the first register 22；
Second register 23, it is connected with the first data validator 21, the first data after being activated by the second drive signal are true
Data will be read compared with default second reference voltage (VREF2) by recognizing device 21, to export one second comparative result simultaneously
It is stored in two registers；
First data comparator 24, the one end of the first data comparator 24 connect with the first register 22 and the second register 23
Connect, the other end is connected with controller 5；
Controller 5 preserving the first comparative result and second respectively in the first register 22 and the second register 23
After comparative result, one first comparison signal (XCOND) to the first data comparator 24 is exported, to activate the first data comparator
24；
Controller 5 after being activated, to meet that reading data is more than the first reference voltage in the first comparative result, and
Second comparative result, which meets to read when data are less than the second reference voltage, forms testing result (XDET1), and testing result is defeated
Go out to controller 5, testing result is representing current memory cell write the operation signal of reparation.
In a kind of preferably embodiment, the first reference voltage is the erasing voltage higher than flash cell, and is less than
The write-in voltage of flash cell.
The second reference voltage is higher than the first reference voltage in a kind of preferably embodiment, and is less than flash cell
Write-in voltage.
In above-mentioned technical proposal, it is the storage list that data-reading unit 2 reads the reading data obtained from memory cell
The current magnitude of voltage of member；
In above-mentioned technical proposal, the first register 22 is forming when the magnitude of voltage of reading is more than the first reference voltage
First comparative result is that the first signal is for example represented with 1；
If the voltage read is secondary signal for example with 0 to the first reference voltage, the first comparative result formed is less than
Represent；
Second register 23 is to the second comparative result formed when the magnitude of voltage of reading is less than the second reference voltage
First signal is for example represented with 1；
If the magnitude of voltage read to being more than the second reference voltage, the second comparative result formed for secondary signal for example with
0 represents；
Data comparator to the first register 22 and the second register 23 output be the first signal (1.1) when,
For the magnitude of voltage of storage element now between the first reference voltage and the second reference voltage, the testing result of formation is to working as
Preceding memory cell write the operation signal of reparation；
If output does not export testing result for (1.0), (0.1) or (0.1), that is, represent current memory cell not
It is disturbed.
In a kind of preferably embodiment, as shown in figure 3, controller 5 reads number to be obtained in data detection device
After (SNDAT), one first drive signal (XCON1) and one the 3rd drive signal (XCON3) are exported；
Data detection device includes：
Second data validator 25, one end are connected with data-reading unit 2, and the other end is connected with controller 5, are controlled receiving
It is activated after the first drive signal or the 3rd drive signal that device 5 processed exports；
One or three register, it is connected with the second data validator 25, the second data after being activated by the first drive signal are true
Recognize device 25 to be detected reading data to generate one the 3rd detection data with default first reference voltage (VREF1), and
3rd detection data are stored in the 3rd register 26；
4th register 27, it is connected with the second data validator 25, the second data after being activated by the 3rd drive signal are true
Recognize device 25 to be detected reading data to generate one the 4th detection data with default 3rd reference voltage (VREF3), and
4th detection data are stored in the 4th register 27；
Second data comparator 28, the one end of the second data comparator 28 connect with the 3rd register 26 and the 4th register 27
Connect, the other end is connected with controller 5；
Controller 5 preserving the 3rd comparative result and the 4th respectively in the 3rd register 26 and the 4th register 27
One second comparison signal (XCOND) to the second data comparator 28 is exported after comparative result, to activate the second data comparator
28；
The second data comparator 28 after activation is electric to meet that reading data are less than the first benchmark in the 3rd comparative result
Pressure, and the second comparative result meets to read formation testing result (XDET2) when data are more than the second reference voltage, and will detection
As a result export to controller 5, testing result is representing current memory cell wipe the operation signal of reparation.
In a kind of preferably embodiment, the 3rd reference voltage is less than the first reference voltage.
As shown in figure 4, represent the first reference voltage (VREF1), the second reference voltage (VREF2) and the 3rd reference voltage
(VREF3) relation between.
In above-mentioned technical proposal, the 3rd register 26 is forming when the magnitude of voltage of reading is less than the first reference voltage
3rd comparative result is that the first signal is for example represented with 1；
If the voltage read is secondary signal for example with 0 to the first reference voltage, the 3rd comparative result formed is more than
Represent；
4th register 27 is to the 4th comparative result formed when the magnitude of voltage of reading is more than three reference voltages
First signal is for example represented with 1；
If the magnitude of voltage read to being less than the 3rd reference voltage, the 4th comparative result formed for secondary signal for example with
0 represents；
Data comparator to the 3rd register 26 and the 4th register 27 output be the first signal (1.1) when,
For the magnitude of voltage of storage element now between the 3rd reference voltage and the first reference voltage, the testing result of formation is to working as
Preceding memory cell wipe the operation signal of reparation；
If output does not export testing result for (1.0), (0.1) or (0.1), that is, represent current memory cell not
It is disturbed.
In a kind of preferably embodiment, storage array 1 includes tactic bit line and tactic wordline
Formed；
Memory cell is formed by a wordline and a bit line, and bit line and the sense amplifier of each memory cell connect
Connect, sense amplifier is to the reading data in memory cell corresponding to being read by bit line.
In a kind of preferably embodiment, in addition to a line decoder, line decoder one end are connected with controller 5, separately
One end is connected with the wordline of each memory cell；
Controller 5 according to storage address to export a word line position signal to line decoder, and line decoder is according to wordline
The bit line of memory cell corresponding to position signalling activation；
Further controller 5 carries out erasing to the memory cell of activation according to testing result and repairs operation or enter row write
Enter to repair operation.
In above-mentioned technical proposal, when the testing result that controller 5 receives is to memory cell write the operation of reparation
During signal, controller 5 generates a locking signal (XTRF) to data and repairs address formation unit 3, and data repair address and form list
Member 3 locks current storage address according to the locking signal, and the storage address of locking is exported to controller 5, controller 5
Corresponding memory cell is found according to storage address, and the operation letter that further write-in according to corresponding to testing result is is repaired
Number, grid-control voltage corresponding to generation carries out write-in to corresponding memory cell and repairs operation.
Preferred embodiments of the present invention are the foregoing is only, not thereby limit embodiments of the present invention and protection model
Enclose, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Scheme obtained by equivalent substitution and obvious change, should be included in protection scope of the present invention.
Claims (9)
1. a kind of flash memory device for avoiding data from disturbing, applied to the reparation of flash memory device, the flash memory device includes storage battle array
Row, the storage array include multiple memory cell, and each memory cell corresponds to a storage address respectively, and its feature exists
In the flash memory device includes：
Data-reading unit, it is connected with the storage array, the corresponding storage in the storage array is read to lasting
Reading data in unit, and by the reading data output；
Data repair address and form unit, and the storage address corresponding to the reading data being read is formed to lasting；
Data detecting unit, it is connected with the data-reading unit, to be detected to the reading data, with described in detection
Read and disturbed corresponding to data in the storage address with the presence or absence of data, and export testing result；
Controller, address is repaired with data respectively and forms unit, the data detecting unit and data-reading unit company
Connect, controller storage corresponding to locking when the testing result represents data interference to be present in the storage address
Address；
The controller carries out data ELIMINATION OF ITS INTERFERENCE operation to the memory cell corresponding to the locked storage address.
2. flash memory device according to claim 1, it is characterised in that deposited described in representing corresponding in the testing result
When data interference be present on storage address, the controller sends a locking signal to the data and repairs address formation unit；
The data repair address and form unit according to the locking signal, to be locked to the current storage address
It is fixed, and the locked storage address is sent to the controller；
Controller memory cell according to corresponding to the testing result and the locked storage address is carried out
Operation is repaired in erasing or operation is repaired in write-in, to realize that the data ELIMINATION OF ITS INTERFERENCE operates.
3. flash memory device according to claim 1, it is characterised in that the data-reading unit includes：
Column decoder, it is connected with the controller, to the corresponding generation one of decoding column address exported according to the controller
Selection signal；
Sense amplifier, one end are connected with the column decoder, and the other end is connected with the storage array, to according to the choosing
The reading data preserved corresponding to signal-obtaining in the storage address are selected, and by the data output that reads to the number
According to detection unit.
4. flash memory device according to claim 1, it is characterised in that the controller is in the data detection device
After obtaining the reading data, one first drive signal and one second drive signal are exported；
The data detection device includes：
First data validator, one end are connected with the data-reading unit, and the other end is connected with the controller, are receiving institute
State after controller exports first drive signal or second drive signal and be activated；
First register, it is connected with first data validator, first number after being activated by first drive signal
According to validator by it is described reading data compared with default first reference voltage, to export one first comparative result and protect
It is stored in first register；
Second register, it is connected with first data validator, first number after being activated by second drive signal
According to validator by it is described reading data compared with default second reference voltage, to export one second comparative result and protect
It is stored in two register；
First data comparator, described first data comparator one end connect with first register and second register
Connect, the other end is connected with the controller；
The controller preserving first comparative result respectively in first register and second register
And after second comparative result, one first comparison signal of output is to first data comparator, to activate described first
Data comparator；
The controller after being activated, to meet that the reading data are more than first base in first comparative result
Quasi- voltage, and second comparative result meets to form the detection when reading data are less than second reference voltage
As a result, and by the testing result export to the controller, the testing result is representing to the current storage list
Member write the operation signal of reparation.
5. flash memory device according to claim 1, it is characterised in that the controller is in the data detection device
After obtaining the reading data, one first drive signal and one the 3rd drive signal are exported；
The data detection device includes：
Second data validator, one end are connected with the data-reading unit, and the other end is connected with the controller, are receiving institute
State controller output first drive signal or the 3rd drive signal after be activated；
One or three register, it is connected with second data validator, described second after being activated by first drive signal
Data validator is detected the reading data with default first reference voltage to generate one the 3rd detection data, and
Described 3rd detection data are stored in the 3rd register；
4th register, it is connected with second data validator, second number after being activated by the 3rd drive signal
The reading data are detected with default 3rd reference voltage to generate one the 4th detection data according to validator, and will
The 4th detection data are stored in the 4th register；
Second data comparator, described second data comparator one end connect with the 3rd register and the 4th register
Connect, the other end is connected with the controller；
The controller preserving the 3rd comparative result respectively in the 3rd register and the 4th register
And one second comparison signal is exported after the 4th comparative result to second data comparator, to activate second number
According to comparator；
Second data comparator after activation is described to meet that the reading data are less than in the 3rd comparative result
First reference voltage, and second comparative result meets to form institute when the reading data are more than second reference voltage
State testing result, and the testing result is exported to the controller, the testing result is representing to described in current
Memory cell wipe the operation signal of reparation.
6. flash memory device according to claim 4, it is characterised in that first reference voltage is higher than the flash memory list
The erasing voltage of member, and less than the write-in voltage of the flash cell；And/or
Second reference voltage be higher than first reference voltage, and less than the flash cell said write electricity
Pressure.
7. flash memory device according to claim 5, it is characterised in that the 3rd reference voltage is less than first benchmark
Voltage.
8. flash memory device according to claim 3, it is characterised in that the storage array include tactic bit line with
And tactic wordline is formed；
The memory cell is formed by a wordline and a bit line, the bit line of each memory cell
It is connected with the sense amplifier, the sense amplifier is to by the memory cell corresponding to bit line reading
The reading data.
9. flash memory device according to claim 8, it is characterised in that also including a line decoder, the line decoder one
End is connected with the controller, and the other end is connected with the wordline of each memory cell；
The controller is to according to the locked storage address one word line position signal of output to the line decoder, institute
State the bit line of line decoder memory cell according to corresponding to the word line position signal activation；
The further controller carries out the erasing to the memory cell of activation according to the testing result and repairs behaviour
Make or carry out said write reparation operation.
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| CN104637536A (en) * | 2013-11-08 | 2015-05-20 | 菲德里克斯有限责任公司 | Flash memory device having efficient refresh operation |
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