CN107577964B - Electromagnetic information hiding method based on random sequence interference and gate circuit path constraint - Google Patents
Electromagnetic information hiding method based on random sequence interference and gate circuit path constraint Download PDFInfo
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Abstract
The invention provides an electromagnetic information hiding method based on random sequence interference and gate circuit path constraint, which is used for solving the technical problem that a password chip seriously leaks electromagnetic information when the electromagnetic information is detected in a small range in the prior art. The method comprises the following implementation steps: frequency division is carried out on an input clock by a frequency divider to obtain f1, a pseudo random number which changes along with time is obtained by a random sequence generator, and frequency division is carried out on f1 by the pseudo random number to obtain a random sequence f2 with randomly changing frequency; the electromagnetic information near the password output pin is interfered by the random sequence f2, so that the electromagnetic information leaked from the password output pin and the electromagnetic information of the random sequence are mixed and cannot be separated; the electromagnetic information of the cryptographic module is scattered, the original concentrated electromagnetic information is dispersed, and the electromagnetic information of the cryptographic module cannot be detected in a small range. The invention can be used for enhancing the security of the password in the field of resisting bypass attack and the like.
Description
Technical Field
The invention belongs to the technical field of information security, and relates to an electromagnetic information hiding method based on random sequence interference and gate circuit path constraint, which can be used for enhancing the security of a password in the fields of resisting bypass attack and the like.
Background
Human society has now entered an information age, and various activities of people in society have relied on information technology, so that information technology equipment has been widely helped again in human society. It brings rapid development to various fields of human society and brings a plurality of unexpected problems. The security of cryptographic chips is one of the most prominent problems.
The cipher chip is an integrated circuit chip with cipher operation function, which is used as the core component of information security system and its security is related to the security of the whole information system. It is widely believed that various types of attacks can be well defended by only mathematically designing a cryptographic algorithm with sufficient strength and formulating some security protocols. But the emergence of the bypass attack theory brings great challenges to chip security. An attacker can rapidly and efficiently break key information such as a secret key and the like in the cryptographic chip by collecting, processing and analyzing the side channel information leaked during the operation of the cryptographic chip. In the field of bypass attack resistance, an intruder obtains electromagnetic information or energy consumption information through detection and analyzes the information, so that the difficulty of password cracking is greatly reduced. Therefore, the information such as energy consumption, electromagnetic information and the like leaked when the chip works can be hidden, and the method plays an important role in the field of bypass attack resistance.
In most of the existing methods for hiding the electromagnetic information, the method of adding a clock crosstalk signal adds the interfered electromagnetic information, so that the electromagnetic information generating the interference and the electromagnetic information generating the password cannot be separated. For example, patent application publication No. CN105607687A entitled "a clock crosstalk implementation method for resisting bypass attack" discloses an electromagnetic information hiding method for resisting bypass attack. The method comprises the steps of carrying out phase delay on an input clock to generate four clocks with 1/4 periods of phase difference and dynamically switching frequency division clocks with 2, 3, 4 or 5 division numbers, wherein five clock sources are total, one path is randomly selected from the five clock sources to be used as clock output, meanwhile, the frequency division clocks are randomly selected from the 2 to 5 division numbers, after one path of clock is selected, the lasting period of the clock is randomly selected from 16 clocks to 31 clocks, finally, a crosstalk clock with randomly converted phase and frequency is generated in the lasting period of each clock source randomly selected by the clock sources, the measurement of the power consumption and the electromagnetic radiation of the bypass attack is based on a stable clock period, the power consumption and the electromagnetic radiation of the scrambled clock cannot be measured based on the same clock period, and the difficulty of the bypass attack is increased. When large-area electromagnetic information measurement is carried out, the method can hide electromagnetic information, but the electromagnetic information of a password output pin and a working area of a password module in a chip cannot be hidden by a high-precision small-range detection device after multiple measurements, so that the electromagnetic information is leaked, and passwords are easy to crack.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides an electromagnetic information hiding method based on random sequence interference and gate circuit path constraint.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
(1) acquiring a random sequence f 2:
(1a) dividing the frequency of an input clock of the FPGA to obtain a clock f1 with the frequency n times of the frequency of a trigger clock of the password module, wherein n is more than or equal to 20;
(1b) calculating any nonlinear function by using a set shift register to obtain a pseudo-random number t, wherein the maximum value obtained by the shift register is 2 n;
(1c) updating the pseudo-random number t by adopting the same frequency as the clock f1 to obtain a random number t' changing along with time;
(1d) dividing the frequency of the clock f1 by using a random number t' to obtain an output sequence f2 with random output frequency;
(2) electromagnetic information near the password output pin is disturbed with a random sequence f 2:
the random frequency output sequence f2 is used as an FPGA output source, the position of a chip password output pin is checked, and the output pin of the random frequency output sequence f2 is set at a pin adjacent to the pin, so that electromagnetic information leaked from the password output pin and electromagnetic information of the random sequence f2 are mixed with each other, and the electromagnetic information near the password output pin is hidden;
(3) scattering the electromagnetic information of the cryptographic module: a user uses FPGA development software to restrain an internal gate circuit path when an FPGA chip works, and the gate circuits which are concentrated in the original working area and carry out password operation are scattered to the corners of a logic array, so that the original concentrated electromagnetic information on the surface of the chip is scattered.
Compared with the prior art, the invention has the following advantages:
1. the invention outputs the output sequence with random frequency near the password output pin of the chip, so that the electromagnetic information leaked from the password output pin and the electromagnetic information of the random sequence f2 are mixed, the interference on the electromagnetic information in a small range near the password output pin is realized, the defect of the leakage of the electromagnetic information in the small range of the password output pin in the prior art is avoided, and the safety of the password chip is effectively improved.
2. According to the invention, by restricting the internal gate circuit path when the FPGA chip works, the part which is concentrated in the original working area and used for carrying out password operation is dispersed to the corner of the logic array, so that the original concentrated electromagnetic information on the surface of the chip is dispersed, the electromagnetic information leaked in a small range in the working area of the password module on the surface of the chip in the prior art is avoided, and the safety of the password chip is further improved.
Drawings
FIG. 1 is a schematic diagram of an electromagnetic information hiding system suitable for use in the present invention;
fig. 2 is a flow chart of the implementation of the present invention.
FIG. 3 cipher module output sequence and reference to electromagnetic information without any processing
FIG. 4 reference diagram of a cipher module output sequence and an electromagnetic information reference diagram of a cipher module incorporating a random sequence
FIG. 5 shows electromagnetic information of a cryptographic module operating region without gate path constraints and electromagnetic information of a cryptographic module operating region after gate path constraints
Detailed Description
The invention is described in further detail below with reference to the following figures and specific examples:
referring to fig. 1, the electromagnetic information hiding system applicable to the present invention includes a random sequence interference module and a cryptographic module electromagnetic information scattering portion; the random sequence interference module comprises two frequency dividers and a random number generator, wherein the frequency divider 1 firstly divides the frequency of the FPGA input clock, the random number generator generates a pseudo-random number which changes along with time, and the frequency divider 2 divides the frequency of the output clock obtained by the frequency divider 1 through the pseudo-random number obtained by the random number generator. The electromagnetic information scattering part of the password module restrains the internal gate circuit path when the FPGA chip works, and the gate circuits which are concentrated in the original working area and carry out password operation are scattered to the corners of the logic array.
Referring to fig. 2, the electromagnetic information hiding method based on random sequence interference and gate circuit constraint includes the following steps:
step 1: acquiring a random sequence f 2:
step 1 a: dividing the frequency of an input clock of the FPGA to obtain a clock f1 with the frequency n times of the frequency of a trigger clock of the password module, wherein n is more than or equal to 20;
the implementation case is realized based on a Xilinx FPGA development version, customers can design and verify circuits of the customers more quickly by utilizing a Xilinx FPGA programmable device, an electromagnetic observation platform, an electromagnetic probe and an oscilloscope are built, a crystal oscillator clock introduced into the FPGA development version is clk, clk is 50MHz, rising edge triggering is adopted to divide clk frequency to obtain f1, the f1 frequency is n times of the triggering clock frequency of a password module, n is more than or equal to 20, the value of n is related to the number of bits of a shift register, the smaller the value of n is, the smaller the number of the bits of the register is, the poor randomness of a pseudo random number is caused to be poor randomness of a random sequence f2, the implementation case takes n to be 64, the triggering clock frequency of the password module is 5KHz, a magnetic field near field probe is used, the resolution is 10mm, the password module output sequence and the electromagnetic information refer to FIG. 3, the upper half part is the electromagnetic information of the password module and is divided into the, when the output sequence 0-1 of the cipher module is changed, the electromagnetism has obvious pulse, and the electromagnetic information and the input sequence of the cipher module are corresponding to each other;
step 1 b: calculating any nonlinear function by using a set shift register to obtain a pseudo-random number t, wherein the maximum value obtained by the shift register is 2 n;
setting 7-bit Shift register ff, 272 × 64, a pseudo random number t is generated by a 7-bit register ff, the 7-bit register ff is given an initial value ff of 7' b1010011, and a shift is performedBy linear operation of the lowest order bits to obtain a pseudo-random number t, using f1The rising edge triggers the update of t:
assigning ff 6 to t
ff [6] is obtained by the preceding 6-bit nonlinear operation (ff [0] < fF [1 >) < fF [2] < fF [3 >) < fF [4] < fF [5]) and ff [6]
ff [5] is ff [4], ff [4] is given to ff [5]
ff [4] ═ ff [3 ]: ff 3 is given to ff 4
ff [3] ═ ff [2 ]: ff 2 is given to ff 3
ff [2] ═ ff [1 ]: ff 1 is given to ff 2
ff [1] ═ ff [0 ]: ff 0 is given to ff 1
ff [0] ═ ff [6]: ff 6 is given to ff 0
Step 1 c: updating the pseudo-random number t by adopting the same frequency as the clock f1 to obtain a random number t' changing along with time;
step 1d, dividing the frequency of the clock f1 by adopting a random number t' to obtain an output sequence f2 with random output sequence width, using a magnetic field near-field probe with resolution of 10mm, referring to a cryptographic module output sequence and electromagnetic information figure 4, wherein the upper half part is the electromagnetic information of the cryptographic module added with the random sequence, the lower half part is the cryptographic module output sequence, and observing to obtain: the electromagnetic information of the output sequence of the cryptographic module is hidden by the electromagnetic information of the random sequence;
step 2: electromagnetic information near the password output pin is disturbed with a random sequence f 2:
the random frequency output sequence f2 is used as an FPGA output source, the position of a chip password output pin is checked, and the output pin of the random frequency output sequence f2 is set at a pin adjacent to the pin, so that electromagnetic information leaked from the password output pin and electromagnetic information of the random sequence f2 are mixed with each other, and the electromagnetic information near the password output pin is hidden;
and step 3: scattering the electromagnetic information of the cryptographic module: a user uses Xilinx FPGA development software PlanAdead to restrain an internal gate circuit path when a chip works, the distribution condition of the internal gate circuit of the FPGA chip is known through software, the part which is concentrated in an original working area and is subjected to cryptographic operation is dispersed to the edge of a logic array, the dispersion of the original concentrated electromagnetic information is realized, a high-precision small-range magnetic field near-field probe is used, the probe with the resolution ratio of 2mm is used for detecting, the electromagnetic information of the working area of a cryptographic module which is not subjected to gate circuit path constraint and the electromagnetic information of the working area of the cryptographic module after the gate circuit path constraint are obtained, refer to figure 5, the upper half part is the electromagnetic information of the working area of the cryptographic module which is not subjected to the gate circuit path constraint, the lower half is the electromagnetic information of the working area of the cryptographic module after the gate circuit path constraint, after the, the hiding of the electromagnetic information of the cryptographic module in high-precision small-range detection is ensured.
The above embodiments only illustrate the implementation method of the present invention by specific implementation, and many variations are possible on the basis of the above embodiments, and such structural changes based on the present invention are included in the protection scope of the present invention.
Claims (2)
1. An electromagnetic information hiding method based on random sequence interference and gate circuit path constraint is characterized by comprising the following steps:
(1) acquiring a frequency-random output sequence f 2:
(1a) dividing the frequency of an input clock of the FPGA to obtain a clock f1 with the frequency n times of the frequency of a trigger clock of the password module, wherein n is more than or equal to 20;
(1b) calculating any nonlinear function by using a set shift register to obtain a pseudo-random number t, wherein the maximum value obtained by the shift register is 2 n;
(1c) updating the pseudo-random number t by adopting the same frequency as the clock f1 to obtain a random number t' changing along with time;
(1d) dividing the frequency of the clock f1 by using a random number t' to obtain an output sequence f2 with random frequency;
(2) electromagnetic information near the password output pin is interfered by a random frequency output sequence f 2:
the random frequency output sequence f2 is used as an FPGA output source, the position of a chip password output pin is checked, and the output pin of the random frequency output sequence f2 is set at a pin adjacent to the pin, so that electromagnetic information leaked from the password output pin and electromagnetic information of the random frequency output sequence f2 are mixed with each other, and the electromagnetic information near the password output pin is hidden;
(3) scattering the electromagnetic information of the cryptographic module: a user uses FPGA development software to restrain an internal gate circuit path when an FPGA chip works, and the gate circuits which are concentrated in an original working area and carry out password operation are scattered to the corners of a logic array in the FPGA chip, so that the original concentrated electromagnetic information on the surface of the chip is scattered.
2. The electromagnetic information hiding method based on random sequence interference and gate circuit path constraint according to claim 1, wherein the step (3) of constraining the internal gate circuit path of the FPGA chip during operation specifically comprises: for an altera development board, directly modifying and setting an sql file to realize the restriction of an internal gate circuit path when an FPGA chip works; for the xilinx development board, the constraint of an internal gate circuit path when the FPGA chip works is directly realized by adopting PlanAdead software.
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| CN109885960A (en) * | 2019-03-05 | 2019-06-14 | 中国人民解放军32082部队 | A kind of embedded chip hardware Trojan horse design method based on electromagnetism bypass analysis |
| CN109861818A (en) * | 2019-03-06 | 2019-06-07 | 京东方科技集团股份有限公司 | Encryption and decryption circuit, encryption and decryption device and encryption and decryption method |
| CN114760003A (en) * | 2022-06-14 | 2022-07-15 | 北京密码云芯科技有限公司 | Encryption protection device for electromagnetic perception attack and use method |
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| CN201352349Y (en) * | 2008-12-18 | 2009-11-25 | 成都立鑫新技术科技有限公司 | Electronic information protector |
| CN104461452A (en) * | 2013-09-17 | 2015-03-25 | 航天信息股份有限公司 | Method and device for generating true random numbers in system on chip |
| CN105607687A (en) * | 2015-12-22 | 2016-05-25 | 上海爱信诺航芯电子科技有限公司 | Anti-bypass attack clock crosstalk realization method |
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| CN201352349Y (en) * | 2008-12-18 | 2009-11-25 | 成都立鑫新技术科技有限公司 | Electronic information protector |
| CN104461452A (en) * | 2013-09-17 | 2015-03-25 | 航天信息股份有限公司 | Method and device for generating true random numbers in system on chip |
| CN105607687A (en) * | 2015-12-22 | 2016-05-25 | 上海爱信诺航芯电子科技有限公司 | Anti-bypass attack clock crosstalk realization method |
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