CN107546974B

CN107546974B - Boost circuit and inverter topology with cascaded diode circuits

Info

Publication number: CN107546974B
Application number: CN201710486849.8A
Authority: CN
Inventors: E·特梅西; M·弗里施
Original assignee: Wenketec Germany Co Ltd
Current assignee: Wenketec Germany Co Ltd
Priority date: 2016-06-24
Filing date: 2017-06-23
Publication date: 2020-06-05
Anticipated expiration: 2037-06-23
Also published as: DE102016211403A1; CN107546974A; DE102016211403B4

Abstract

The present invention generally relates to topologies for boost circuits, inverters, and half-bridge circuits. A Power Factor Correction (PFC) boost circuit for connection to an Alternating Current (AC) power source, comprising: an AC input node (102) for connection to an AC power source; a reference potential node (104) for connection to a reference potential; and at least first and second power transistors connected in anti-series with respect to each other between the AC input node and the reference potential node, wherein the first power transistor (T1) is connected in anti-parallel to the first power diode (D5) and the second power transistor (T2) is connected in anti-parallel to the second power diode (D6). A first diode circuit (D1, D2) is connected between the AC input node (102) and a positive output node (112) and comprises a series connection of first and second diode elements having different recovery times.

Description

Boost circuit and inverter topology with cascaded diode circuits

Technical Field

The present invention relates generally to power electronic switching circuits, and more particularly to power modules employing two or more controlled switches. More specifically, the present invention provides improved topologies for boost circuits, inverters, and half-bridge circuits.

Efficiency is becoming more and more important in the field of power electronics and in many applications, such as inverter modules for the solar market, and efficiency optimization has become a major design goal. Photovoltaic solar panels typically use Pulse Width Modulation (PWM) inverters to convert Direct Current (DC) power generated by the solar cells into Alternating Current (AC) power that can be fed to a power grid. Typical additional applications for these inverters include their use in Uninterruptible Power Supplies (UPS), fuel cells and wind turbines. Furthermore, PWM inverters can be used to provide compensation for reactive loads, for harmonic cancellation of the power supply grid, or as variable speed drives for induction motors. The most commonly used inverters are single-phase and three-phase transformerless inverters.

The most commonly used switching elements in inverter designs are field effect transistors FETs, such as metal oxide semiconductor field effect transistors MOSFETs, bipolar transistors, such as insulated gate bipolar transistors IGBTs, bipolar junction transistors BJTs, and gate turn-off thyristors GTOs. Traditionally, MOSFETs are used for low DC voltage or low power inverter designs. IGBTs are used for medium to high power or high voltage inverter designs. GTOs are used for ultra high power inverter designs. A recent development is the so-called Super Junction (SJ) MOSFET, which has a very low parasitic capacitance compared to standard MOSFETs. The SJ MOSFET has about half the value of the input and output capacitance, which provides benefits for switching losses and driving losses.

Furthermore, the present invention relates to a Power Factor Correction (PFC) boost circuit. In particular, the present invention relates to a PFC boost circuit comprising switchable power transistors to switch the circuit between a flyback state and a forward state.

Background

Over the years, the industry has considered a number of different circuit arrangements for PFC boost circuits in an attempt to maximize power supply efficiency while reducing the number of components and minimizing power losses. Conventional approaches to arranging single phase PFC boost circuits rely on bridge rectifiers to rectify the AC mains voltage to a continuously varying DC voltage source. For example, a conventional PFC boost circuit may include a full-wave rectifier composed of four diode elements. An inductive element is arranged in series and a capacitive element is arranged in parallel at the output of the rectifier output. The switchable power transistor is controlled to store energy in the inductive element and to transfer the stored energy to the capacitive element.

A known neutral boost PFC circuit provided by Vincotech corporation is depicted in fig. 1. According to this topology, an inductor is connected between the AC power source and the first AC input node 102. The first diode D10 is disposed between the first AC input node 102 and a first terminal of the first capacitor C1. A second diode D14, which is connected in anti-parallel with the first diode D10, is disposed between the first AC input node 102 and the first terminal of the second capacitor C2. Second terminals of the first and second capacitors are connected to each other at a second AC input node 104 and to ground potential. A series circuit of two Insulated Gate Bipolar Transistors (IGBTs) T1, T2 is connected between the first AC input node 102 and the second AC input node 104. In addition, diodes D5 and D6 are placed in the flyback path of the IGBTs T1, T2 to conduct reverse current and compensate for the lack of a body diode in the bipolar transistor. Both IGBTs are connected to the same gate drive unit and the same power supply.

However, in this known circuit, a full blocking voltage is required as the maximum rated voltage of the diodes D1 and D4, e.g. 1200V. When such high-rated silicon diodes are used, the switching frequency becomes too slow (switching frequencies greater than 4kHz must typically be achieved). Alternatively, an expensive silicon carbide (SiC) schottky barrier diode may be used. A problem associated with the PFC circuit shown in fig. 1 is potential ringing upon emergency shutdown. After the IGBTs T1, T2 turn off, the reverse recovery current will charge the inductor L in the opposite direction and change the voltage at the first AC input node 102 to an opposite DC voltage.

Furthermore, for other known power module circuits, such as inverters with Neutral Point Clamped (NPC) topology, fast boost diodes with high blocking voltages (e.g. 1200V) are required. Fig. 8-10 show a conventional topology of a mixed-voltage NPC inverter module, where the diodes need to commutate half of the DC voltage, but must block the full voltage during the inactive half-wave. In other words, a fast diode with a high rated voltage is required, and thus the conventional circuit is costly to manufacture.

Accordingly, there is a need to provide improved PFC boost circuits, NPC inverter circuits, boost circuits, and three-phase inverters that can be implemented with cheaper components while being safe, robust, and universally applicable.

Disclosure of Invention

This object is solved by the subject matter of the independent claims. Advantageous embodiments of the invention are the subject matter of the dependent claims.

The invention is based on the following idea: the use of a series connection of at least two diodes with half the blocking voltage reduces the reverse recovery charge and thus reduces the switching losses compared to the use of a single diode with a certain blocking voltage. According to the invention, the individual diodes in the various power module circuits are replaced by a series connection of diodes with different recovery speeds.

According to a first advantageous embodiment of the present invention, there is provided a Power Factor Correction (PFC) boost circuit for connection to an Alternating Current (AC) power source, the PFC boost circuit comprising: an AC input node for connection to an AC power source; a reference potential node for connection to a reference potential; a positive output node for outputting a positive DC voltage and a negative output node for outputting a negative DC voltage; and at least first and second power transistors connected in anti-series with respect to each other between the AC input node and the reference potential node.

The first power transistor is connected in anti-parallel to the first power diode, and the second power transistor is connected in anti-parallel to the second power diode. These first and second power diodes are formed by the body diodes of the first and second power transistors, wherein the power transistors are for example MOSFETs or IGBTs. In the case where the power transistors are GaN-based fabricated, with slightly different mechanisms for reverse bias (or diode) operation, the first and second power diodes may advantageously be formed from diodes fabricated separately from the first and second power transistors. For example, the diode may be integrated with a circuit for synchronous rectification of the switch.

According to the invention, a first diode circuit is connected between the AC input node and the positive output node, wherein the first diode circuit comprises a series connection of first and second diode elements having different recovery times.

By replacing the single diode of the conventional arrangement with two diodes having different recovery times, one of the diodes may advantageously be a fast recovery diode, while the other of the diodes is a low dropout diode optimized to reduce static losses. In operation, fast diodes handle commutation during switching, while low drop-off diodes increase blocking capability during static blocking mode. This mode of operation is for example advantageous for typical three-level AC/DC converter applications, i.e. three-phase PFC. During one half-wave, only the inactive diode is loaded with the full blocking voltage. The diode that is commutating faces only half the maximum voltage. Illustratively, when used with a total of 1200V DC voltage, the two diodes have a rated blocking voltage of 600V.

The boost PFC circuit according to the present invention exhibits improved switching behavior and increased efficiency, covering 1200V applications without the use of expensive silicon carbide technology.

Advantageously, the gate terminal and the emitter (or source) terminal of the semiconductor boost switch are at the same voltage level. Thus, only one gate driver and power supply is required.

Furthermore, no dynamic symmetrization is required, since only half of the DC voltage is switched at commutation.

It will be apparent to those skilled in the art that any particular semiconductor switch may be used in accordance with the principles of the present invention. For example, an IGBT, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a GaN High Electron Mobility Transistor (HEMT), or any other suitable technology may be employed. In case field effect technology is used, the diode connected in anti-parallel with the switch may be replaced by a body diode and/or synchronous rectification.

Advantageously, the first diode element is connected between the second diode element and the reference potential node and comprises an ultrafast semiconductor diode having a recovery time of less than about 100 ns.

According to an exemplary embodiment, the second diode element comprises a low-drop semiconductor diode having a forward voltage drop of less than about 1V.

Further, a first output capacitor connected in series between the first diode circuit and the reference potential node may be provided. The capacitor may for example be an integral part of a power supply module comprising a PFC circuit according to the invention.

To provide a symmetrical circuit architecture, a second diode circuit is provided between the AC input node and the negative output node or between the negative output node and a node connecting the first and second power transistors. The second diode circuit comprises a series connection of two diode elements having different recovery times when connected between a negative output node and a node connecting the first and second power transistors. An arrangement with only one diode as the second diode circuit has the advantage that one less diode is needed.

Further, a second output capacitor may be connected in series between the second diode circuit and the reference potential node.

By additionally providing the first symmetric diode connected between the reference potential node and a node connecting two diode elements of the first diode circuit, the problem of potential ringing can be effectively suppressed. The symmetry of the leakage current can also be performed by providing a resistor in parallel with the symmetric diode, if desired. Furthermore, a second symmetric diode may be connected between the reference potential node and a node connecting two diode elements of the second diode circuit.

The concept according to the invention can also be advantageously used with inverter circuits having a Neutral Point Clamped (NPC) topology. The inverter circuit includes: a first input terminal for connection to a DC voltage of a first polarity and a second input terminal for connection to a DC voltage of a polarity opposite to the first polarity and an input neutral point terminal for connection to a reference potential.

A first output node is connected to a first end of the first decoupling inductor, a second output node is connected to a first end of the second decoupling inductor, and an output connection point is provided for outputting an AC voltage connected to a second end of the first decoupling inductor and a second end of the second decoupling inductor. A first semiconductor switching device is coupled between the first input terminal and the first output node, wherein a second semiconductor switching device is coupled between the second input terminal and the second output node, the first and second semiconductor switching devices each comprising at least two semiconductor switches connected in series.

According to the invention, a first diode circuit is connected between the first input terminal and the first output node, and a second diode circuit is connected between the second input terminal and the second output node, wherein the first and second diode circuits each comprise a series connection of first and second diode elements having different recovery times.

Advantageously, the first diode element serves as a boost diode which has to commutate half the DC voltage, while at the inactive half-wave the second diode element provides the required blocking voltage. According to the present invention, the second diode element is a low dropout rectifier diode having no fast recovery function. In particular, the first and second diode elements are rated with a maximum blocking voltage of half the maximum DC voltage occurring between the first input terminal and the second input terminal.

The shunt output topology improves the switching characteristics of the NPC inverter, in particular cross-conduction is avoided. The circuit according to the invention provides improved efficiency in boost mode using the reduced voltage drop of the second rectifier diode.

Furthermore, according to an advantageous embodiment of the invention, an optional clamping diode may be provided for improving the symmetry upon a change of polarity of the input voltage and during the passive blocking mode. In particular, the inverter circuit may further include a first symmetric diode connected between the input neutral point terminal and a node connecting the two diode elements of the first diode circuit. A second symmetric diode may be connected between the input neutral point terminal and a node connecting the two diode elements of the second diode circuit.

According to another advantageous embodiment, at least one of the diode elements is formed by a series connection of two symmetrical fast recovery diodes. For the case where the DC voltage is high, e.g. above 1200V, the division of the invention into two diodes connected in series may still be insufficient, so that a slow silicon diode with a sufficiently high blocking voltage (e.g. 1200V) or an expensive SiC schottky barrier diode is required. By specifically forming the boost diode and the neutral clamp diode as a series connection of two symmetrical fast recovery diodes, this problem can be overcome and only diodes with a lower blocking voltage (e.g. 600V) are required.

The invention also relates to an inverter circuit with a hybrid voltage Neutral Point Clamped (NPC) topology. The inverter circuit includes: a first input terminal for connection to a DC voltage of a first polarity; a second input terminal for connection to a DC voltage of a polarity opposite to the first polarity; and an input neutral terminal for connection to a reference potential.

A first output node is connected to a first end of the first decoupling inductor, a second output node is connected to a first end of the second decoupling inductor, and an output connection point is provided for outputting an AC voltage connected to a second end of the first decoupling inductor and a second end of the second decoupling inductor. A first semiconductor switching device is coupled between the first input terminal and the first output node, wherein a second semiconductor switching device is coupled between the second input terminal and the second output node, the first and second semiconductor switching devices each comprising at least two semiconductor switches connected in series. A first diode circuit is connected between the first input terminal and the first output node, and a second diode circuit is connected between the second input terminal and the second output node, wherein the first and second diode circuits each comprise a series connection of first and second diode elements having different recovery times. It can be seen that an advantage of this concept is that diodes with high blocking voltages are not required, in particular for reactive power switching. Thus, a faster switching with reduced manufacturing costs may be achieved.

According to another advantageous embodiment, a voltage boost circuit for use in a power supply module is provided.

The boost circuit comprises a first DC input terminal connected to a DC voltage of a first polarity via an inductor; a second DC input terminal for connection to a DC voltage of a polarity opposite to the first polarity; and a first output terminal, a second output terminal, and an output neutral point. A first semiconductor switching device is coupled between the first or second input terminal and the input neutral point, wherein a first output capacitor is coupled between the first output terminal and the output neutral point, and wherein a second output capacitor is coupled between the second output terminal and the output neutral point. A diode circuit is coupled between the second or first input terminal and the input neutral point, wherein the diode circuit comprises a series connection of first and second diode elements having different recovery times, and wherein a third diode element is connected between the output neutral point and a node connecting the two diode elements of the diode circuit.

The use of a series connection of a first and a second diode element with different recovery times has the following advantages: each diode must be rated at half the blocking voltage required by conventional boost circuits.

Finally, the basic idea of the invention can also be implemented in a three-phase inverter architecture based on a half-bridge architecture. According to the present invention, a three-phase inverter circuit includes: a first DC input terminal for connection to a DC voltage of a first polarity; a second DC input terminal for connection to a DC voltage of a polarity opposite to the first polarity; and first, second and third half-bridges connected in parallel between the first and second input terminals, each half-bridge comprising a series connection of two semiconductor switches; first, second and third output terminals, the first output terminal being connected to a node connecting the two semiconductor switches of the first half-bridge, the second output terminal being connected to a node connecting the two semiconductor switches of the second half-bridge and the third output terminal being connected to a node connecting the two semiconductor switches of the third half-bridge. According to the invention, first to sixth series connections of first and second diode elements are connected across each said semiconductor switch, each of the diode elements being rated for a maximum blocking voltage of half the maximum voltage occurring between the first input terminal and the second input terminal.

With this arrangement, high switching performance can be achieved without using expensive SiC schottky barrier diodes with full rated blocking voltages.

To additionally provide symmetry, the inverter circuit may include: a series circuit of two capacitors, wherein a node between the two capacitors forms an input neutral point, wherein the first capacitor is connected in parallel to the first resistor and the second capacitor is connected in parallel to the second resistor; and first to sixth symmetric diodes each connected between the input neutral point and a node connecting two diode elements connected in series. In this embodiment, each diode element connected to the first or second input terminal has a faster recovery time than the corresponding second diode element. During recovery, the second diode element receives the full voltage until a difference between the output voltage and the neutral voltage is reached between the capacitors. The horizontally symmetric diode provides a reverse recovery current and clamps the first diode to a neutral voltage. Thus, a symmetry can be achieved.

Drawings

The accompanying drawings are incorporated in and form a part of this specification to illustrate several embodiments of the present invention. Together with the description, the drawings serve to explain the principles of the invention. The drawings are only for purposes of illustrating preferred and alternative examples of how the invention may be made and used and are not to be construed as limiting the invention to only the embodiments shown and described. Furthermore, several aspects of the embodiments may form the solution according to the invention, alone or in different combinations. Thus, the embodiments described below can be considered alone or in any combination thereof. Additional features and advantages will be made apparent from the following more particular description of various embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same elements, and in which:

fig. 1 is a circuit diagram of a conventional neutral boost PFC circuit;

fig. 2 is a circuit diagram of a neutral boost PFC circuit according to the present invention;

fig. 3 is a circuit diagram of another neutral boost PFC circuit according to the present invention;

fig. 4 is a circuit diagram of another neutral boost PFC circuit according to the present invention;

FIG. 5 is a circuit diagram of a conventional NPC inverter;

FIG. 6 is a circuit diagram of an NPC inverter with split output according to the present invention;

FIG. 7 is a circuit diagram of another NPC inverter with split output according to the present invention;

fig. 8 is a circuit diagram of a conventional mixed-voltage NPC inverter;

fig. 9 is a circuit diagram of another conventional mixed-voltage NPC inverter;

fig. 10 is a circuit diagram of another conventional mixed-voltage NPC inverter;

fig. 11 is a circuit diagram of a mixed voltage NPC inverter according to the present invention;

fig. 12 is a circuit diagram of a mixed voltage NPC inverter according to another embodiment of the present invention;

FIG. 13 is a circuit diagram of a conventional boost circuit;

FIG. 14 is a circuit diagram of a boost circuit according to the present invention;

fig. 15 is a circuit diagram of a conventional three-phase inverter;

fig. 16 is a circuit diagram of a three-phase inverter according to the present invention;

fig. 17 is a circuit diagram of another three-phase inverter according to the present invention.

Detailed Description

The invention will now be explained in more detail with reference to the drawings. Referring to fig. 1, reference will first be made to a conventional neutral boost Power Factor Correction (PFC) circuit in order to better understand the basic principles of the present invention. The neutral boost PFC circuit is connected to the alternating current power source AC via an inductor L with a first input node 102. The first transistor T1 and the second transistor T2 are connected in series between the first input node 102 and a second input node 104 connected to a reference potential, such as ground. In the illustrated embodiment, the transistors T1 and T2 include Insulated Gate Bipolar Transistors (IGBTs). Therefore, each of the transistors T1, T2 is connected in anti-parallel with the diodes D5 and D6, respectively. However, it is obvious to a person skilled in the art that other semiconductor switches than IGBTs may be used, such as field effect transistors FETs, such as metal oxide semiconductor field effect transistors MOSFETs, bipolar junction transistors BJTs, GaN-based transistors and gate turn-off thyristors GTOs. When MOSFETs are used, diodes D5 and D6 may be replaced by body diodes of transistors. On the other hand, for GaN-based transistors, synchronous rectification of the switch may be advantageously utilized to fabricate the diode.

The IGBTs T1, T2 are connected in reverse series, i.e. the emitter of the IGBT T1 is connected to the emitter of the IGBT T2. In this structure, the gate terminals of the two IGBTs T1, T2 are connected to a common gate driver, so that only one gate driver and one power supply are required. First and second output capacitors C1, C2 are provided for outputting positive and negative DC voltages between the first and

second output nodes

112, 114 and ground potential 104. A first diode D10 and a second diode D14 are arranged between the first AC input node 102 and the first and

second output nodes

112, 114, respectively.

However, as mentioned above, in this known circuit, a full blocking voltage is required as the maximum rated blocking voltage of the diodes D10 and D14, e.g. 1200V. When such high-rated silicon diodes are used, the switching frequency becomes too slow (switching frequencies greater than 4kHz must typically be achieved). Alternatively, an expensive silicon carbide (SiC) schottky barrier diode may be used. A problem associated with the PFC circuit shown in fig. 1 is potential ringing upon emergency shutdown. After the IGBTs T1, T2 turn off, the reverse recovery current will charge the inductor L in the opposite direction and change the voltage at the first AC input node 102 to an opposite DC voltage.

To overcome these problems, the present invention proposes to modify the circuit of fig. 1 by replacing each diode D10 and D14 with a series connection of two diodes. The circuit is shown in fig. 2. According to the present invention, instead of the diode D10 being rated with a full blocking voltage, a series connection of diodes D1 and D2 with half the blocking voltage is provided between the first AC input node 102 and the first output node 112. In addition, diode D14 of fig. 1, which is rated for a full blocking voltage (e.g., 1200V), is replaced by a series connection of diodes D3 and D4, each rated for half of the blocking voltage (e.g., 600V). The diodes D1 and D4 closest to the

output nodes

112, 114 comprise ultrafast recovery diodes, while the diodes D2 and D3 and D5 and D6 are formed by so-called low-dropout diodes, i.e. diodes with a low forward-voltage drop optimized to reduce static losses. The introduction of two diodes in series (hereinafter sometimes also referred to as "cascade") with half-blocking voltage and with different recovery speed reduces the reverse recovery charge and losses during switching of the diodes and the respective switching elements. Generally, much faster elements are available in 600V technology compared to 1200V technology. This will result in a further reduction of the switching losses.

The problem with using cascaded circuits is the voltage sharing and dynamic symmetry of the diodes during commutation. Since one of the two diodes recovers in reverse faster, the diode will have to block the full reverse voltage. According to the invention, a full blocking voltage during commutation is avoided, so that the full blocking voltage is only needed in a static mode after commutation.

According to the invention, the symmetrization is given by the function of the specific application environment or must be provided by using an additional clamping circuit. In fig. 2, further clamping circuits are shown by dashed lines. In particular, two symmetric diodes D7 and D8 may be provided. The first symmetric diode D7 is arranged between the reference potential node 104 and a node 108 between the first diode element D1 and the second diode element D2. The second symmetric diode D8 is connected between the reference potential node 104 and the node 110 between the diode elements D4 and D3.

By providing these optional symmetric diodes D7, D8, potential ringing can be effectively suppressed. Furthermore, the symmetry of the blocking operation is preferably ensured by the reverse leakage characteristics of the diodes used or by providing a resistor (not shown in the figure) in parallel with the symmetric diodes D7, D8.

With the circuit arrangement according to the invention, it is possible to improve the switching characteristics of the boost PFC circuit while using only low-cost-effective diodes with lower blocking voltages instead of expensive SiC diodes with higher blocking voltages. In this architecture, the gate terminals of the two IGBTs T1, T2 are connected to a common gate driver, so that only one gate driver and one power supply are required.

Fig. 3 shows an improved neutral boost PFC circuit arrangement according to the present invention. In contrast to the embodiment shown in fig. 2, the circuit arrangement of fig. 3 provides only a cascaded diode circuit between the first AC input node 102 and the first output node 112. The second output node 114 is connected to the two emitter terminals of the IGBTs T1 and T2 at node 106 via a single diode D4. This arrangement has the advantage that fewer diodes are required to implement the circuit. As can be seen from this figure, both transistors T1, T2 are controlled by a common gate driver 107. The gate driver 107 receives a Pulse Width Modulation (PWM) control signal at its input.

Fig. 4 shows a variation of the improved circuit shown in fig. 3. According to this embodiment, a further temperature sensor 116 is provided. The circuit arrangement shown in fig. 4 can be assembled as a separately housed module component. As shown in dashed lines, the module may optionally be provided with integrated output capacitors C1, C2 and a symmetric diode D7 as described above.

The inventive concept of dividing the diode structure into a plurality of diodes may advantageously be used with a Neutral Point Clamped (NPC) inverter structure. Fig. 5 shows a conventional NPC inverter module, which may be used, for example, to generate a sinusoidal output voltage from a DC input voltage, for example, from a photovoltaic module. The NPC inverter includes two IGBTs T51, T52 in the first branch and two IGBTs T53, T54 in the second branch. Each transistor is provided with a diode (reference numerals D51, D52, D53, D54). The first branch is connected to a first DC input terminal 118, which may be connected to a DC voltage of positive polarity. The second branch is connected to a second DC input terminal 120 which may be connected to a DC voltage of negative polarity. The output terminal 122 may be connected to an inductor (not shown in the figure), for example. The input neutral point NP may be connected to ground.

In operation, the transistor T52 is turned on during the positive half-wave of the output signal. The transistor T53 is turned on during the negative half wave. The PWM is modulated by transistors T51 and T54. When transistor T51 is off during the positive half-wave, current will commutate from neutral NP to output 122 through diode D55. The negative path is completely inactive. At the negative half-wave, the negative current commutates from neutral NP through diode D56 with transistors T51 and T52 inactive.

Generally, NPC topologies have the advantage of reduced switching losses, since only half of the DC voltage needs to be switched; this also halves the switching losses in the transistors. Furthermore, the NPC topology has lower ripple in the output current and half of the output voltage transients. This reduces the effort of filtering and isolation in the filter inductor. Finally, in the NPC architecture, the DC voltage is split into positive and negative voltages, which support a series connection of DC capacitors without the problem of leakage compensation.

These advantages are maintained by the improved topology according to the invention shown in fig. 6. In addition, shunt outputs OUT1, OUT2 are provided which improve switching characteristics by avoiding cross conduction. According to the present invention, a cascade circuit of two diodes having different recovery times is provided between each input terminal and one of the output terminals. Specifically, the diodes D61 and D62 are connected between the first DC input terminal 118 and the second output terminal OUT 2. Diodes D63 and D64 are connected between the second DC input terminal 120 and the first output terminal OUT 1. Diodes D61 and D64 operate as boost diodes and must commutate half the DC voltage at the respective inactive half-wave. The internal vertical diodes D62 and D63 provide the required blocking voltage. According to the present invention, the internal diodes D62 and D63 are formed of low-dropout rectifying diodes having no fast recovery function. With this reduced pressure drop, improved efficiency may be achieved in boost mode.

Optionally, further clamping diodes D65, D66 may be provided as indicated by dashed lines in fig. 6. These clamping diodes D65, D66 improve the symmetry during the passive blocking mode.

In addition, a temperature sensor 116 may be provided for monitoring the temperature of the power module.

Fig. 7 shows a further refinement of the NPC circuit according to the invention. According to this embodiment, some of the diodes shown in fig. 6 are replaced by a series connection of two further diodes. Preferably, the boost diodes D61, D64 and the neutral clamp diodes D67, D68 are formed by a series connection of two symmetrical fast recovery diodes D61-a, D61-b, D64-a, D64-b, D67-a, D67-b, D68-a, D68-b.

In addition to the advantages of the circuit shown in fig. 6, this solution has the advantage that even higher DC voltages (greater than e.g. 1200V) can be handled without the need to use slow Si diodes or expensive SiC diodes.

Fig. 8 to 10 show a conventional mixed-voltage NPC inverter. The advantage of this topology is that only one forward voltage drop occurs upon excitation. However, for these known circuits, a fast boost diode with double the blocking voltage is required for reactive power switching. For example, a 1200V rated diode is required instead of a 600V rated diode. This is because the diodes must block the full voltage during the inactive half-wave, although they need only commutate to half the voltage.

To overcome this problem, the present invention provides a mixed voltage NPC circuit having an advanced booster circuit as shown in fig. 11. According to the present invention, a series connection of diodes D111 and D114 and a series connection of diodes D112 and D113 are provided, and IGBTs T113 and T114 are connected between ground and the node connecting these diodes. With the circuit according to fig. 11, the utilization of the overall semiconductor switch is improved, since the buck and boost diode functions are partially combined.

Advantageously, the topology requires only 600V rated diodes, but can operate in a three-level configuration up to 1000V (of course the specific values are merely exemplary).

As can be seen from fig. 11, at the time of the step-down operation, the diode D111 serves as a freewheeling diode (FWD) for the IGBT T111 and the diode D112 serves as an FWD for the IGBT T112, while at the time of the step-up operation, the diode D113 serves as an FWD for the IGBT T113 and the diode D114 serves as an FWD for the IGBT T114.

In the embodiment shown in fig. 11, only IGBTs are used as semiconductor switches. However, in order to increase the switching frequency and the ability to handle reactive power, SiC MOSFETs and Super Junction (SJ) MOSFETs may also be employed. Fig. 12 shows a correspondingly improved mixed-voltage NPC inverter circuit.

In particular, the transistors T111 and T112 forming the step-down switch include SiC MOSFETs. The transistors T113 and T114 forming the boost switch include SJ MOSFETs. As is well known, by using SJ MOSFETs, the switching speed increases dramatically. This behavior comes from the low parasitic capacitance of the SJ MOSFET compared to the standard MOSFET. The SJ MOSFET has about half the value of the input and output capacitance, which provides benefits for switching losses and driving losses. Thus, operating at 200kHz can achieve efficiencies in excess of 98%, including filters. Furthermore, an inductor with a very low inductance can be used at the output. The circuit shown in fig. 12 has 100% capability of handling reactive power and may also provide Low Voltage Ride Through (LVRT) and Fault Ride Through (FRT). This cost is moderate because only two expensive SiC MOSFETs are required.

Another advantageous application of the concept according to the invention will now be described with reference to fig. 13 and 14. Fig. 13 depicts a conventional boost circuit, comprising: a semiconductor switch T131, a zener diode DZ, and an output capacitor C. The advantage of this boost circuit can be seen primarily in the fact that only one voltage drop occurs during freewheeling and excitation. However, a disadvantage of this circuit is that a zener diode with a full rated blocking voltage (e.g., 1200V) is required. Therefore, for high frequencies that must be handled in solar power applications, an expensive 1200V schottky barrier diode is required.

This problem can be overcome by using a boost circuit with a cascade of diodes and optionally symmetrical diodes as shown in fig. 14. According to this embodiment, the series connection of diodes D142 and D143 is connected between the first DC input terminal 118 (which is connected to the DC voltage via the inductor L) and the DC + output terminal 112. A symmetric diode D144 is connected between the node 119 connecting diodes D142 and D143 and the output Neutral Point (NP) node 104.

An IGBT T141 is arranged between the second DC input node 120 and the first DC input node 118. According to the present invention, diode D142 has a faster recovery time than diode D143. Thus, during recovery, diode D142 receives the full voltage until the difference between the output voltage and the neutral voltage is reached between capacitors C1 and C2. An auxiliary symmetric diode 144 (shown as optional by the dashed line) provides reverse recovery current and clamps diode D143 to neutral voltage.

Advantageously, the circuit arrangement shown in fig. 14 requires only diodes rated with a blocking voltage of half the maximum occurring DC voltage. The three-level architecture is compatible with most existing topologies.

In fig. 14, the series connection of diodes D142 and D143 is arranged in the positive path. However, it is obvious to those skilled in the art that alternatively, the diode may also be arranged in the negative path, while the IGBT T141 will be arranged in the positive path.

Furthermore, the present invention can also be advantageously applied to a three-phase inverter as shown in fig. 15. The conventional circuit is based on three half bridges and provides three AC phase outputs from a DC input. In contrast to this known arrangement, the present invention proposes to replace the diodes across each of the semiconductor switches of the half-bridge by a series connection of two diodes having only half the blocking voltage. Fig. 16 shows a circuit arrangement according to the invention. These series-connected diodes can be formed by identical fast recovery diodes and improve the switching speed. Therefore, high switching performance can be achieved without using an expensive SiC schottky barrier diode having a full blocking voltage.

Optionally, a temperature sensor 116 may be provided.

Fig. 17 shows a further advantageous embodiment in which diodes with different recovery speeds are used as cascade diodes. The three-phase inverter circuit may operate as a booster. In each half-bridge branch, the external diode has a faster recovery time than the internal diode. Thus, during recovery, the external diode receives the full voltage until the difference between the output voltage and the neutral voltage is reached between the capacitors C3 and C4. Each branch also includes an auxiliary horizontal diode that provides reverse recovery current and clamps the internal diode to neutral voltage. Advantageously, the problem of symmetrization can be solved compared to the arrangement of fig. 16.

In summary, the present invention allows the use of low voltage diodes that provide faster reverse recovery characteristics. This reduces switching losses and improves efficiency in high frequency switching applications. In the market there are fast recovery diodes with lower voltages that are much faster than fast recovery diodes with higher blocking voltages and furthermore, at lower costs compared to alternatives such as dual voltage SiC diodes.

The circuits described in detail above may be used as sub-circuits or as stand-alone modules of a power supply module. Furthermore, the illustrated topology may be distributed over multiple modules or substrates to provide a low inductance commutation path. In addition, an optional leakage current symmetry circuit may be provided and integrated into the power supply module.

Claims

1. A power factor correcting boost circuit for connection to an alternating current, AC, power source, the power factor correcting boost circuit comprising:

an AC input node (102) for connection to an AC power source;

a reference potential node (104) for connection to a reference potential;

a positive output node (112) for outputting a positive DC voltage and a negative output node (114) for outputting a negative DC voltage;

at least first and second power transistors (T1, T2) connected in anti-series with respect to each other between the AC input node and the reference potential node, wherein the first power transistor (T1) is connected in anti-parallel to a first power diode (D5), and the second power transistor (T2) is connected in anti-parallel to a second power diode (D6);

a first diode circuit (D1, D2) connected between the AC input node (102) and the positive output node (112);

wherein the first diode circuit (D1, D2) is formed by a series connection of first and second diode elements having different recovery times, and wherein one of the diode elements comprises a fast recovery diode and the other of the diode elements comprises a low dropout diode optimized to reduce static losses, such that in operation the fast recovery diode handles commutation during switching, while the low dropout diode increases blocking capability during static blocking mode.

2. The pfc boost circuit of claim 1, wherein the first diode element (D1) is connected between the second diode element (D2) and the positive output node (112) and comprises an ultrafast semiconductor diode having a recovery time of less than about 100ns as the fast recovery diode.

3. The pfc boost circuit of claim 2, wherein the second diode element (D2) comprises a low-dropout semiconductor diode having a forward voltage drop of less than about 1V as the low-dropout diode.

4. The power factor correction boost circuit according to one of claims 1 to 3, wherein the first and second power diodes (D5, D6) are formed by body diodes of the first and second power transistors (T1, T2) or the first and second power diodes (D5, D6) are formed by diodes manufactured separately from the first and second power transistors (T1, T2).

5. The power factor correction boost circuit according to one of claims 1 to 3, further comprising a first output capacitor (C1) connected in series between the first diode circuit (D1, D2) and the reference potential node (104).

6. The power factor correction boost circuit according to one of claims 1 to 3, wherein a second diode circuit (D3, D4) is provided between the AC input node (102) and the negative output node (114), wherein the second diode circuit (D3, D4) comprises a series connection of two diode elements having different recovery times.

7. The power factor correction boost circuit according to one of claims 1 to 3, wherein a second diode circuit (D4) is provided between the negative output node (114) and a node (106) connecting the first and second power transistors (T1, T2).

8. The power factor correction boost circuit of claim 6, further comprising a second output capacitor (C2) connected in series between the second diode circuit (D3, D4) and the reference potential node (104).

9. The PFC boost circuit of claim 7, further comprising a second output capacitor (C2) connected in series between said second diode circuit (D4) and said reference potential node (104).

10. The power factor correction boost circuit according to one of claims 1 to 3, further comprising a first symmetric diode (D7) connected between the reference potential node (104) and a node (108) connecting the two diode elements of the first diode circuit (D1, D2).

11. The PFC boost circuit of claim 7, further comprising a second symmetric diode (D8) connected between the reference potential node (104) and a node (110) connecting the two diode elements of the second diode circuit (D4).

12. The pfc boost circuit of claim 8, further comprising a second symmetric diode (D8) connected between the reference potential node (104) and a node (110) connecting the two diode elements of the second diode circuit (D3, D4).

13. The pfc boost circuit of claim 9, further comprising a second symmetric diode (D8) connected between the reference potential node (104) and a node (110) connecting the two diode elements of the second diode circuit (D4).

14. The power factor correction boost circuit according to one of claims 1 to 3, wherein the first and second power transistors (T1, T2) are controlled by a common gate driver.