CN107544343B - Wireless communication frequency hopping controller - Google Patents
Wireless communication frequency hopping controller Download PDFInfo
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- CN107544343B CN107544343B CN201710881664.7A CN201710881664A CN107544343B CN 107544343 B CN107544343 B CN 107544343B CN 201710881664 A CN201710881664 A CN 201710881664A CN 107544343 B CN107544343 B CN 107544343B
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Abstract
The invention provides a wireless communication frequency hopping controller, which comprises an RTC time service circuit, an FPGA control circuit, a storage circuit and a signal analysis circuit, wherein the FPGA control circuit is respectively connected with the RTC time service circuit, the storage circuit and the signal analysis circuit; the invention can quickly realize the frequency hopping control of the wireless communication system, the technical maturity of the composition circuit of the frequency hopping controller is high, and the synchronization performance of the frequency hopping communication system is excellent, thus the invention has good application prospect.
Description
Technical Field
The invention relates to a wireless communication frequency hopping controller, and belongs to the technical field of wireless communication.
Background
The frequency hopping is 'multi-frequency, code selection and frequency keying', namely, a frequency hopping instruction is formed by a pseudo code sequence to control a frequency synthesizer, and the frequency shift keying is selected from a plurality of frequencies. Frequency hopping communication has the capacity of resisting interference and interception and can share frequency spectrum resources, so that the frequency hopping communication has great advantages in the current modern electronic warfare.
The invention designs a frequency hopping controller of a wireless communication system by combining the frequency hopping technical indexes of the conventional wireless communication system, which can be configured with different software codes to realize the frequency hopping control of the wireless communication systems of different models.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a wireless communication frequency hopping controller, which can be configured with different software codes to implement frequency hopping control of different types of wireless communication systems
The invention is realized by the following technical scheme.
The invention provides a wireless communication frequency hopping controller, which comprises an RTC time service circuit, an FPGA control circuit, a storage circuit and a signal analysis circuit, wherein the FPGA control circuit is respectively connected with the RTC time service circuit, the storage circuit and the signal analysis circuit;
the RTC time service circuit is used for completing a time service task of a time reference required by frequency hopping synchronization and is a local time service clock of the frequency hopping controller;
the FPGA control circuit is used for completing the time sequence planning and logic control tasks of the frequency hopping communication system and is an information processor of the frequency hopping controller;
the storage circuit is used for finishing the storage task of the control information and is an information storage unit of the frequency hopping controller;
the signal analysis circuit is used for completing the analysis task of the channel quality information and is a signal collector of the frequency hopping controller.
The FPGA control circuit comprises an FPGA control chip, a resistor R78, a field effect transistor JFET _ P, a light emitting diode, a resistor R79, a resistor R40, a resistor R54, a resistor R16, a resistor R55, a resistor R41, a resistor R56, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R102, a resistor R101, a resistor R100 and a JTAG controller; a pin T18, a pin T17, a pin U18, a pin V17, a pin V18, a pin U17 and a pin L23 of the FPGA control chip are connected in parallel and then grounded, a pin N22, a pin N23, a pin AB23 and a pin AC23 are connected in parallel and then grounded, a pin M22 is connected with a potentiometer RP, a pin M23 is grounded, and a pin M15 is connected with a resistor R78 in series and then connected with a power supply.
A pin N14 of the FPGA control chip is connected with a grid electrode of a field effect transistor JFET _ P, a drain electrode of the field effect transistor JFET _ P is connected with a power supply after being connected with a light-emitting diode and a resistor R79 in series, and a source electrode of the field effect transistor JFET _ P is grounded;
a pin AD21 of the FPGA control chip is connected with a resistor R40 and a resistor R54 in parallel, a pin AD22 is connected with a resistor R16 and a resistor R55 in parallel, a pin AC22 is connected with a resistor R41 and a resistor R56 in parallel, a resistor R54, a resistor R55 and a resistor R56 are connected with a power supply after being connected with the power supply in parallel, and the resistor R40, the resistor R16 and the resistor R41 are connected with the ground after being connected with the power supply in parallel;
the pin N15 of the FPGA control chip is a clock signal interface of the FPGA, and the pin AB15, the pin AC14, the pin AC15 and the pin AD14 are respectively connected with a TCK pin, a TMS pin, a TDI pin and a TDO pin of the JTAG controller.
The FPGA control chip comprises a pin L and a resistor R, a pin J and a resistor R, a pin K and a resistor R, a pin J and a resistor R, a pin H and a resistor R, a pin G and a resistor R, a pin L and a resistor R, a pin K and a resistor R, a pin G and a resistor R, a pin H and a resistor R, a pin K and a resistor R102, a pin A and a resistor R101, a pin AE and a resistor R100 which are connected in series, wherein the resistor R, the resistor R19, the resistor R102, the resistor R101 and the resistor R100 are connected in parallel and then grounded.
The power supply is 3.3V, the resistor R78 is 330 omega, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, the resistor R19, the resistor R79, the resistor R102, the resistor R101 and the resistor R100 are all 1K omega, and the resistor R54, the resistor R55 and the resistor R56 are all 4.7K omega.
The RTC time service circuit comprises an RTC time service chip, wherein a pin 1 and a pin 12 of the RTC time service chip are respectively grounded, a pin 24 is connected with a direct current power supply, and the size of the direct current power supply is 3.3V;
the pin 11 of the RTC time service chip is connected with the pin AF15 of the FPGA control chip, the pin 10 of the RTC time service chip is connected with the pin AE16 of the FPGA control chip, the pin 9 of the RTC time service chip is connected with the pin AE21 of the FPGA control chip, the pin 8 of the RTC time service chip is connected with the pin AD20 of the FPGA control chip, the pin 7 of the RTC time service chip is connected with the pin AF16 of the FPGA control chip, the pin 6 of the RTC time service chip is connected with the pin AE17 of the FPGA control chip, the pin 5 of the RTC time service chip is connected with the pin AE19 of the FPGA control chip, and the pin 4 of the RTC time service chip is connected with the pin AD19 of the;
the pin 23 of the RTC time service chip is connected with the pin H18 of the FPGA control chip, the pin 18 of the RTC time service chip is connected with the pin K17 of the FPGA control chip, the pin 17 of the RTC time service chip is connected with the pin G15 of the FPGA control chip, the pin 15 of the RTC time service chip is connected with the pin L18 of the FPGA control chip, the pin 14 of the RTC time service chip is connected with the pin G16 of the FPGA control chip, the pin 13 of the RTC time service chip is connected with the pin K18 of the FPGA control chip, and the pin 19 of the RTC time service chip is an IRQ interface.
The memory circuit comprises a memory chip, a pin A1 of the memory chip, a pin B17 of the FPGA control chip, a pin B1 of the memory chip, a pin A14 of the FPGA control chip, a pin C1 of the memory chip, a pin A15 of the FPGA control chip, a pin D1 of the memory chip, a pin B15 of the FPGA control chip, a pin D2 of the memory chip, a pin B16 of the FPGA control chip, a pin A2 of the memory chip, a pin AG17 of the FPGA control chip, a pin C2 of the memory chip, a pin AH18 of the FPGA control chip, a pin A3 of the memory chip, a pin AE18 of the FPGA control chip, a pin B3 of the memory chip, a pin AF18 of the FPGA control chip, a pin C3 of the memory chip, a pin AG16 of the FPGA control chip, a pin D3 of the memory chip, a pin AH17 of the FPGA control chip, a pin C17 of the memory chip, an AF 17 of the FPGA control chip, and an AF 17 of the pin AG17 of the FPGA control chip, A pin B5 of the memory chip and a pin AG15 of the FPGA control chip, a pin C5 of the memory chip and a pin AH15 of the FPGA control chip, a pin D7 of the memory chip and a pin AG20 of the FPGA control chip, a pin D8 of the memory chip and a pin AG21 of the FPGA control chip, a pin A7 of the memory chip and a pin AH13 of the FPGA control chip, a pin B7 of the memory chip and a pin D22 of the FPGA control chip, a pin C7 of the memory chip and a pin AE23 of the FPGA control chip, a pin C8 of the memory chip and a pin AE23 of the FPGA control chip, a pin A8 of the memory chip and a pin AH14 of the FPGA control chip, and a pin G1 and a pin H8 of the memory chip are both connected with a pin AH19 of the FPGA control chip;
the pin F2 of the memory chip and the pin AK16 of the FPGA control chip, the pin E2 of the memory chip and the pin AL16 of the FPGA control chip, the pin G3 of the memory chip and the pin AL21 of the FPGA control chip, the pin E4 of the memory chip and the pin AK21 of the FPGA control chip, the pin E5 of the memory chip and the pin AK17 of the FPGA control chip, the pin G5 of the memory chip and the pin AJ17 of the FPGA control chip, the pin G6 of the memory chip and the pin AL19 of the FPGA control chip, the pin H7 of the memory chip and the pin AL20 of the FPGA control chip, the pin E20 of the memory chip and the pin AK 20 of the FPGA control chip, the pin E20 of the memory chip and the pin AL20 of the FPGA control chip, the pin F20 of the memory chip and the pin AL20 of the FPGA control chip, and the pin AM 20 of the memory chip and the pin AM 20 of the FPGA control chip, the pin F20 of the pin 20 of the memory chip and the pin AM 20 of the FPGA control chip, and the pin 20 of the memory chip, A pin G7 of the memory chip is connected with a pin AP16 of the FPGA control chip, and a pin E7 of the memory chip is connected with a pin AP17 of the FPGA control chip;
the storage circuit further comprises a resistor RJ7, a resistor RJ8, a resistor RJ9, a resistor RJ10, a resistor RJ11, a resistor RJ12, a resistor R35, a resistor RJ13, a resistor RJ14, a resistor RJ15, a resistor RJ16 and a programmable read-only memory PROM, wherein a pin F7 of the storage chip is connected with the resistor R42 in series and then is connected with a pin J20 of the FPGA control chip; the resistor RJ7, the resistor RJ8, the resistor RJ9, the resistor RJ10, the resistor RJ11 and the resistor RJ12 are connected in parallel, one ends of the resistor RJ7, the resistor RJ8 and the resistor RJ9 are connected with a direct-current power supply, and one ends of the resistor RJ10, the resistor RJ11 and the resistor RJ12 are grounded; a pin F8 of the storage chip is connected with a resistor RJ7 and a resistor RJ10 in parallel and then connected with a pin H13 of the FPGA control chip, a pin G8 is connected with a resistor RJ8 and a resistor RJ11 in parallel and then connected with a pin H19 of the FPGA control chip, and a pin B4 is connected with a resistor RJ9 and a resistor RJ12 in parallel and then connected with a pin J14 of the FPGA control chip; a pin E6 and a pin F6 of the memory chip are connected with a resistor R35 in series and then grounded, a pin C6 and a pin A4 are respectively connected with a resistor RJ14 and a resistor RJ16 in series, a pin D4 is connected with the resistor RJ13 and the resistor RJ15 in parallel, one end of the resistor RJ15 is grounded, and the resistor RJ13, the resistor RJ15, the resistor RJ14 and the resistor RJ16 are connected with a direct-current power supply in parallel and then grounded; a pin H2, a pin H4, a pin H6 and a pin B2 of the memory chip are connected in parallel and then grounded, a pin G4, a pin D5 and a pin D6 are connected in parallel and then connected with a direct current power supply, and a pin A6 and a pin H31 are connected in parallel and then connected with a programmable read-only memory (PROM).
The direct current power supply is 3.3V, the sizes of the resistor RJ7, the resistor RJ8, the resistor RJ9, the resistor RJ14 and the resistor RJ16 are all 4.7K omega, and the voltage of the programmable read-only memory PROM is 1.8V.
The signal analysis circuit comprises a signal analysis chip, an analog-to-digital converter AD, a capacitor C21, a resistor R106, a resistor R107, a capacitor C22, a capacitor C23, an active crystal oscillator, a capacitor C24, a capacitor C25, a resistor R108, a resistor R109, a capacitor C18, a resistor R105, a capacitor C17, a capacitor C19, a resistor R180, a resistor R170 and a resistor R190; the pin 1 and the pin 21 of the signal analysis chip are respectively connected with an analog-to-digital converter (AD), the pin 57 and the pin 24 are respectively connected with a direct-current power supply, the pin 36, the pin 45 and the pin 46 are respectively connected with an alternating-current power supply, the pin 37 and the pin 44 are positive-direction input ends, the pin 38 and the pin 43 are reverse-direction input ends, and the pin 41 is a CML interface; the pin 49 of the signal analysis chip is connected with a capacitor C21, a resistor R106, a resistor R107 and a capacitor C22 in series, a capacitor C22 is connected with a capacitor C23 in parallel, and one end of each of the capacitor C22 and the capacitor C23 is a first signal input end and a second signal input end respectively;
the pin 3 of the active crystal oscillator is connected with a resistor R107 and a resistor R106 in parallel and outputs 32MHZ clock frequency, the pin 2 is grounded, the pin 1 is grounded after being connected with a capacitor C24 in series, the pin 4 is connected with a resistor R108, a resistor 109 and a capacitor C25 in parallel, one ends of the capacitor C25 and the resistor R109 are grounded respectively, one end of the resistor R108 is connected with an analog-to-digital converter AD, and the capacitor C24 is connected with the resistors R108 and R109 in parallel;
the pin 50 of the signal analysis chip is connected with the capacitor C18 and the resistor R105 in parallel and then grounded, the pin 39 is connected with the capacitor C17, the capacitor C19, the resistor R180 and the resistor R170 in parallel, one end of the resistor R170 is grounded, the pin 40 is connected with the resistor R180 and the resistor R170 in parallel, the pin 42 is connected with the resistor R190 in series and then grounded, and the pin 65 is grounded;
the pin 33 of the signal analysis chip is connected with the pin J17 of the FPGA control chip, the pin 34 of the signal analysis chip is connected with the pin L19 of the FPGA control chip, the pin 35 of the signal analysis chip is connected with the pin K19 of the FPGA control chip, the pin 47 of the signal analysis chip is connected with the pin AH12 of the FPGA control chip, the pin 48 of the signal analysis chip is connected with the pin AG13 of the FPGA control chip, the pin 51 of the signal analysis chip is connected with the pin AH20 of the FPGA control chip, and the pin 52 of the signal analysis chip is connected with the pin AJ21 of the FPGA control chip;
the pin 12 of the signal analysis chip and the pin E16 of the FPGA control chip, the pin 13 of the signal analysis chip and the pin E17 of the FPGA control chip, the pin 14 of the signal analysis chip and the pin E14 of the FPGA control chip, the pin 15 of the signal analysis chip and the pin D14 of the FPGA control chip, the pin 16 of the signal analysis chip and the pin F20 of the FPGA control chip, the pin 17 of the signal analysis chip and the pin G20 of the FPGA control chip, the pin 18 of the signal analysis chip and the pin D15 of the FPGA control chip, the pin 19 of the signal analysis chip and the pin D16 of the FPGA control chip, the pin 22 of the signal analysis chip and the pin D20 of the FPGA control chip, the pin 23 of the signal analysis chip and the pin E21 of the FPGA control chip, the pin 25 of the signal analysis chip and the pin D17 of the FPGA control chip, the pin 26 of the signal analysis chip and the pin C17 of the FPGA control chip, the pin 27 of the signal analysis chip and the pin F19 of the FPGA control chip, The pin 28 of the signal analysis chip is connected with a pin E19 of the FPGA control chip;
the pin 11 of the signal analysis chip is connected with the pin G18 of the FPGA control chip, the pin 56 of the signal analysis chip is connected with the pin AJ14 of the FPGA control chip, the pin 55 of the signal analysis chip is connected with the pin AL23 of the FPGA control chip, the pin 54 of the signal analysis chip is connected with the pin AK24 of the FPGA control chip, the pin 53 of the signal analysis chip is connected with the pin AK13 of the FPGA control chip, and the pin 10 of the signal analysis chip is connected with the pin AK23 of the FPGA control chip;
the pin 9 of the signal analysis chip and the pin F16 of the FPGA control chip, the pin 8 of the signal analysis chip and the pin D24 of the FPGA control chip, the pin 7 of the signal analysis chip and the pin E23 of the FPGA control chip, the pin 6 of the signal analysis chip and the pin F14 of the FPGA control chip, the pin 5 of the signal analysis chip and the pin F15 of the FPGA control chip, the pin 4 of the signal analysis chip and the pin F24 of the FPGA control chip, the pin 3 of the signal analysis chip and the pin E24 of the FPGA control chip, the pin 2 of the signal analysis chip and the pin AH24 of the FPGA control chip, the pin 63 of the signal analysis chip and the pin AJ24 of the FPGA control chip, the pin 62 of the signal analysis chip and the pin AK12 of the FPGA control chip, the pin 61 of the signal analysis chip and the pin AJ12 of the FPGA control chip, the pin 60 of the signal analysis chip and the pin AH23 of the signal analysis chip, the pin 59 of the signal analysis chip and the pin AJ22 of the FPGA control chip, Pin 58 of the signal analysis chip is connected to pin AL13 of the FPGA control chip.
The voltage of the analog-to-digital converter AD is 3.3V, the direct current power supply is 1.8V, the alternating current power supply is 1.8V, the input frequencies of the first signal input end and the second signal input end are both 18.432MHZ, the sizes of the capacitor C21, the capacitor C22, the capacitor C23, the capacitor C24, the capacitor C18, the capacitor C17 and the capacitor C19 are all 0.1UF, the size of the capacitor C25 is 0.01UF, the sizes of the resistor R106 and the resistor R107 are all 100 omega, the sizes of the resistor R108, the resistor R190 and the resistor R109 are all 10K omega, the size of the resistor R105 is 39K omega, and the size of the resistor R170 is 0 omega.
The invention has the beneficial effects that: the frequency hopping controller can quickly realize frequency hopping control of a wireless communication system, has high technical maturity of the composition circuit of the frequency hopping controller, realizes excellent synchronization performance of the frequency hopping communication system, and is an invention with good application prospect.
Drawings
FIG. 1 is an FPGA control circuit of the present invention;
FIG. 2 is a RTC timing circuit of the present invention;
FIG. 3 is a memory circuit of the present invention;
FIG. 4 is a signal analysis circuit of the present invention;
FIG. 5 is an enlarged view of FIG. 1A;
FIG. 6 is an enlarged view of FIG. 1B;
fig. 7 is a schematic structural view of the present invention.
Detailed Description
The technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.
As shown in fig. 7, a wireless communication frequency hopping controller includes an RTC time service circuit, an FPGA control circuit, a storage circuit, and a signal analysis circuit, where the FPGA control circuit is connected to the RTC time service circuit, the storage circuit, and the signal analysis circuit respectively;
the RTC time service circuit is used for completing a time service task of a time reference required by frequency hopping synchronization and is a local time service clock of the frequency hopping controller;
the FPGA control circuit is used for completing the time sequence planning and logic control tasks of the frequency hopping communication system and is an information processor of the frequency hopping controller;
the storage circuit is used for finishing the storage task of the control information and is an information storage unit of the frequency hopping controller;
the signal analysis circuit is used for completing the analysis task of the channel quality information and is a signal collector of the frequency hopping controller.
As shown in fig. 1, 5 and 6, the FPGA control circuit includes an FPGA control chip, a resistor R78, a field effect transistor JFET _ P, a light emitting diode, a resistor R79, a resistor R40, a resistor R54, a resistor R16, a resistor R55, a resistor R41, a resistor R56, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R102, a resistor R101, a resistor R100, and a JTAG controller; a pin T18, a pin T17, a pin U18, a pin V17, a pin V18, a pin U17 and a pin L23 of the FPGA control chip are connected in parallel and then grounded, a pin N22, a pin N23, a pin AB23 and a pin AC23 are connected in parallel and then grounded, a pin M22 is connected with a potentiometer RP, a pin M23 is grounded, and a pin M15 is connected with a resistor R78 in series and then connected with a power supply.
A pin N14 of the FPGA control chip is connected with a grid electrode of a field effect transistor JFET _ P, a drain electrode of the field effect transistor JFET _ P is connected with a power supply after being connected with a light-emitting diode and a resistor R79 in series, and a source electrode of the field effect transistor JFET _ P is grounded;
a pin AD21 of the FPGA control chip is connected with a resistor R40 and a resistor R54 in parallel, a pin AD22 is connected with a resistor R16 and a resistor R55 in parallel, a pin AC22 is connected with a resistor R41 and a resistor R56 in parallel, a resistor R54, a resistor R55 and a resistor R56 are connected with a power supply after being connected with the power supply in parallel, and the resistor R40, the resistor R16 and the resistor R41 are connected with the ground after being connected with the power supply in parallel;
the pin N15 of the FPGA control chip is a clock signal interface of the FPGA, and the pin AB15, the pin AC14, the pin AC15 and the pin AD14 are respectively connected with a TCK pin, a TMS pin, a TDI pin and a TDO pin of the JTAG controller.
The FPGA control chip comprises a pin L and a resistor R, a pin J and a resistor R, a pin K and a resistor R, a pin J and a resistor R, a pin H and a resistor R, a pin G and a resistor R, a pin L and a resistor R, a pin K and a resistor R, a pin G and a resistor R, a pin H and a resistor R, a pin K and a resistor R102, a pin A and a resistor R101, a pin AE and a resistor R100 which are connected in series, wherein the resistor R, the resistor R19, the resistor R102, the resistor R101 and the resistor R100 are connected in parallel and then grounded.
The power supply is 3.3V, the resistor R78 is 330 omega, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, the resistor R19, the resistor R79, the resistor R102, the resistor R101 and the resistor R100 are all 1K omega, and the resistor R54, the resistor R55 and the resistor R56 are all 4.7K omega.
As shown in fig. 2, the RTC time service circuit includes an RTC time service chip, a pin 1 and a pin 12 of the RTC time service chip are respectively grounded, a pin 24 is connected to a dc power supply, and the dc power supply has a voltage of 3.3V;
the pin 11 of the RTC time service chip is connected with the pin AF15 of the FPGA control chip, the pin 10 of the RTC time service chip is connected with the pin AE16 of the FPGA control chip, the pin 9 of the RTC time service chip is connected with the pin AE21 of the FPGA control chip, the pin 8 of the RTC time service chip is connected with the pin AD20 of the FPGA control chip, the pin 7 of the RTC time service chip is connected with the pin AF16 of the FPGA control chip, the pin 6 of the RTC time service chip is connected with the pin AE17 of the FPGA control chip, the pin 5 of the RTC time service chip is connected with the pin AE19 of the FPGA control chip, and the pin 4 of the RTC time service chip is connected with the pin AD19 of the;
the pin 23 of the RTC time service chip is connected with the pin H18 of the FPGA control chip, the pin 18 of the RTC time service chip is connected with the pin K17 of the FPGA control chip, the pin 17 of the RTC time service chip is connected with the pin G15 of the FPGA control chip, the pin 15 of the RTC time service chip is connected with the pin L18 of the FPGA control chip, the pin 14 of the RTC time service chip is connected with the pin G16 of the FPGA control chip, and the pin 13 of the RTC time service chip is connected with the pin K18 of the FPGA control chip, the pin 19 of the RTC time service chip is an IRQ interface, namely an interrupt request, and the IRQ interface is used for executing the action of a hardware interrupt request in a used computer.
As shown in fig. 3, the memory circuit includes a memory chip, a pin a1 of the memory chip and a pin B17 of the FPGA control chip, a pin B1 of the memory chip and a pin a14 of the FPGA control chip, a pin C1 of the memory chip and a pin a15 of the FPGA control chip, a pin D1 of the memory chip and a pin B15 of the FPGA control chip, a pin D2 of the memory chip and a pin B16 of the FPGA control chip, a pin a2 of the memory chip and a pin AG17 of the FPGA control chip, a pin C2 of the memory chip and a pin AH18 of the FPGA control chip, a pin A3 of the memory chip and a pin AE18 of the FPGA control chip, a pin B3 of the memory chip and a pin AF18 of the FPGA control chip, a pin C3 of the memory chip and a pin AG 597 of the FPGA control chip, a pin D3 of the memory chip and a pin AH 72 of the FPGA control chip, a pin C17 of the FPGA control chip and a pin 36 16 2 of the FPGA control chip, a pin C17 of the FPGA control chip, A pin B5 of the memory chip and a pin AG15 of the FPGA control chip, a pin C5 of the memory chip and a pin AH15 of the FPGA control chip, a pin D7 of the memory chip and a pin AG20 of the FPGA control chip, a pin D8 of the memory chip and a pin AG21 of the FPGA control chip, a pin A7 of the memory chip and a pin AH13 of the FPGA control chip, a pin B7 of the memory chip and a pin D22 of the FPGA control chip, a pin C7 of the memory chip and a pin AE23 of the FPGA control chip, a pin C8 of the memory chip and a pin AE23 of the FPGA control chip, a pin A8 of the memory chip and a pin AH14 of the FPGA control chip, and a pin G1 and a pin H8 of the memory chip are both connected with a pin AH19 of the FPGA control chip;
the pin F2 of the memory chip and the pin AK16 of the FPGA control chip, the pin E2 of the memory chip and the pin AL16 of the FPGA control chip, the pin G3 of the memory chip and the pin AL21 of the FPGA control chip, the pin E4 of the memory chip and the pin AK21 of the FPGA control chip, the pin E5 of the memory chip and the pin AK17 of the FPGA control chip, the pin G5 of the memory chip and the pin AJ17 of the FPGA control chip, the pin G6 of the memory chip and the pin AL19 of the FPGA control chip, the pin H7 of the memory chip and the pin AL20 of the FPGA control chip, the pin E20 of the memory chip and the pin AK 20 of the FPGA control chip, the pin E20 of the memory chip and the pin AL20 of the FPGA control chip, the pin F20 of the memory chip and the pin AL20 of the FPGA control chip, and the pin AM 20 of the memory chip and the pin AM 20 of the FPGA control chip, the pin F20 of the pin 20 of the memory chip and the pin AM 20 of the FPGA control chip, and the pin 20 of the memory chip, A pin G7 of the memory chip is connected with a pin AP16 of the FPGA control chip, and a pin E7 of the memory chip is connected with a pin AP17 of the FPGA control chip;
the storage circuit further comprises a resistor RJ7, a resistor RJ8, a resistor RJ9, a resistor RJ10, a resistor RJ11, a resistor RJ12, a resistor R35, a resistor RJ13, a resistor RJ14, a resistor RJ15, a resistor RJ16 and a programmable read-only memory PROM, wherein a pin F7 of the storage chip is connected with the resistor R42 in series and then is connected with a pin J20 of the FPGA control chip; the resistor RJ7, the resistor RJ8, the resistor RJ9, the resistor RJ10, the resistor RJ11 and the resistor RJ12 are connected in parallel, one ends of the resistor RJ7, the resistor RJ8 and the resistor RJ9 are connected with a direct-current power supply, and one ends of the resistor RJ10, the resistor RJ11 and the resistor RJ12 are grounded; a pin F8 of the storage chip is connected with a resistor RJ7 and a resistor RJ10 in parallel and then connected with a pin H13 of the FPGA control chip, a pin G8 is connected with a resistor RJ8 and a resistor RJ11 in parallel and then connected with a pin H19 of the FPGA control chip, and a pin B4 is connected with a resistor RJ9 and a resistor RJ12 in parallel and then connected with a pin J14 of the FPGA control chip; a pin E6 and a pin F6 of the memory chip are connected with a resistor R35 in series and then grounded, a pin C6 and a pin A4 are respectively connected with a resistor RJ14 and a resistor RJ16 in series, a pin D4 is connected with the resistor RJ13 and the resistor RJ15 in parallel, one end of the resistor RJ15 is grounded, and the resistor RJ13, the resistor RJ15, the resistor RJ14 and the resistor RJ16 are connected with a direct-current power supply in parallel and then grounded; a pin H2, a pin H4, a pin H6 and a pin B2 of the memory chip are connected in parallel and then grounded, a pin G4, a pin D5 and a pin D6 are connected in parallel and then connected with a direct current power supply, and a pin A6 and a pin H31 are connected in parallel and then connected with a programmable read-only memory (PROM).
The direct current power supply is 3.3V, the sizes of the resistor RJ7, the resistor RJ8, the resistor RJ9, the resistor RJ14 and the resistor RJ16 are all 4.7K omega, and the voltage of the programmable read-only memory PROM is 1.8V.
As shown in fig. 4, the signal analysis circuit includes a signal analysis chip, an analog-to-digital converter AD, a capacitor C21, a resistor R106, a resistor R107, a capacitor C22, a capacitor C23, an active crystal oscillator, a capacitor C24, a capacitor C25, a resistor R108, a resistor R109, a capacitor C18, a resistor R105, a capacitor C17, a capacitor C19, a resistor R180, a resistor R170, and a resistor R190; pin 1 and pin 21 of the signal analysis chip are respectively connected with an analog-to-digital converter (AD), pin 57 and pin 24 are respectively connected with a direct-current power supply, pin 36, pin 45 and pin 46 are respectively connected with an alternating-current power supply, pin 37 and pin 44 are positive input ends, pin 38 and pin 43 are negative input ends, pin 41 is a CML interface, the CML interface is current mode logic and mainly driven by current, the CML interface is the simplest one of all high-speed data interface forms, and the input and output of the CML interface are well matched, so that peripheral devices are reduced; the pin 49 of the signal analysis chip is connected with a capacitor C21, a resistor R106, a resistor R107 and a capacitor C22 in series, a capacitor C22 is connected with a capacitor C23 in parallel, and one end of each of the capacitor C22 and the capacitor C23 is a first signal input end and a second signal input end respectively;
the pin 3 of the active crystal oscillator is connected in parallel with a resistor R107 and a resistor R106 and outputs 32MHZ clock frequency, the pin 2 is grounded, the pin 1 is grounded after being connected in series with a capacitor C24, the pin 4 is connected in parallel with a resistor R108, a resistor 109 and a capacitor C25, one ends of the capacitor C25 and the resistor R109 are grounded respectively, one end of the resistor R108 is connected with an analog-to-digital converter AD, and the capacitor C24 is connected in parallel with the resistors R108 and R109. (ii) a
The pin 50 of the signal analysis chip is connected with the capacitor C18 and the resistor R105 in parallel and then grounded, the pin 39 is connected with the capacitor C17, the capacitor C19, the resistor R180 and the resistor R170 in parallel, one end of the resistor R170 is grounded, the pin 40 is connected with the resistor R180 and the resistor R170 in parallel, the pin 42 is connected with the resistor R190 in series and then grounded, and the pin 65 is grounded;
the pin 33 of the signal analysis chip is connected with the pin J17 of the FPGA control chip, the pin 34 of the signal analysis chip is connected with the pin L19 of the FPGA control chip, the pin 35 of the signal analysis chip is connected with the pin K19 of the FPGA control chip, the pin 47 of the signal analysis chip is connected with the pin AH12 of the FPGA control chip, the pin 48 of the signal analysis chip is connected with the pin AG13 of the FPGA control chip, the pin 51 of the signal analysis chip is connected with the pin AH20 of the FPGA control chip, and the pin 52 of the signal analysis chip is connected with the pin AJ21 of the FPGA control chip;
the pin 12 of the signal analysis chip and the pin E16 of the FPGA control chip, the pin 13 of the signal analysis chip and the pin E17 of the FPGA control chip, the pin 14 of the signal analysis chip and the pin E14 of the FPGA control chip, the pin 15 of the signal analysis chip and the pin D14 of the FPGA control chip, the pin 16 of the signal analysis chip and the pin F20 of the FPGA control chip, the pin 17 of the signal analysis chip and the pin G20 of the FPGA control chip, the pin 18 of the signal analysis chip and the pin D15 of the FPGA control chip, the pin 19 of the signal analysis chip and the pin D16 of the FPGA control chip, the pin 22 of the signal analysis chip and the pin D20 of the FPGA control chip, the pin 23 of the signal analysis chip and the pin E21 of the FPGA control chip, the pin 25 of the signal analysis chip and the pin D17 of the FPGA control chip, the pin 26 of the signal analysis chip and the pin C17 of the FPGA control chip, the pin 27 of the signal analysis chip and the pin F19 of the FPGA control chip, The pin 28 of the signal analysis chip is connected with a pin E19 of the FPGA control chip;
the pin 11 of the signal analysis chip is connected with the pin G18 of the FPGA control chip, the pin 56 of the signal analysis chip is connected with the pin AJ14 of the FPGA control chip, the pin 55 of the signal analysis chip is connected with the pin AL23 of the FPGA control chip, the pin 54 of the signal analysis chip is connected with the pin AK24 of the FPGA control chip, the pin 53 of the signal analysis chip is connected with the pin AK13 of the FPGA control chip, and the pin 10 of the signal analysis chip is connected with the pin AK23 of the FPGA control chip;
the pin 9 of the signal analysis chip and the pin F16 of the FPGA control chip, the pin 8 of the signal analysis chip and the pin D24 of the FPGA control chip, the pin 7 of the signal analysis chip and the pin E23 of the FPGA control chip, the pin 6 of the signal analysis chip and the pin F14 of the FPGA control chip, the pin 5 of the signal analysis chip and the pin F15 of the FPGA control chip, the pin 4 of the signal analysis chip and the pin F24 of the FPGA control chip, the pin 3 of the signal analysis chip and the pin E24 of the FPGA control chip, the pin 2 of the signal analysis chip and the pin AH24 of the FPGA control chip, the pin 63 of the signal analysis chip and the pin AJ24 of the FPGA control chip, the pin 62 of the signal analysis chip and the pin AK12 of the FPGA control chip, the pin 61 of the signal analysis chip and the pin AJ12 of the FPGA control chip, the pin 60 of the signal analysis chip and the pin AH23 of the signal analysis chip, the pin 59 of the signal analysis chip and the pin AJ22 of the FPGA control chip, Pin 58 of the signal analysis chip is connected to pin AL13 of the FPGA control chip.
The voltage of the analog-to-digital converter AD is 3.3V, the direct current power supply is 1.8V, the alternating current power supply is 1.8V, the input frequencies of the first signal input end and the second signal input end are both 18.432MHZ, the sizes of the capacitor C21, the capacitor C22, the capacitor C23, the capacitor C24, the capacitor C18, the capacitor C17 and the capacitor C19 are all 0.1UF, the size of the capacitor C25 is 0.01UF, the sizes of the resistor R106 and the resistor R107 are all 100 omega, the sizes of the resistor R108, the resistor R190 and the resistor R109 are all 10K omega, the size of the resistor R105 is 39K omega, and the size of the resistor R170 is 0 omega.
In summary, after the present invention is powered on, the RTC time service circuit shown in fig. 2 transmits a local clock to the FPGA control circuit shown in fig. 1, the FPGA control circuit shown in fig. 1 reads an initial configuration state of a system in the storage circuit shown in fig. 3, and in combination with a reference clock provided by the RTC time service circuit shown in fig. 2, frequency hopping synchronization of the wireless communication system is realized through control logic and an algorithm, and a communication link of the wireless communication system is established, wherein the signal analysis circuit shown in fig. 4 collects current channel quality information and transmits the collected information to the FPGA control circuit shown in fig. 1, and the FPGA control circuit shown in fig. 1 analyzes current channel quality through FFT calculation, and according to an analysis result, self-adaptive frequency hopping of the wireless communication system is realized.
Claims (7)
1. A wireless communication frequency hopping controller, characterized by: the FPGA control circuit is respectively connected with the RTC time service circuit, the storage circuit and the signal analysis circuit;
the RTC time service circuit is used for completing a time service task of a time reference required by frequency hopping synchronization and is a local time service clock of the frequency hopping controller;
the RTC time service circuit comprises an RTC time service chip, wherein a pin 1 and a pin 12 of the RTC time service chip are respectively grounded, a pin 24 is connected with a direct current power supply, and the size of the direct current power supply is 3.3V;
the pin 11 of the RTC time service chip is connected with the pin AF15 of the FPGA control chip, the pin 10 of the RTC time service chip is connected with the pin AE16 of the FPGA control chip, the pin 9 of the RTC time service chip is connected with the pin AE21 of the FPGA control chip, the pin 8 of the RTC time service chip is connected with the pin AD20 of the FPGA control chip, the pin 7 of the RTC time service chip is connected with the pin AF16 of the FPGA control chip, the pin 6 of the RTC time service chip is connected with the pin AE17 of the FPGA control chip, the pin 5 of the RTC time service chip is connected with the pin AE19 of the FPGA control chip, and the pin 4 of the RTC time service chip is connected with the pin AD19 of the;
the pin 23 of the RTC time service chip is connected with the pin H18 of the FPGA control chip, the pin 18 of the RTC time service chip is connected with the pin K17 of the FPGA control chip, the pin 17 of the RTC time service chip is connected with the pin G15 of the FPGA control chip, the pin 15 of the RTC time service chip is connected with the pin L18 of the FPGA control chip, the pin 14 of the RTC time service chip is connected with the pin G16 of the FPGA control chip, the pin 13 of the RTC time service chip is connected with the pin K18 of the FPGA control chip, and the pin 19 of the RTC time service chip is an IRQ interface;
the FPGA control circuit is used for completing the time sequence planning and logic control tasks of the frequency hopping communication system and is an information processor of the frequency hopping controller;
the storage circuit is used for finishing the storage task of the control information and is an information storage unit of the frequency hopping controller;
the signal analysis circuit is used for completing the analysis task of the channel quality information and is a signal collector of the frequency hopping controller;
the memory circuit comprises a memory chip, a pin A1 of the memory chip, a pin B17 of the FPGA control chip, a pin B1 of the memory chip, a pin A14 of the FPGA control chip, a pin C1 of the memory chip, a pin A15 of the FPGA control chip, a pin D1 of the memory chip, a pin B15 of the FPGA control chip, a pin D2 of the memory chip, a pin B16 of the FPGA control chip, a pin A2 of the memory chip, a pin AG17 of the FPGA control chip, a pin C2 of the memory chip, a pin AH18 of the FPGA control chip, a pin A3 of the memory chip, a pin AE18 of the FPGA control chip, a pin B3 of the memory chip, a pin AF18 of the FPGA control chip, a pin C3 of the memory chip, a pin AG16 of the FPGA control chip, a pin D3 of the memory chip, a pin AH17 of the FPGA control chip, a pin C17 of the memory chip, an AF 17 of the FPGA control chip, and an AF 17 of the pin AG17 of the FPGA control chip, A pin B5 of the memory chip and a pin AG15 of the FPGA control chip, a pin C5 of the memory chip and a pin AH15 of the FPGA control chip, a pin D7 of the memory chip and a pin AG20 of the FPGA control chip, a pin D8 of the memory chip and a pin AG21 of the FPGA control chip, a pin A7 of the memory chip and a pin AH13 of the FPGA control chip, a pin B7 of the memory chip and a pin D22 of the FPGA control chip, a pin C7 of the memory chip and a pin AE23 of the FPGA control chip, a pin C8 of the memory chip and a pin AE23 of the FPGA control chip, a pin A8 of the memory chip and a pin AH14 of the FPGA control chip, and a pin G1 and a pin H8 of the memory chip are both connected with a pin AH19 of the FPGA control chip;
the pin F2 of the memory chip and the pin AK16 of the FPGA control chip, the pin E2 of the memory chip and the pin AL16 of the FPGA control chip, the pin G3 of the memory chip and the pin AL21 of the FPGA control chip, the pin E4 of the memory chip and the pin AK21 of the FPGA control chip, the pin E5 of the memory chip and the pin AK17 of the FPGA control chip, the pin G5 of the memory chip and the pin AJ17 of the FPGA control chip, the pin G6 of the memory chip and the pin AL19 of the FPGA control chip, the pin H7 of the memory chip and the pin AL20 of the FPGA control chip, the pin E20 of the memory chip and the pin AK 20 of the FPGA control chip, the pin E20 of the memory chip and the pin AL20 of the FPGA control chip, the pin F20 of the memory chip and the pin AL20 of the FPGA control chip, and the pin AM 20 of the memory chip and the pin AM 20 of the FPGA control chip, the pin F20 of the pin 20 of the memory chip and the pin AM 20 of the FPGA control chip, and the pin 20 of the memory chip, A pin G7 of the memory chip is connected with a pin AP16 of the FPGA control chip, and a pin E7 of the memory chip is connected with a pin AP17 of the FPGA control chip;
the storage circuit further comprises a resistor RJ7, a resistor RJ8, a resistor RJ9, a resistor RJ10, a resistor RJ11, a resistor RJ12, a resistor R35, a resistor RJ13, a resistor RJ14, a resistor RJ15, a resistor RJ16 and a programmable read-only memory PROM, wherein a pin F7 of the storage chip is connected with the resistor R42 in series and then is connected with a pin J20 of the FPGA control chip;
the resistor RJ7, the resistor RJ8, the resistor RJ9, the resistor RJ10, the resistor RJ11 and the resistor RJ12 are connected in parallel, one ends of the resistor RJ7, the resistor RJ8 and the resistor RJ9 are connected with a direct-current power supply, and one ends of the resistor RJ10, the resistor RJ11 and the resistor RJ12 are grounded;
a pin F8 of the storage chip is connected with a resistor RJ7 and a resistor RJ10 in parallel and then connected with a pin H13 of the FPGA control chip, a pin G8 is connected with a resistor RJ8 and a resistor RJ11 in parallel and then connected with a pin H19 of the FPGA control chip, and a pin B4 is connected with a resistor RJ9 and a resistor RJ12 in parallel and then connected with a pin J14 of the FPGA control chip;
a pin E6 and a pin F6 of the memory chip are connected with a resistor R35 in series and then grounded, a pin C6 and a pin A4 are respectively connected with a resistor RJ14 and a resistor RJ16 in series, a pin D4 is connected with the resistor RJ13 and the resistor RJ15 in parallel, one end of the resistor RJ15 is grounded, and the resistor RJ13, the resistor RJ15, the resistor RJ14 and the resistor RJ16 are connected with a direct-current power supply in parallel and then grounded;
a pin H2, a pin H4, a pin H6 and a pin B2 of the memory chip are connected in parallel and then grounded, a pin G4, a pin D5 and a pin D6 are connected in parallel and then connected with a direct current power supply, and a pin A6 and a pin H31 are connected in parallel and then connected with a Programmable Read Only Memory (PROM);
the signal analysis circuit comprises a signal analysis chip, an analog-to-digital converter AD, a capacitor C21, a resistor R106, a resistor R107, a capacitor C22, a capacitor C23, an active crystal oscillator, a capacitor C24, a capacitor C25, a resistor R108, a resistor R109, a capacitor C18, a resistor R105, a capacitor C17, a capacitor C19, a resistor R180, a resistor R170 and a resistor R190; the pin 1 and the pin 21 of the signal analysis chip are respectively connected with an analog-to-digital converter (AD), the pin 57 and the pin 24 are respectively connected with a direct-current power supply, the pin 36, the pin 45 and the pin 46 are respectively connected with an alternating-current power supply, the pin 37 and the pin 44 are positive-direction input ends, the pin 38 and the pin 43 are reverse-direction input ends, and the pin 41 is a CML interface;
the pin 49 of the signal analysis chip is connected with a capacitor C21, a resistor R106, a resistor R107 and a capacitor C22 in series, a capacitor C22 is connected with a capacitor C23 in parallel, and one end of each of the capacitor C22 and the capacitor C23 is a first signal input end and a second signal input end respectively;
the pin 3 of the active crystal oscillator is connected with a resistor R107 and a resistor R106 in parallel and outputs 32MHZ clock frequency, the pin 2 is grounded, the pin 1 is grounded after being connected with a capacitor C24 in series, the pin 4 is connected with a resistor R108, a resistor 109 and a capacitor C25 in parallel, one ends of the capacitor C25 and the resistor R109 are grounded respectively, one end of the resistor R108 is connected with an analog-to-digital converter AD, and the capacitor C24 is connected with the resistors R108 and R109 in parallel;
the pin 50 of the signal analysis chip is connected with the capacitor C18 and the resistor R105 in parallel and then grounded, the pin 39 is connected with the capacitor C17, the capacitor C19, the resistor R180 and the resistor R170 in parallel, one end of the resistor R170 is grounded, the pin 40 is connected with the resistor R180 and the resistor R170 in parallel, the pin 42 is connected with the resistor R190 in series and then grounded, and the pin 65 is grounded;
the pin 33 of the signal analysis chip is connected with the pin J17 of the FPGA control chip, the pin 34 of the signal analysis chip is connected with the pin L19 of the FPGA control chip, the pin 35 of the signal analysis chip is connected with the pin K19 of the FPGA control chip, the pin 47 of the signal analysis chip is connected with the pin AH12 of the FPGA control chip, the pin 48 of the signal analysis chip is connected with the pin AG13 of the FPGA control chip, the pin 51 of the signal analysis chip is connected with the pin AH20 of the FPGA control chip, and the pin 52 of the signal analysis chip is connected with the pin AJ21 of the FPGA control chip;
the pin 12 of the signal analysis chip and the pin E16 of the FPGA control chip, the pin 13 of the signal analysis chip and the pin E17 of the FPGA control chip, the pin 14 of the signal analysis chip and the pin E14 of the FPGA control chip, the pin 15 of the signal analysis chip and the pin D14 of the FPGA control chip, the pin 16 of the signal analysis chip and the pin F20 of the FPGA control chip, the pin 17 of the signal analysis chip and the pin G20 of the FPGA control chip, the pin 18 of the signal analysis chip and the pin D15 of the FPGA control chip, the pin 19 of the signal analysis chip and the pin D16 of the FPGA control chip, the pin 22 of the signal analysis chip and the pin D20 of the FPGA control chip, the pin 23 of the signal analysis chip and the pin E21 of the FPGA control chip, the pin 25 of the signal analysis chip and the pin D17 of the FPGA control chip, the pin 26 of the signal analysis chip and the pin C17 of the FPGA control chip, the pin 27 of the signal analysis chip and the pin F19 of the FPGA control chip, The pin 28 of the signal analysis chip is connected with a pin E19 of the FPGA control chip;
the pin 11 of the signal analysis chip is connected with the pin G18 of the FPGA control chip, the pin 56 of the signal analysis chip is connected with the pin AJ14 of the FPGA control chip, the pin 55 of the signal analysis chip is connected with the pin AL23 of the FPGA control chip, the pin 54 of the signal analysis chip is connected with the pin AK24 of the FPGA control chip, the pin 53 of the signal analysis chip is connected with the pin AK13 of the FPGA control chip, and the pin 10 of the signal analysis chip is connected with the pin AK23 of the FPGA control chip;
the pin 9 of the signal analysis chip and the pin F16 of the FPGA control chip, the pin 8 of the signal analysis chip and the pin D24 of the FPGA control chip, the pin 7 of the signal analysis chip and the pin E23 of the FPGA control chip, the pin 6 of the signal analysis chip and the pin F14 of the FPGA control chip, the pin 5 of the signal analysis chip and the pin F15 of the FPGA control chip, the pin 4 of the signal analysis chip and the pin F24 of the FPGA control chip, the pin 3 of the signal analysis chip and the pin E24 of the FPGA control chip, the pin 2 of the signal analysis chip and the pin AH24 of the FPGA control chip, the pin 63 of the signal analysis chip and the pin AJ24 of the FPGA control chip, the pin 62 of the signal analysis chip and the pin AK12 of the FPGA control chip, the pin 61 of the signal analysis chip and the pin AJ12 of the FPGA control chip, the pin 60 of the signal analysis chip and the pin AH23 of the signal analysis chip, the pin 59 of the signal analysis chip and the pin AJ22 of the FPGA control chip, Pin 58 of the signal analysis chip is connected to pin AL13 of the FPGA control chip.
2. The wireless communication frequency hopping controller of claim 1, wherein: the FPGA control circuit comprises an FPGA control chip, a resistor R78, a field effect transistor JFET _ P, a light emitting diode, a resistor R79, a resistor R40, a resistor R54, a resistor R16, a resistor R55, a resistor R41, a resistor R56, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R102, a resistor R101, a resistor R100 and a JTAG controller; a pin T18, a pin T17, a pin U18, a pin V17, a pin V18, a pin U17 and a pin L23 of the FPGA control chip are connected in parallel and then grounded, a pin N22, a pin N23, a pin AB23 and a pin AC23 are connected in parallel and then grounded, a pin M22 is connected with a potentiometer RP, a pin M23 is grounded, and a pin M15 is connected with a resistor R78 in series and then connected with a power supply.
3. The wireless communication frequency hopping controller of claim 2, wherein: a pin N14 of the FPGA control chip is connected with a grid electrode of a field effect transistor JFET _ P, a drain electrode of the field effect transistor JFET _ P is connected with a power supply after being connected with a light-emitting diode and a resistor R79 in series, and a source electrode of the field effect transistor JFET _ P is grounded;
a pin AD21 of the FPGA control chip is connected with a resistor R40 and a resistor R54 in parallel, a pin AD22 is connected with a resistor R16 and a resistor R55 in parallel, a pin AC22 is connected with a resistor R41 and a resistor R56 in parallel, a resistor R54, a resistor R55 and a resistor R56 are connected with a power supply after being connected with the power supply in parallel, and the resistor R40, the resistor R16 and the resistor R41 are connected with the ground after being connected with the power supply in parallel;
the pin N15 of the FPGA control chip is a clock signal interface of the FPGA, and the pin AB15, the pin AC14, the pin AC15 and the pin AD14 are respectively connected with a TCK pin, a TMS pin, a TDI pin and a TDO pin of the JTAG controller.
4. The wireless communication frequency hopping controller of claim 2, wherein: a pin L21 and a resistor R1, a pin L20 and a resistor R2, a pin L15 and a resistor R3, a pin L16 and a resistor R4, a pin J22 and a resistor R5, a pin K21 and a resistor R6, a pin K16 and a resistor R7, a pin J15 and a resistor R8, a pin H22 and a resistor R9, a pin G22 and a resistor R10, a pin L10 and a resistor R10, a pin K10 and a resistor R10, a pin J10 and a resistor R10, a pin G10 and a resistor R10, a pin H10 and a resistor R10, a pin K10 and a resistor R10, a pin AE and a resistor R10, a pin a resistor R102, a pin a resistor R10 and a resistor R10, and a resistor R100 of the FPGA control chip are;
the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, the resistor R19, the resistor R102, the resistor R101 and the resistor R100 are connected in parallel and then grounded.
5. The wireless communication frequency hopping controller according to any one of claims 1 to 4, wherein: the power supply is 3.3V, the resistor R78 is 330 omega, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, the resistor R19, the resistor R79, the resistor R102, the resistor R101 and the resistor R100 are all 1K omega, and the resistor R54, the resistor R55 and the resistor R56 are all 4.7K omega.
6. The wireless communication frequency hopping controller of claim 1, wherein: the direct current power supply is 3.3V, the sizes of the resistor RJ7, the resistor RJ8, the resistor RJ9, the resistor RJ14 and the resistor RJ16 are all 4.7K omega, and the voltage of the programmable read-only memory PROM is 1.8V.
7. The wireless communication frequency hopping controller of claim 1, wherein: the voltage of the analog-to-digital converter AD is 3.3V, the direct current power supply is 1.8V, the alternating current power supply is 1.8V, the input frequencies of the first signal input end and the second signal input end are both 18.432MHZ, the sizes of the capacitor C21, the capacitor C22, the capacitor C23, the capacitor C24, the capacitor C18, the capacitor C17 and the capacitor C19 are all 0.1UF, the size of the capacitor C25 is 0.01UF, the sizes of the resistor R106 and the resistor R107 are all 100 omega, the sizes of the resistor R108, the resistor R190 and the resistor R109 are all 10K omega, the size of the resistor R105 is 39K omega, and the size of the resistor R170 is 0 omega.
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| US7444130B2 (en) * | 2005-08-19 | 2008-10-28 | Nextstep, Inc. | Tethered digital butler consumer electronic device and method |
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