CN107544343A - A kind of radio communication frequency hopping controller - Google Patents
A kind of radio communication frequency hopping controller Download PDFInfo
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- CN107544343A CN107544343A CN201710881664.7A CN201710881664A CN107544343A CN 107544343 A CN107544343 A CN 107544343A CN 201710881664 A CN201710881664 A CN 201710881664A CN 107544343 A CN107544343 A CN 107544343A
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Abstract
The invention provides a kind of radio communication frequency hopping controller, including RTC time service circuits, FPGA control circuit, storage circuit and signal evaluation circuit, the FPGA control circuit to be connected with RTC time services circuit, storage circuit and signal evaluation circuit respectively；The present invention can quickly realize the frequency hopping control of wireless communication system, and the built-up circuit technology maturity of frequency hopping controller is high, realizes that frequency-hopping communication system net synchronization capability is excellent, is a kind of invention with good application prospect.
Description
Technical field
The present invention relates to a kind of radio communication frequency hopping controller, belong to wireless communication technology field.
Background technology
Frequency hopping is exactly that " multifrequency, code selection, frequency keying " forms frequency hopping instruction to control frequency synthesizer with pseudo-code sequence,
And select frequency shift keying in multiple frequencies.Frequency hopping communications has anti-interference, anti-intercepting and capturing ability, and can accomplish that frequency spectrum resource is total to
Enjoy, so, in present modern electronic warfare, frequency hopping communications shows big advantage.
The present invention is to combine the frequency hopping index of conventional wireless communication system, a kind of wireless communication system frequency hopping of design
Controller, different software codes can be configured, realize different model wireless communication system frequency hopping control.
The content of the invention
In order to solve the above technical problems, the invention provides a kind of radio communication frequency hopping controller, the radio communication frequency hopping
Controller can configure different software codes, realize different model wireless communication system frequency hopping control
The present invention is achieved by the following technical programs.
A kind of radio communication frequency hopping controller provided by the invention, including RTC time service circuits, FPGA control circuit, storage
Circuit and signal evaluation circuit, the FPGA control circuit connect with RTC time services circuit, storage circuit and signal evaluation circuit respectively
Connect；
The RTC time services circuit is used for the time service task for completing frequency-hopping synchronization required time benchmark, is frequency hopping controller
Local time service clock；
The FPGA control circuit is used to complete frequency-hopping communication system dynamic layout and logic control task, is frequency hopping control
The message handler of device；
The storage circuit is used for the store tasks for completing control information, is the information memory cell of frequency hopping controller；
The signal evaluation circuit is used for the analysis task for completing channel quality information, is the signal acquisition of frequency hopping controller
Device.
The FPGA control circuit includes FPGA control chip, resistance R78, FET JFET_P, light emitting diode, electricity
Hinder R79, resistance R40, resistance R54, resistance R16, resistance R55, resistance R41, resistance R56, resistance R1, resistance R2, resistance R3, electricity
Hinder R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance
R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R102, resistance R101, resistance R100 and JTAG
Controller；The pin T18 of the FPGA control chip, pin T17, pin U18, pin V17, pin V18, pin U17 and draw
It is grounded, is grounded after pin N22, pin N23, pin AB23 and pin AC23 parallel connections, pin M22 is connected with electricity after pin L23 parallel connections
Position device RP, pin M23 are grounded, and power supply is connected after pin M15 series resistances R78.
The pin N14 of the FPGA control chip connects FET JFET_P grid, FET JFET_P drain electrode
Connected with light emitting diode and resistance R79 and be followed by power supply, source ground；
The pin AD21 and resistance R40 and resistance R54 of the FPGA control chip are in parallel, pin AD22 and resistance R16 and
Resistance R55 is in parallel, and pin AC22 is in parallel with resistance R41 and resistance R56, is connected after resistance R54, resistance R55 and resistance R56 parallel connections
It is grounded after power supply, resistance R40, resistance R16 and resistance R41 parallel connections；
The pin N15 of the FPGA control chip be FPGA interface clock signal, pin AB15, pin AC14, pin
AC15, pin AD14 connect TCK pin, TMS pin, TDI pins and the TDO pins of jtag controller respectively.
The pin L21 and resistance R1 of the FPGA control chip, pin L20 and resistance R2, pin L15 and resistance R3, draw
Pin L16 and resistance R4, pin J22 and resistance R5, pin K21 and resistance R6, pin K16 and resistance R7, pin J15 and resistance
R8, pin H22 and resistance R9, pin G22 and resistance R10, pin L14 and resistance R11, pin K14 and resistance R12, pin K22
With resistance R13, pin K23 and resistance R14, pin J12 and resistance R15, pin H12 and resistance R16, pin G23 and resistance
R17, pin H23 and resistance R18, pin K13 and resistance R19, pin K12 and resistance R102, pin A and resistance R101, pin
AE22 connects with resistance R100, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, electricity
Hinder R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18,
It is grounded after resistance R19, resistance R102, resistance R101 and resistance R100 parallel connections.
The power supply is 3.3V, and resistance R78 size is 330 Ω, resistance R1, resistance R2, resistance R3, resistance R4, resistance
R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance
R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R79, resistance R102, resistance R101 and resistance R100 size
It is 1K Ω, resistance R54, resistance R55, resistance R56 size are 4.7K Ω.
The RTC time services circuit includes RTC time service chips, and the pin 1 and pin 12 of RTC time service chips are grounded, drawn respectively
Pin 24 connects dc source, and the size of dc source is 3.3V；
The pin 10 of the pin 11 of the RTC time services chip and pin AF15, RTC time service chip of FPGA control chip with
The pin 9 of pin AE16, RTC time service chip of FPGA control chip and pin AE21, RTC time service chip of FPGA control chip
Pin 8 and FPGA control chip pin AD20, RTC time service chip pin 7 and FPGA control chip pin AF16,
The pin 5 and FPGA control chip of the pin 6 of RTC time service chips and pin AE17, RTC time service chip of FPGA control chip
The pin 4 of pin AE19, RTC time service chip is connected with the pin AD19 of FPGA control chip；
The pin 18 of the pin 23 of the RTC time services chip and pin H18, RTC time service chip of FPGA control chip with
The pin 17 of pin K17, RTC time service chip of FPGA control chip and pin G15, RTC time service chip of FPGA control chip
Pin 15 and FPGA control chip pin L18, RTC time service chip pin 14 and FPGA control chip pin G16,
The pin 13 of RTC time service chips is connected with the pin K18 of FPGA control chip, and the pin 19 of RTC time service chips is IRQ interfaces.
The storage circuit includes storage chip, the pin A1 of storage chip and the pin B17 of FPGA control chip, storage
The pin B1 of the chip and pin A14 of FPGA control chip, the pin C1 of storage chip and FPGA control chip pin A15,
The pin D1 of the storage chip and pin B15 of FPGA control chip, the pin D2 of the storage chip and pin of FPGA control chip
B16, the pin A2 of storage chip and FPGA control chip pin AG17, the pin C2 of storage chip and FPGA control chip
Pin AH18, the pin A3 of storage chip and FPGA control chip pin AE18, storage chip pin B3 and FPGA control
The pin AF18 of chip, the pin C3 of storage chip and FPGA control chip pin AG16, storage chip pin D3 with
The pin AH17 of FPGA control chip, the pin C4 of storage chip and FPGA control chip pin AF19, storage chip draw
The pin A5 and pin AG18 of FPGA control chip, the pin B5 of storage chip and FPGA control chip pin AG15, storage core
The pin C5 of the piece and pin AH15 of FPGA control chip, the pin D7 of storage chip and FPGA control chip pin AG20,
The pin D8 of the storage chip and pin AG21 of FPGA control chip, the pin A7 of the storage chip and pin of FPGA control chip
AH13, the pin B7 of storage chip and FPGA control chip pin D22, the pin C7 of storage chip and FPGA control chip
Pin AE23, the pin C8 of storage chip and FPGA control chip pin AE23, storage chip pin A8 and FPGA control
The pin AH14 connections of chip, the pin G1 and pin H8 of storage chip are connected with the pin AH19 of FPGA control chip；
The pin F2 of the storage chip and pin AK16 of FPGA control chip, storage chip pin E2 and FPGA control
The pin AL16 of coremaking piece, the pin G3 of storage chip and FPGA control chip pin AL21, storage chip pin E4 with
The pin AK21 of FPGA control chip, the pin E5 of storage chip and FPGA control chip pin AK17, storage chip draw
The pin G5 and pin AJ17 of FPGA control chip, the pin G6 of storage chip and FPGA control chip pin AL19, storage core
The pin H7 of the piece and pin AL20 of FPGA control chip, the pin E1 of storage chip and FPGA control chip pin AK18,
The pin E3 of the storage chip and pin AL18 of FPGA control chip, the pin F3 of the storage chip and pin of FPGA control chip
AJ19, the pin F4 of storage chip and FPGA control chip pin AK19, the pin F5 of storage chip and FPGA control chip
Pin AM15, the pin H5 and the pin AM16 of FPGA control chip of storage chip, the pin G7 and FPGA of storage chip control
The pin AP16 of coremaking piece, the pin E7 of storage chip and FPGA control chip pin AP17 connections；
The storage circuit also include resistance RJ7, resistance RJ8, resistance RJ9, resistance RJ10, resistance RJ11, resistance RJ12,
Resistance R35, resistance RJ13, resistance RJ14, resistance RJ15, resistance RJ16 and programmable read only memory PROM, storage chip
Pin F7 connects with resistance R42 is followed by the pin J20 of FPGA control chip；The resistance RJ7, resistance RJ8, resistance RJ9, resistance
RJ10, resistance RJ11 and resistance RJ12 are in parallel, and resistance RJ7, resistance RJ8, resistance RJ9 one end are connected with dc source, electricity
Resistance RJ10, resistance RJ11 and resistance RJ12 one end are grounded；The pin F8 and resistance RJ7 and resistance RJ10 of the storage chip
Parallel connection is followed by the pin H13 of FPGA control chip, and pin G8 is in parallel with resistance RJ8 and resistance RJ11 to be followed by FPGA control chip
Pin H19, pin B4 and resistance RJ9 and resistance RJ12 pin J14 in parallel for being followed by FPGA control chip；The storage chip
Pin E6 and pin F6 is grounded after being connected with resistance R35, and pin C6 and pin A4 connect with resistance RJ14 and resistance RJ16 respectively,
Pin D4 is in parallel with resistance RJ13 and resistance RJ15, resistance RJ15 one end ground connection, resistance RJ13, resistance RJ15, resistance RJ14
Dc source is followed by with resistance RJ16 parallel connections；After the pin H2 of the storage chip, pin H4, pin H6 and pin B2 parallel connections
Ground connection, pin G4, pin D5 and pin D6 parallel connections are followed by dc source, and pin A6 and pin H31 parallel connections are followed by programmable read-only
Memory PROM.
The dc source is 3.3V, and resistance RJ7, resistance RJ8, resistance RJ9, resistance RJ14 and resistance RJ16 size are equal
For 4.7K Ω, programmable read only memory PROM voltage is 1.8V.
The signal evaluation circuit includes signal analysis chip, analog-to-digital conversion device AD, electric capacity C21, resistance R106, resistance
R107, electric capacity C22, electric capacity C23, there are source crystal oscillator, electric capacity C24, electric capacity C25, resistance R108, resistance R109, electric capacity C18, resistance
R105, electric capacity C17, electric capacity C19, resistance R180, resistance R170 and resistance R190；The pin 1 of the signal analysis chip and draw
Pin 21 connects analog-to-digital conversion device AD respectively, pin 57 and draws 24 and connects dc source respectively, and pin 36, pin 45 and pin 46 divide
AC power is not connected, and pin 37 and pin 44 are positive input, and pin 38 and pin 43 are reverse input end, and pin 41 is
CML interfaces；The pin 49 of the signal analysis chip is connected with electric capacity C21, resistance R106, resistance R107 and electric capacity C22, electric capacity
C22 is in parallel with electric capacity C23, and electric capacity C22 and electric capacity C23 one end are respectively the first signal input part and secondary signal input；
It is described have source crystal oscillator pin 3 it is in parallel with resistance R107 and resistance R106, and export 32MHZ clock frequency, draw
Pin 2 is grounded, and pin 1 is grounded after being connected with electric capacity C24, and pin 4 is in parallel with resistance R108, resistance 109 and electric capacity C25, electric capacity C25
It is grounded respectively with resistance R109 one end, resistance R108 a termination analog-to-digital conversion device AD, electric capacity C24 and resistance R108, R109
It is in parallel；
It is grounded after the pin 50 of the signal analysis chip is in parallel with electric capacity C18, resistance R105, pin 39 and electric capacity C17,
Electric capacity C19, resistance R180, resistance R170 are in parallel, and resistance R170 one end ground connection, pin 40 and resistance R180, resistance R170 are simultaneously
Connection, pin 42 are grounded after being connected with resistance R190, and pin 65 is grounded；
The pin 33 of the signal analysis chip and the pin J17 of FPGA control chip, the pin 34 of signal analysis chip
The pin 35 of pin L19, signal analysis chip with FPGA control chip and the pin K19 of FPGA control chip, signal analysis
The pin 47 of chip and the pin AH12 of FPGA control chip, the pin 48 and the pin of FPGA control chip of signal analysis chip
AG13, signal analysis chip pin 51 and pin AH20, the pin 52 and FPGA of signal analysis chip of FPGA control chip
The pin AJ21 connections of control chip；
The pin 12 of the signal analysis chip and the pin E16 of FPGA control chip, the pin 13 of signal analysis chip
The pin 14 of pin E17, signal analysis chip with FPGA control chip and the pin E14 of FPGA control chip, signal analysis
The pin 15 of chip and the pin D14 of FPGA control chip, the pin 16 and the pin of FPGA control chip of signal analysis chip
F20, the pin 17 and pin G20 of FPGA control chip of signal analysis chip, the pin 18 of signal analysis chip are controlled with FPGA
The pin D15 of coremaking piece, the pin D16 of the pin 19 of signal analysis chip and FPGA control chip, signal analysis chip draw
The pin 22 and pin D20 of FPGA control chip, the pin 23 of signal analysis chip and pin E21, the signal of FPGA control chip
Pin 26 and the FPGA control chip of the pin 25 of analysis chip and the pin D17 of FPGA control chip, signal analysis chip
Pin C17, the pin F19 of pin 27 and FPGA control chip of signal analysis chip, the pin 28 of signal analysis chip with
The pin E19 connections of FPGA control chip；
The pin 11 of the signal analysis chip and the pin G18 of FPGA control chip, the pin 56 of signal analysis chip
The pin 55 of pin AJ14, signal analysis chip with FPGA control chip and the pin AL23 of FPGA control chip, signal point
Analyse the pin 54 and the pin AK24, the pin 53 of signal analysis chip and drawing for FPGA control chip of FPGA control chip of chip
Pin AK13, the pin 10 of signal analysis chip are connected with the pin AK23 of FPGA control chip；
The pin 9 of the signal analysis chip and the pin F16 of FPGA control chip, signal analysis chip pin 8 with
The pin D24 of FPGA control chip, the pin 7 of signal analysis chip and pin E23, the signal analysis chip of FPGA control chip
Pin F15, letter with FPGA control chip of the pin F14 of pin 6 and FPGA control chip, the pin 5 of signal analysis chip
Pin 3 and the FPGA control chip of the pin 4 of number analysis chip and the pin F24 of FPGA control chip, signal analysis chip
Pin E24, the pin AH24 of pin 2 and FPGA control chip of signal analysis chip, the pin 63 of signal analysis chip with
The pin AJ24 of FPGA control chip, the pin AK12 of the pin 62 of signal analysis chip and FPGA control chip, signal analysis
The pin 61 of chip and the pin AJ12 of FPGA control chip, the pin 60 and the pin of FPGA control chip of signal analysis chip
AH23, signal analysis chip pin 59 and pin AJ22, the pin 58 and FPGA of signal analysis chip of FPGA control chip
The pin AL13 connections of control chip.
The voltage of the analog-to-digital conversion device AD is 3.3V, dc source 1.8V, AC power 1.8V, and the first signal is defeated
The incoming frequency for entering end and secondary signal input is 18.432MHZ, electric capacity C21, electric capacity C22, electric capacity C23, electric capacity C24,
Electric capacity C18, electric capacity C17, electric capacity C19 size are 0.1UF, and electric capacity C25 size is 0.01UF, resistance R106, resistance
R107 size is 100 Ω, and resistance R108, resistance R190, resistance R109 size are 10K Ω, resistance R105 size
For 39K Ω, resistance R170 size is 0 Ω.
The beneficial effects of the present invention are：The frequency hopping control of wireless communication system can be quickly realized, frequency hopping controller
Built-up circuit technology maturity is high, realizes that frequency-hopping communication system net synchronization capability is excellent, is a kind of hair with good application prospect
It is bright.
Brief description of the drawings
Fig. 1 is FPGA control circuit of the present invention；
Fig. 2 is RTC time services circuit of the present invention；
Fig. 3 is storage circuit of the present invention；
Fig. 4 is signal evaluation circuit of the present invention；
Fig. 5 is enlarged drawing at Figure 1A；
Fig. 6 is enlarged drawing at Figure 1B；
Fig. 7 is the structural representation of the present invention.
Embodiment
Be described further below technical scheme, but claimed scope be not limited to it is described.
As shown in fig. 7, a kind of radio communication frequency hopping controller, including RTC time service circuits, FPGA control circuit, storage electricity
Road and signal evaluation circuit, the FPGA control circuit connect with RTC time services circuit, storage circuit and signal evaluation circuit respectively
Connect；
The RTC time services circuit is used for the time service task for completing frequency-hopping synchronization required time benchmark, is frequency hopping controller
Local time service clock；
The FPGA control circuit is used to complete frequency-hopping communication system dynamic layout and logic control task, is frequency hopping control
The message handler of device；
The storage circuit is used for the store tasks for completing control information, is the information memory cell of frequency hopping controller；
The signal evaluation circuit is used for the analysis task for completing channel quality information, is the signal acquisition of frequency hopping controller
Device.
As shown in Fig. 1, Fig. 5 and Fig. 6, FPGA control circuit includes FPGA control chip, resistance R78, FET JFET_
P, light emitting diode, resistance R79, resistance R40, resistance R54, resistance R16, resistance R55, resistance R41, resistance R56, resistance R1,
Resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance
R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R102, resistance
R101, resistance R100 and jtag controller；The pin T18 of the FPGA control chip, pin T17, pin U18, pin V17,
It is grounded after pin V18, pin U17 and pin L23 parallel connections, pin N22, pin N23, pin AB23 and pin AC23 parallel connections are followed by
Ground, pin M22 are connected with potentiometer RP, and pin M23 is grounded, and power supply is connected after pin M15 series resistances R78.
The pin N14 of the FPGA control chip connects FET JFET_P grid, FET JFET_P drain electrode
Connected with light emitting diode and resistance R79 and be followed by power supply, source ground；
The pin AD21 and resistance R40 and resistance R54 of the FPGA control chip are in parallel, pin AD22 and resistance R16 and
Resistance R55 is in parallel, and pin AC22 is in parallel with resistance R41 and resistance R56, is connected after resistance R54, resistance R55 and resistance R56 parallel connections
It is grounded after power supply, resistance R40, resistance R16 and resistance R41 parallel connections；
The pin N15 of the FPGA control chip be FPGA interface clock signal, pin AB15, pin AC14, pin
AC15, pin AD14 connect TCK pin, TMS pin, TDI pins and the TDO pins of jtag controller respectively.
The pin L21 and resistance R1 of the FPGA control chip, pin L20 and resistance R2, pin L15 and resistance R3, draw
Pin L16 and resistance R4, pin J22 and resistance R5, pin K21 and resistance R6, pin K16 and resistance R7, pin J15 and resistance
R8, pin H22 and resistance R9, pin G22 and resistance R10, pin L14 and resistance R11, pin K14 and resistance R12, pin K22
With resistance R13, pin K23 and resistance R14, pin J12 and resistance R15, pin H12 and resistance R16, pin G23 and resistance
R17, pin H23 and resistance R18, pin K13 and resistance R19, pin K12 and resistance R102, pin A and resistance R101, pin
AE22 connects with resistance R100, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, electricity
Hinder R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18,
It is grounded after resistance R19, resistance R102, resistance R101 and resistance R100 parallel connections.
The power supply is 3.3V, and resistance R78 size is 330 Ω, resistance R1, resistance R2, resistance R3, resistance R4, resistance
R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance
R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R79, resistance R102, resistance R101 and resistance R100 size
It is 1K Ω, resistance R54, resistance R55, resistance R56 size are 4.7K Ω.
As shown in Fig. 2 RTC time services circuit includes RTC time service chips, the pin 1 and pin 12 of RTC time service chips connect respectively
Ground, pin 24 connect dc source, and the size of dc source is 3.3V；
The pin 10 of the pin 11 of the RTC time services chip and pin AF15, RTC time service chip of FPGA control chip with
The pin 9 of pin AE16, RTC time service chip of FPGA control chip and pin AE21, RTC time service chip of FPGA control chip
Pin 8 and FPGA control chip pin AD20, RTC time service chip pin 7 and FPGA control chip pin AF16,
The pin 5 and FPGA control chip of the pin 6 of RTC time service chips and pin AE17, RTC time service chip of FPGA control chip
The pin 4 of pin AE19, RTC time service chip is connected with the pin AD19 of FPGA control chip；
The pin 18 of the pin 23 of the RTC time services chip and pin H18, RTC time service chip of FPGA control chip with
The pin 17 of pin K17, RTC time service chip of FPGA control chip and pin G15, RTC time service chip of FPGA control chip
Pin 15 and FPGA control chip pin L18, RTC time service chip pin 14 and FPGA control chip pin G16,
The pin 13 of RTC time service chips is connected with the pin K18 of FPGA control chip, and the pin 19 of RTC time service chips is IRQ interfaces,
That is interrupt requests, the effect of IRQ interfaces is exactly the action that hardware interrupt request is performed in computer used.
As shown in figure 3, storage circuit includes storage chip, the pin A1 of storage chip and the pin of FPGA control chip
B17, the pin B1 of storage chip and FPGA control chip pin A14, the pin C1 of storage chip and FPGA control chip
Pin A15, the pin D1 of storage chip and FPGA control chip pin B15, pin D2 and FPGA the control core of storage chip
The pin B16 of piece, the pin A2 of storage chip and FPGA control chip pin AG17, storage chip pin C2 and FPGA control
The pin AH18 of coremaking piece, the pin A3 of storage chip and FPGA control chip pin AE18, storage chip pin B3 with
The pin AF18 of FPGA control chip, the pin C3 of storage chip and FPGA control chip pin AG16, storage chip draw
The pin D3 and pin AH17 of FPGA control chip, the pin C4 of storage chip and FPGA control chip pin AF19, storage core
The pin A5 of the piece and pin AG18 of FPGA control chip, the pin B5 of storage chip and FPGA control chip pin AG15,
The pin C5 of the storage chip and pin AH15 of FPGA control chip, the pin D7 of the storage chip and pin of FPGA control chip
AG20, the pin D8 of storage chip and FPGA control chip pin AG21, the pin A7 of storage chip and FPGA control chip
Pin AH13, the pin B7 and the pin D22 of FPGA control chip of storage chip, the pin C7 and FPGA of storage chip control
The pin AE23 of chip, the pin C8 of storage chip and FPGA control chip pin AE23, storage chip pin A8 with
The pin AH14 connections of FPGA control chip, the pin AH19 of the pin G1 and pin H8 of storage chip with FPGA control chip
Connection；
The pin F2 of the storage chip and pin AK16 of FPGA control chip, storage chip pin E2 and FPGA control
The pin AL16 of coremaking piece, the pin G3 of storage chip and FPGA control chip pin AL21, storage chip pin E4 with
The pin AK21 of FPGA control chip, the pin E5 of storage chip and FPGA control chip pin AK17, storage chip draw
The pin G5 and pin AJ17 of FPGA control chip, the pin G6 of storage chip and FPGA control chip pin AL19, storage core
The pin H7 of the piece and pin AL20 of FPGA control chip, the pin E1 of storage chip and FPGA control chip pin AK18,
The pin E3 of the storage chip and pin AL18 of FPGA control chip, the pin F3 of the storage chip and pin of FPGA control chip
AJ19, the pin F4 of storage chip and FPGA control chip pin AK19, the pin F5 of storage chip and FPGA control chip
Pin AM15, the pin H5 and the pin AM16 of FPGA control chip of storage chip, the pin G7 and FPGA of storage chip control
The pin AP16 of coremaking piece, the pin E7 of storage chip and FPGA control chip pin AP17 connections；
The storage circuit also include resistance RJ7, resistance RJ8, resistance RJ9, resistance RJ10, resistance RJ11, resistance RJ12,
Resistance R35, resistance RJ13, resistance RJ14, resistance RJ15, resistance RJ16 and programmable read only memory PROM, storage chip
Pin F7 connects with resistance R42 is followed by the pin J20 of FPGA control chip；The resistance RJ7, resistance RJ8, resistance RJ9, resistance
RJ10, resistance RJ11 and resistance RJ12 are in parallel, and resistance RJ7, resistance RJ8, resistance RJ9 one end are connected with dc source, electricity
Resistance RJ10, resistance RJ11 and resistance RJ12 one end are grounded；The pin F8 and resistance RJ7 and resistance RJ10 of the storage chip
Parallel connection is followed by the pin H13 of FPGA control chip, and pin G8 is in parallel with resistance RJ8 and resistance RJ11 to be followed by FPGA control chip
Pin H19, pin B4 and resistance RJ9 and resistance RJ12 pin J14 in parallel for being followed by FPGA control chip；The storage chip
Pin E6 and pin F6 is grounded after being connected with resistance R35, and pin C6 and pin A4 connect with resistance RJ14 and resistance RJ16 respectively,
Pin D4 is in parallel with resistance RJ13 and resistance RJ15, resistance RJ15 one end ground connection, resistance RJ13, resistance RJ15, resistance RJ14
Dc source is followed by with resistance RJ16 parallel connections；After the pin H2 of the storage chip, pin H4, pin H6 and pin B2 parallel connections
Ground connection, pin G4, pin D5 and pin D6 parallel connections are followed by dc source, and pin A6 and pin H31 parallel connections are followed by programmable read-only
Memory PROM.
The dc source is 3.3V, and resistance RJ7, resistance RJ8, resistance RJ9, resistance RJ14 and resistance RJ16 size are equal
For 4.7K Ω, programmable read only memory PROM voltage is 1.8V.
As shown in figure 4, signal evaluation circuit include signal analysis chip, analog-to-digital conversion device AD, electric capacity C21, resistance R106,
Resistance R107, electric capacity C22, electric capacity C23, have source crystal oscillator, electric capacity C24, electric capacity C25, resistance R108, resistance R109, electric capacity C18,
Resistance R105, electric capacity C17, electric capacity C19, resistance R180, resistance R170 and resistance R190；The pin 1 of the signal analysis chip
Analog-to-digital conversion device AD is connected respectively with pin 21, pin 57 and is drawn 24 and is connected dc source, pin 36, pin 45 and pin respectively
46 connect AC power respectively, and pin 37 and pin 44 are positive input, and pin 38 and pin 43 are reverse input end, pin
41 be CML interfaces, and CML interfaces are CMLs, is driven mainly by electric current, it may be said that CML interfaces are all high-speed datas
Simplest one kind in interface shape, its input and output match, direct during use so as to reduce peripheral components
Can is connected, need not substantially be matched outside IC, it is simpler that this feature designs single plate hardware, and veneer seems more
Succinctly, the amplitude of oscillation of CML interfaces is smaller, and power dissipation ratio is relatively low；The pin 49 of the signal analysis chip and electric capacity C21, resistance R106,
Resistance R107 and electric capacity C22 series connection, electric capacity C22 is in parallel with electric capacity C23, and electric capacity C22 and electric capacity C23 one end are respectively the first letter
Number input and secondary signal input；
It is described have source crystal oscillator pin 3 it is in parallel with resistance R107 and resistance R106, and export 32MHZ clock frequency, draw
Pin 2 is grounded, and pin 1 is grounded after being connected with electric capacity C24, and pin 4 is in parallel with resistance R108, resistance 109 and electric capacity C25, electric capacity C25
It is grounded respectively with resistance R109 one end, resistance R108 a termination analog-to-digital conversion device AD, electric capacity C24 and resistance R108, R109
Parallel connection, wherein, there is the internal oscillator that source crystal oscillator does not need CPU, signal quality is good, more stable, and connected mode is relative
Simply (power filter is mainly carried out, the PI type filter networks formed usually using an electric capacity and inductance, output end is with one
The resistance trap signal of small resistance), it is not necessary to complicated configuration circuit.；
It is grounded after the pin 50 of the signal analysis chip is in parallel with electric capacity C18, resistance R105, pin 39 and electric capacity C17,
Electric capacity C19, resistance R180, resistance R170 are in parallel, and resistance R170 one end ground connection, pin 40 and resistance R180, resistance R170 are simultaneously
Connection, pin 42 are grounded after being connected with resistance R190, and pin 65 is grounded；
The pin 33 of the signal analysis chip and the pin J17 of FPGA control chip, the pin 34 of signal analysis chip
The pin 35 of pin L19, signal analysis chip with FPGA control chip and the pin K19 of FPGA control chip, signal analysis
The pin 47 of chip and the pin AH12 of FPGA control chip, the pin 48 and the pin of FPGA control chip of signal analysis chip
AG13, signal analysis chip pin 51 and pin AH20, the pin 52 and FPGA of signal analysis chip of FPGA control chip
The pin AJ21 connections of control chip；
The pin 12 of the signal analysis chip and the pin E16 of FPGA control chip, the pin 13 of signal analysis chip
The pin 14 of pin E17, signal analysis chip with FPGA control chip and the pin E14 of FPGA control chip, signal analysis
The pin 15 of chip and the pin D14 of FPGA control chip, the pin 16 and the pin of FPGA control chip of signal analysis chip
F20, the pin 17 and pin G20 of FPGA control chip of signal analysis chip, the pin 18 of signal analysis chip are controlled with FPGA
The pin D15 of coremaking piece, the pin D16 of the pin 19 of signal analysis chip and FPGA control chip, signal analysis chip draw
The pin 22 and pin D20 of FPGA control chip, the pin 23 of signal analysis chip and pin E21, the signal of FPGA control chip
Pin 26 and the FPGA control chip of the pin 25 of analysis chip and the pin D17 of FPGA control chip, signal analysis chip
Pin C17, the pin F19 of pin 27 and FPGA control chip of signal analysis chip, the pin 28 of signal analysis chip with
The pin E19 connections of FPGA control chip；
The pin 11 of the signal analysis chip and the pin G18 of FPGA control chip, the pin 56 of signal analysis chip
The pin 55 of pin AJ14, signal analysis chip with FPGA control chip and the pin AL23 of FPGA control chip, signal point
Analyse the pin 54 and the pin AK24, the pin 53 of signal analysis chip and drawing for FPGA control chip of FPGA control chip of chip
Pin AK13, the pin 10 of signal analysis chip are connected with the pin AK23 of FPGA control chip；
The pin 9 of the signal analysis chip and the pin F16 of FPGA control chip, signal analysis chip pin 8 with
The pin D24 of FPGA control chip, the pin 7 of signal analysis chip and pin E23, the signal analysis chip of FPGA control chip
Pin F15, letter with FPGA control chip of the pin F14 of pin 6 and FPGA control chip, the pin 5 of signal analysis chip
Pin 3 and the FPGA control chip of the pin 4 of number analysis chip and the pin F24 of FPGA control chip, signal analysis chip
Pin E24, the pin AH24 of pin 2 and FPGA control chip of signal analysis chip, the pin 63 of signal analysis chip with
The pin AJ24 of FPGA control chip, the pin AK12 of the pin 62 of signal analysis chip and FPGA control chip, signal analysis
The pin 61 of chip and the pin AJ12 of FPGA control chip, the pin 60 and the pin of FPGA control chip of signal analysis chip
AH23, signal analysis chip pin 59 and pin AJ22, the pin 58 and FPGA of signal analysis chip of FPGA control chip
The pin AL13 connections of control chip.
The voltage of the analog-to-digital conversion device AD is 3.3V, dc source 1.8V, AC power 1.8V, and the first signal is defeated
The incoming frequency for entering end and secondary signal input is 18.432MHZ, electric capacity C21, electric capacity C22, electric capacity C23, electric capacity C24,
Electric capacity C18, electric capacity C17, electric capacity C19 size are 0.1UF, and electric capacity C25 size is 0.01UF, resistance R106, resistance
R107 size is 100 Ω, and resistance R108, resistance R190, resistance R109 size are 10K Ω, resistance R105 size
For 39K Ω, resistance R170 size is 0 Ω.
In summary, in the present invention after electricity, local clock is transferred to by Fig. 2 RTC time services circuit by Fig. 1 FPGA controls
Circuit, Fig. 1 FPGA control circuits read system initial configuration state in Fig. 3 storage circuits, are provided with reference to Fig. 2 RTC time services circuit
Reference clock, by control logic and algorithm, realize the frequency-hopping synchronization of wireless communication system, establish the logical of wireless communication system
Believe link, wherein, Fig. 4 signal evaluation circuits are acquired to current channel quality information, and give figure the information transmission of collection
1FPGA control circuits, Fig. 1 FPGA control circuits are calculated by FFT, are analyzed present channel quality, according to analysis result, are realized nothing
The AFH of line communication system.
Claims (10)
- A kind of 1. radio communication frequency hopping controller, it is characterised in that：Including RTC time service circuits, FPGA control circuit, storage circuit And signal evaluation circuit, the FPGA control circuit are connected with RTC time services circuit, storage circuit and signal evaluation circuit respectively；The RTC time services circuit is used for the time service task for completing frequency-hopping synchronization required time benchmark, is the local of frequency hopping controller Time service clock；The FPGA control circuit is used to complete frequency-hopping communication system dynamic layout and logic control task, is frequency hopping controller Message handler；The storage circuit is used for the store tasks for completing control information, is the information memory cell of frequency hopping controller；The signal evaluation circuit is used for the analysis task for completing channel quality information, is the signal picker of frequency hopping controller.
- 2. radio communication frequency hopping controller as claimed in claim 1, it is characterised in that：The FPGA control circuit includes FPGA Control chip, resistance R78, FET JFET_P, light emitting diode, resistance R79, resistance R40, resistance R54, resistance R16, electricity Hinder R55, resistance R41, resistance R56, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, electricity Hinder R18, resistance R19, resistance R102, resistance R101, resistance R100 and jtag controller；The pin of the FPGA control chip It is grounded after T18, pin T17, pin U18, pin V17, pin V18, pin U17 and pin L23 parallel connections, pin N22, pin It is grounded after N23, pin AB23 and pin AC23 parallel connections, pin M22 is connected with potentiometer RP, pin M23 ground connection, pin M15 strings Power supply is connected after connection resistance R78.
- 3. radio communication frequency hopping controller as claimed in claim 2, it is characterised in that：The pin of the FPGA control chip N14 connects FET JFET_P grid, and FET JFET_P drain electrode is connected with light emitting diode and resistance R79 and is followed by electricity Source, source ground；The pin AD21 and resistance R40 and resistance R54 of the FPGA control chip are in parallel, pin AD22 and resistance R16 and resistance R55 is in parallel, and pin AC22 is in parallel with resistance R41 and resistance R56, and electricity is connected after resistance R54, resistance R55 and resistance R56 parallel connections It is grounded after source, resistance R40, resistance R16 and resistance R41 parallel connections；The pin N15 of the FPGA control chip be FPGA interface clock signal, pin AB15, pin AC14, pin AC15, Pin AD14 connects TCK pin, TMS pin, TDI pins and the TDO pins of jtag controller respectively.
- 4. radio communication frequency hopping controller as claimed in claim 2, it is characterised in that：The pin of the FPGA control chip L21 and resistance R1, pin L20 and resistance R2, pin L15 and resistance R3, pin L16 and resistance R4, pin J22 and resistance R5, Pin K21 and resistance R6, pin K16 and resistance R7, pin J15 and resistance R8, pin H22 and resistance R9, pin G22 and resistance R10, pin L14 and resistance R11, pin K14 and resistance R12, pin K22 and resistance R13, pin K23 and resistance R14, pin J12 and resistance R15, pin H12 and resistance R16, pin G23 and resistance R17, pin H23 and resistance R18, pin K13 and resistance R19, pin K12 connect with resistance R102, pin A with resistance R101, pin AE22 with resistance R100；The resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, It is grounded after resistance R102, resistance R101 and resistance R100 parallel connections.
- 5. the radio communication frequency hopping controller as described in any one in Claims 1 to 4, it is characterised in that：The power supply is 3.3V, resistance R78 size are 330 Ω, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electricity Hinder R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, Resistance R18, resistance R19, resistance R79, resistance R102, resistance R101 and resistance R100 size are 1K Ω, resistance R54, electricity Hinder R55, resistance R56 size is 4.7K Ω.
- 6. radio communication frequency hopping controller as claimed in claim 1, it is characterised in that：The RTC time services circuit is awarded including RTC When chip, the pin 1 and pin 12 of RTC time service chips be grounded respectively, and pin 24 connects dc source, and the size of dc source is 3.3V；The pin 10 and FPGA of the pin 11 of the RTC time services chip and pin AF15, RTC time service chip of FPGA control chip The pin 9 of pin AE16, RTC time service chip of control chip and drawing for pin AE21, RTC time service chip of FPGA control chip The pin 7 and pin AF16, RTC of FPGA control chip of pin 8 and pin AD20, RTC time service chip of FPGA control chip are awarded When chip pin 6 and FPGA control chip pin AE17, RTC time service chip pin 5 and the pin of FPGA control chip The pin 4 of AE19, RTC time service chip is connected with the pin AD19 of FPGA control chip；The pin 18 and FPGA of the pin 23 of the RTC time services chip and pin H18, RTC time service chip of FPGA control chip The pin 17 of pin K17, RTC time service chip of control chip and drawing for pin G15, RTC time service chip of FPGA control chip The pin 14 and pin G16, RTC of FPGA control chip of pin 15 and pin L18, RTC time service chip of FPGA control chip are awarded When the pin 13 of chip be connected with the pin K18 of FPGA control chip, the pin 19 of RTC time service chips is IRQ interfaces.
- 7. radio communication frequency hopping controller as claimed in claim 1, it is characterised in that：The storage circuit includes storage core Piece, the pin A1 of the storage chip and pin B17 of FPGA control chip, the pin B1 of storage chip and drawing for FPGA control chip Pin A14, the pin C1 of storage chip and FPGA control chip pin A15, the pin D1 of storage chip and FPGA control chip Pin B15, the pin D2 and the pin B16 of FPGA control chip of storage chip, the pin A2 and FPGA of storage chip control The pin AG17 of chip, the pin C2 of storage chip and FPGA control chip pin AH18, storage chip pin A3 with The pin AE18 of FPGA control chip, the pin B3 of storage chip and FPGA control chip pin AF18, storage chip draw The pin C3 and pin AG16 of FPGA control chip, the pin D3 of storage chip and FPGA control chip pin AH17, storage core The pin C4 of the piece and pin AF19 of FPGA control chip, the pin A5 of storage chip and FPGA control chip pin AG18, The pin B5 of the storage chip and pin AG15 of FPGA control chip, the pin C5 of the storage chip and pin of FPGA control chip AH15, the pin D7 of storage chip and FPGA control chip pin AG20, the pin D8 of storage chip and FPGA control chip Pin AG21, the pin A7 and the pin AH13 of FPGA control chip of storage chip, the pin B7 and FPGA of storage chip control The pin D22 of coremaking piece, the pin C7 of storage chip and FPGA control chip pin AE23, storage chip pin C8 with The pin AE23 of FPGA control chip, the pin A8 of storage chip and FPGA control chip pin AH14 connections, storage chip Pin G1 and pin H8 be connected with the pin AH19 of FPGA control chip；The pin F2 of the storage chip and pin AK16 of FPGA control chip, storage chip pin E2 and FPGA control core The pin AL16 of piece, the pin G3 of storage chip and FPGA control chip pin AL21, the pin E4 and FPGA of storage chip The pin AK21 of control chip, the pin E5 of storage chip and FPGA control chip pin AK17, the pin G5 of storage chip The pin G6 of pin AJ17, storage chip with the FPGA control chip and pin AL19 of FPGA control chip, storage chip The pin H7 and pin AL20 of FPGA control chip, the pin E1 of storage chip and FPGA control chip pin AK18, storage The pin E3 of the chip and pin AL18 of FPGA control chip, the pin F3 of the storage chip and pin of FPGA control chip AJ19, the pin F4 of storage chip and FPGA control chip pin AK19, the pin F5 of storage chip and FPGA control chip Pin AM15, the pin H5 and the pin AM16 of FPGA control chip of storage chip, the pin G7 and FPGA of storage chip control The pin AP16 of coremaking piece, the pin E7 of storage chip and FPGA control chip pin AP17 connections；The storage circuit also includes resistance RJ7, resistance RJ8, resistance RJ9, resistance RJ10, resistance RJ11, resistance RJ12, resistance R35, resistance RJ13, resistance RJ14, resistance RJ15, resistance RJ16 and programmable read only memory PROM, the pin of storage chip F7 connects with resistance R42 is followed by the pin J20 of FPGA control chip；The resistance RJ7, resistance RJ8, resistance RJ9, resistance RJ10, resistance RJ11 and resistance RJ12 are in parallel, resistance RJ7, resistance RJ8, resistance RJ9 one end are connected with dc source, and resistance RJ10, resistance RJ11 and resistance RJ12 one end are grounded；The pin F8 and resistance RJ7 and resistance RJ10 of the storage chip pin H13 in parallel for being followed by FPGA control chip, pin G8 the pin H19 that is followed by FPGA control chip in parallel with resistance RJ8 and resistance RJ11, pin B4 and resistance RJ9 and resistance RJ12 Parallel connection is followed by the pin J14 of FPGA control chip；The pin E6 and pin F6 of the storage chip are grounded after being connected with resistance R35, pin C6 and pin A4 respectively with resistance RJ14 and resistance RJ16 series connection, pin D4 is in parallel with resistance RJ13 and resistance RJ15, resistance RJ15 one end ground connection, resistance RJ13, resistance RJ15, resistance RJ14 and resistance RJ16 parallel connections are followed by dc source；It is grounded, pin G4, pin D5 and draws after the pin H2 of the storage chip, pin H4, pin H6 and pin B2 are in parallel Pin D6 parallel connections are followed by dc source, and pin A6 and pin H31 parallel connections are followed by programmable read only memory PROM.
- 8. radio communication frequency hopping controller as claimed in claim 7, it is characterised in that：The dc source is 3.3V, resistance RJ7, resistance RJ8, resistance RJ9, resistance RJ14 and resistance RJ16 size are 4.7K Ω, programmable read only memory PROM's Voltage is 1.8V.
- 9. radio communication frequency hopping controller as claimed in claim 1, it is characterised in that：The signal evaluation circuit includes signal Analysis chip, analog-to-digital conversion device AD, electric capacity C21, resistance R106, resistance R107, electric capacity C22, electric capacity C23, there are source crystal oscillator, electric capacity C24, electric capacity C25, resistance R108, resistance R109, electric capacity C18, resistance R105, electric capacity C17, electric capacity C19, resistance R180, resistance R170 and resistance R190；The pin 1 and pin 21 of the signal analysis chip connect analog-to-digital conversion device AD respectively, pin 57 and draw 24 connect dc source respectively, and pin 36, pin 45 and pin 46 connect AC power, pin 37 and pin 44 as forward direction respectively Input, pin 38 and pin 43 are reverse input end, and pin 41 is CML interfaces；The pin 49 of the signal analysis chip is connected with electric capacity C21, resistance R106, resistance R107 and electric capacity C22, electric capacity C22 In parallel with electric capacity C23, electric capacity C22 and electric capacity C23 one end are respectively the first signal input part and secondary signal input；It is described have source crystal oscillator pin 3 it is in parallel with resistance R107 and resistance R106, and export 32MHZ clock frequency, pin 2 connects Ground, pin 1 are grounded after being connected with electric capacity C24, and pin 4 is in parallel with resistance R108, resistance 109 and electric capacity C25, electric capacity C25 and electricity Resistance R109 one end is grounded respectively, and resistance R108 termination analog-to-digital conversion a device AD, electric capacity C24 is in parallel with resistance R108, R109；It is grounded after the pin 50 of the signal analysis chip is in parallel with electric capacity C18, resistance R105, pin 39 and electric capacity C17, electric capacity C19, resistance R180, resistance R170 are in parallel, and resistance R170 one end ground connection, pin 40 is in parallel with resistance R180, resistance R170, draws Pin 42 is grounded after being connected with resistance R190, and pin 65 is grounded；The pin 33 of the signal analysis chip and the pin J17 of FPGA control chip, signal analysis chip pin 34 with The pin L19 of FPGA control chip, the pin 35 of signal analysis chip and pin K19, the signal analysis core of FPGA control chip The pin 47 of piece and the pin AH12 of FPGA control chip, the pin 48 and the pin of FPGA control chip of signal analysis chip AG13, signal analysis chip pin 51 and pin AH20, the pin 52 and FPGA of signal analysis chip of FPGA control chip The pin AJ21 connections of control chip；The pin 12 of the signal analysis chip and the pin E16 of FPGA control chip, signal analysis chip pin 13 with The pin E17 of FPGA control chip, the pin 14 of signal analysis chip and pin E14, the signal analysis core of FPGA control chip The pin 15 of piece and the pin D14 of FPGA control chip, the pin 16 and the pin of FPGA control chip of signal analysis chip F20, the pin 17 and pin G20 of FPGA control chip of signal analysis chip, the pin 18 of signal analysis chip are controlled with FPGA The pin D15 of coremaking piece, the pin D16 of the pin 19 of signal analysis chip and FPGA control chip, signal analysis chip draw The pin 22 and pin D20 of FPGA control chip, the pin 23 of signal analysis chip and pin E21, the signal of FPGA control chip Pin 26 and the FPGA control chip of the pin 25 of analysis chip and the pin D17 of FPGA control chip, signal analysis chip Pin C17, the pin F19 of pin 27 and FPGA control chip of signal analysis chip, the pin 28 of signal analysis chip with The pin E19 connections of FPGA control chip；The pin 11 of the signal analysis chip and the pin G18 of FPGA control chip, signal analysis chip pin 56 with The pin AJ14 of FPGA control chip, the pin AL23 of the pin 55 of signal analysis chip and FPGA control chip, signal analysis The pin 54 of chip and the pin AK24 of FPGA control chip, the pin 53 and the pin of FPGA control chip of signal analysis chip AK13, the pin 10 of signal analysis chip are connected with the pin AK23 of FPGA control chip；The pin 9 of the signal analysis chip and the pin F16 of FPGA control chip, the pin 8 and FPGA of signal analysis chip The pin D24 of control chip, the pin E23 of the pin 7 of signal analysis chip and FPGA control chip, signal analysis chip draw Pin F15, the signal point of the pin 6 and pin F14 of FPGA control chip, the pin 5 of signal analysis chip with FPGA control chip Analyse the pin 4 of chip and the pin F24 of FPGA control chip, the pin 3 and the pin of FPGA control chip of signal analysis chip E24, the pin 2 and pin AH24 of FPGA control chip of signal analysis chip, the pin 63 of signal analysis chip are controlled with FPGA The pin AJ24 of coremaking piece, the pin AK12 of the pin 62 of signal analysis chip and FPGA control chip, signal analysis chip The pin AJ12 of pin 61 and FPGA control chip, the pin 60 of signal analysis chip and FPGA control chip pin AH23, The pin 59 of signal analysis chip and the pin AJ22 of FPGA control chip, the pin 58 and FPGA control cores of signal analysis chip The pin AL13 connections of piece.
- 10. radio communication frequency hopping controller as claimed in claim 9, it is characterised in that：The voltage of the analog-to-digital conversion device AD For 3.3V, dc source 1.8V, AC power 1.8V, the incoming frequency of the first signal input part and secondary signal input It is 18.432MHZ, electric capacity C21, electric capacity C22, electric capacity C23, electric capacity C24, electric capacity C18, electric capacity C17, electric capacity C19 size are equal For 0.1UF, electric capacity C25 size is 0.01UF, and resistance R106, resistance R107 size are 100 Ω, resistance R108, resistance R190, resistance R109 size are 10K Ω, and resistance R105 size is 39K Ω, and resistance R170 size is 0 Ω.
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