CN107543985B - Multi-section battery core protection board disconnection detection circuit - Google Patents

Multi-section battery core protection board disconnection detection circuit Download PDF

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CN107543985B
CN107543985B CN201710526424.5A CN201710526424A CN107543985B CN 107543985 B CN107543985 B CN 107543985B CN 201710526424 A CN201710526424 A CN 201710526424A CN 107543985 B CN107543985 B CN 107543985B
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voltage
signal
battery
gate
source
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CN107543985A (en
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李演明
张豪
陈忠会
刘雨鑫
周罡
曹灿
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Xi'an Zhonghexin Microelectronics Co ltd
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Xi'an Huatai Semiconductor Technology Co Ltd
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Abstract

The invention discloses a circuit for detecting disconnection of a multi-section battery cell protection board, which can remove highest BAT (battery charge) by multiplexing an overvoltage comparatornOutside BAT1～BATn‑1The battery is respectively used for detecting disconnection and overvoltage, and the circuit mainly comprises a pull-up current source I1～In‑1And an overvoltage comparator OV1～OVn‑1And a voltage dividing resistor R01～R0n‑1The structure can simultaneously carry out overvoltage and disconnection detection on the n-1 batteries. A narrow pulse signal XCLK with a certain period generated by a timing and control unitHVSwitch SW for controlling overvoltage and disconnection detection of each battery1～SWn‑1(ii) a The battery disconnection detection circuit solves the problems that the traditional battery protection circuit cannot detect battery disconnection and overvoltage at the same time and cannot detect disconnection under the condition of undervoltage of the battery; narrow pulse signal XCLK is usedHVThe signal used as the disconnection detection switch greatly reduces the power consumption of the circuit; and only the pull-up current is utilized, and the overvoltage comparator is multiplexed, so that the area of the circuit is effectively reduced.

Description

Multi-section battery core protection board disconnection detection circuit
Technical Field
The invention belongs to the technical field of battery protection, and relates to a circuit for detecting disconnection of a multi-section battery core protection board.
Background
With the development of various intelligent devices and new energy power vehicles, the lithium power battery is developed and applied very mature, and a plurality of lithium batteries are connected in series to form battery packs with different voltages and different capacities so as to supply power for high-power consumption electric equipment. For the safety of the battery pack, it is common to provide a lithium battery protection chip including a disconnection and overvoltage protection circuit to ensure that each battery closes a charging tube or a discharge tube in case of disconnection or overvoltage, thereby prolonging the service life of the battery.
Taking a battery pack consisting of n batteries as an example for analysis, when the disconnection detection module works normally, the voltage difference of each battery is not large, so that the battery voltage VC detected at the nth batterynApproximately equal to n times the voltage of each cell. When the jth battery is disconnected, the voltage VC of the battery isjWill be pulled up to the voltage VC of the last batteryj+1And when detecting, the battery voltage VC at the momentjAnd the data is transmitted to a comparator so as to detect the disconnection abnormity. And VCjThe battery is pulled high, and the traditional circuit can also misjudge the disconnection of the battery as the overvoltage of the battery sometimes; and the traditional circuit is realized by a single battery disconnection detection module, and the battery disconnection detection module uses more comparators, so that the chip area is large and the power consumption is large.
Disclosure of Invention
Aiming at the defects of the existing battery disconnection detection circuit, the invention provides a multiplexing overvoltage comparator, and solves the problems of large area and large power consumption of the existing circuit only by using a pull-up mode; the voltage of each battery is respectively obtained different voltage division ratios through different voltage division points, and the voltage of each battery is different when the disconnection and the overvoltage occur, so that the voltage division of the battery and the reference voltage can accurately judge whether the abnormal state of the battery is disconnection or overvoltage through a comparator; and the mode can ensure that the disconnection detection of the batteries of other sections is not influenced by the undervoltage condition of the batteries.
In order to achieve the purpose, the invention adopts the following technical scheme to solve the problem: a circuit for detecting disconnection of a multi-section battery core protection board comprises a disconnection detection unit A, a time sequence and control unit B and a plurality of batteries BAT connected in series1～BATnN is a positive integer greater than or equal to 2;
battery BATiThrough a resistor R connected in seriesiAnd a capacitor CiThe RC filter circuit is grounded, and the battery BAT1The negative electrode is grounded, i is more than or equal to 1 and less than or equal to n; battery BATjVoltage VC of the batteryjBy connecting a voltage-dividing resistor R0jTo obtain a partial pressure VFBjInput comparator AjPositive input terminal of (1), comparator AjIs connected with a reference voltage VREFjJ is more than or equal to 1 and less than or equal to n-1, and the resistance R01～R0(n-1)Are connected in series in sequence and are provided with a resistor R01One end is grounded;
highest battery BATnThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage VDDHVRespectively connected with a DC current source I1～In-1Is connected to a DC current source IjIs passed through a switch SWjCorresponding resistance R0jIs connected to one end of a switch SWjThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A10Generated narrow pulse signal XCLKHVControl in XCLKHVWhen the falling edge arrives, the switch SW in the detection circuitjClosing and starting the disconnection detection, wherein j is more than or equal to 1 and less than or equal to n-1;
comparator AjIs connected to the logic or gate a11J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A11And D flip-flop A13Input terminal D and counter A12Is connected to the input of D flip-flop A13The input end CLK is formed by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B passing through a time delay unit A14The generated signal controls, D flip-flop A13The output signal BLD of the output terminal Q is respectively connected to the input terminals of the logic OR gate 101 and the second level shift unit 104, the output signal of the second level shift unit 104 passes through the second inverter 105 to output the signal DHC to control the NMOS transistor Q2, and the other input terminal of the logic OR gate 101 is connected to the counter A12The output end of the logic or gate 101 outputs a signal CHC through the first level shifting unit 102 and the first inverter 103 to control the NMOS transistor Q1。
Battery disconnectionThe detection unit A comprises a high-voltage PMOS tube Ma0～Ma(n-1)Voltage V ofDDHVAnd a high voltage PMOS transistor Ma0～Ma(n-1)Is connected with a source electrode of the high-voltage PMOS transistor Ma0And a high voltage PMOS transistor Ma1～Ma(n-1)Respectively form a current mirror and a high-voltage PMOS tube Ma0Is a source of a current mirror and is composed of a direct current source I0Providing a mirror current, wherein the high voltage PMOS transistor Ma0And a high voltage PMOS transistor MajThe current mirror is used as a DC current source IjJ is more than or equal to 1 and less than or equal to n-1; high-voltage PMOS (P-channel Metal oxide semiconductor) tube Ma0Drain electrode of (1) and DC current source I0Is connected to a DC current source I0The output end of the transformer is grounded;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube MbjSource electrode and high voltage PMOS transistor MajIs connected to the drain of the transistor, a narrow pulse signal XCLKHVControl high-voltage PMOS tube MbjThe grid of (1), wherein the high voltage PMOS tube MbjAs a switch SWjHigh voltage PMOS transistor MbjDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjOne end of and a high voltage NMOS tube McjIs connected to the drain of the resistor RbjAnother terminal of (1) and a resistor RcjOne end of and a high voltage NMOS tube MdjIs connected to the drain of the resistor RcjIs connected to a voltage source V at the other endjThe negative electrode of (1); high-voltage NMOS tube McjIs formed by XCLKHVA signal control, the source of which is connected to the positive input end of the comparator Aj; high-voltage NMOS tube MdjGate of from CLKHVControl of signal, source and comparator AjThe positive input end of the power supply is connected; comparator AjThe reverse input end of the voltage source is connected with a voltage source VjThe provided reference voltage VREFjThe output end is connected with a logic OR gate A11Wherein j is more than or equal to 1 and less than or equal to n-1; voltage source V1The negative electrode of (2) is grounded.
The battery disconnection detecting unit A includes a resistor R1～Rn-1Voltage V ofDDHVAnd a resistor RjIs connected to one end of a resistor RjAs a direct current source IjThe other end of the resistor Rj is connected toIs connected to a high-voltage PMOS tube MajWherein, the high voltage PMOS transistor MajAs a switch SWjFrom a narrow pulse signal XCLKHVControl high-voltage PMOS tube MajGrid of (1), high voltage PMOS transistor MajDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjOne end of and a high voltage NMOS tube McjIs connected to the drain of the resistor RbjAnother terminal of (1) and a resistor RcjOne end of and a high voltage NMOS tube MdjIs connected to the drain of the resistor RcjIs connected to a voltage source V at the other endjThe negative electrode of (1); high-voltage NMOS tube McjIs formed by XCLKHVSignal control with source connected to comparator AjThe positive input terminal of (1); high-voltage NMOS tube MdjGate of from CLKHVControl of signal, source and comparator AjThe positive input end of the power supply is connected; comparator AjThe reverse input end of the voltage source is connected with a voltage source VjThe provided reference voltage VREFjThe output end is connected with a logic OR gate A11Wherein j is more than or equal to 1 and less than or equal to n-1; voltage source V1The negative electrode of (2) is grounded.
The cell disconnection detecting unit A comprises a high-voltage PMOS tube Ma0～Ma(n-1)Voltage V ofDDHVAnd a high voltage PMOS transistor Ma0～Ma(n-1)Is connected with a source electrode of the high-voltage PMOS transistor Ma0And a high voltage PMOS transistor Ma1～Ma(n-1)Respectively form a current mirror and a high-voltage PMOS tube Ma0Is a source of a current mirror and is composed of a direct current source I0Providing a mirror current, wherein the high voltage PMOS transistor Ma0And a high voltage PMOS transistor MajThe current mirror is used as a DC current source IjHigh voltage PMOS transistor Ma0Drain electrode of (1) and DC current source I0Is connected to a DC current source I0The output end of the transformer is grounded;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube MbjSource electrode and high voltage PMOS transistor MajIs connected to the drain of the transistor, a narrow pulse signal XCLKHVControl high-voltage PMOS tube MbjThe grid of (1), wherein the high voltage PMOS tube MbjAs a switch SWjHigh voltage PMOS tubeMbjDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjAnd a comparator AbjIs connected to the positive input terminal of the resistor RbjAnother terminal of (1) and a resistor RcjAnd a comparator AajIs connected to the positive input terminal of the resistor RcjIs connected to a voltage source V at the other endjNegative pole of (2), voltage source V1The negative electrode of (2) is grounded; comparator AbjAnd a comparator AajThe reverse input ends are connected with a voltage source VjSupplied reference voltage VREFjComparator AbjThe output end is connected with a logic OR gate A101Input terminal of, comparator AajThe output ends of the two-way switch are connected with a logic OR gate A102Wherein the comparator AajAnd a comparator AbjAs a comparator AjLogical OR gate A101And logic OR gate A102As a logic OR gate A11，1≤j≤n-1；
The signal OVP comprises a signal OVP1 and a signal OVP2, and a logic OR gate A101The output signal of (1) is OVP1, and the signal OVP1 is D flip-flop A in the asynchronous counter circuit16And D flip-flop A17And D flip-flop A18Providing a clear signal, D flip-flop A16D trigger A17D trigger A18Respective clock signals are provided by the output end XQ of the previous D flip-flop, the input ends D of the three D flip-flops are connected to the respective output ends XQ, and the output ends Q of the three D flip-flops pass through an AND logic AND gate A19A rear output signal OVP _ G; logic OR gate A102Is OVP2 and is transmitted to D flip-flop A13Input terminal D, D flip-flop A13The input end CLK is formed by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B passing through a time delay unit A14The generated signal controls, D flip-flop A13And j is more than or equal to 1 and less than or equal to n-1.
The time sequence and control unit circuit B comprises a high-voltage PMOS tube M1High voltage PMOS transistor M1Source and high voltage PMOS transistor M2Source, highPressing PMOS tube M3Source electrode, high voltage PMOS tube M4Source electrode, high voltage PMOS tube M5The source electrodes are all connected to a power supply voltage VDDHVHigh voltage PMOS transistor M1Grid and drain thereof and high-voltage PMOS (P-channel metal oxide semiconductor) transistor M2High voltage PMOS transistor M3High voltage PMOS transistor M4The grid electrode of the PMOS transistor M is connected to form a current mirror, and a high-voltage PMOS transistor M1The drain electrode is also connected with the ground through a current source I;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube M2The drain electrode is connected with a high-voltage PMOS tube M5Grid, high-voltage NMOS tube M9Drain electrode of (1) and high voltage NMOS transistor M8And through a capacitor C and a high voltage NMOS transistor M9Source electrode, high voltage NMOS tube M8Source electrode, high voltage NMOS tube M7Source electrode, high voltage NMOS transistor M6The source electrode of the transistor is connected with the back ground GND; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M3Drain and high voltage NMOS transistor M8Drain and inverter B1The input ends are connected; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M4Drain and high voltage NMOS transistor M7Drain and grid and high-voltage NMOS tube M6The grid electrodes are connected; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M5Drain and high voltage NMOS transistor M6Drain and inverter B2The input ends are connected;
inverter B2And an R-S flip-flop B4The R end of (A) is connected; inverter B1Through an inverter B3Switch-in to R-S trigger B4The S terminal of (1); R-S trigger B4Is passed through an inverter B5As an output clock signal XCLK, and from B5Output end of the NMOS transistor M is fed back to the NMOS transistor M9A gate electrode of (1).
Figure GDA0002163960440000041
VBLDIs D flip-flop A13The voltage of the output signal BLD at the output terminal Q.
Counter A12Comprises an input end and a logic OR gate A11D flip-flop a connected to the output terminal of16D trigger A17And D flip-flop A18Logical OR gate A11The output of the over voltage protection circuit is an OVP signal which is a D trigger A in an asynchronous counter circuit16And D flip-flop A17And D flip-flop A18Providing a zero clearing signal; the output ends Q of the three D triggers pass through a logic AND gate A19Rear output signal OVP _ G, logic AND gate A19The output terminal of the narrow pulse signal XCLK is connected to the logic OR gate A15Input terminal of (1), logic OR gate A15Is connected to the D flip-flop A16Clock signal CLK, D flip-flop A17Clock signal CLK is connected to D flip-flop A16Output XQ and input D, D flip-flop A18Clock signal CLK is connected to D flip-flop A17An output XQ and an input D.
D flip-flop A13CLK through an inverter A20And a delay unit A14The generated signal controls.
The working principle of the invention is as follows: when a certain battery is disconnected or overvoltage occurs, the level of the disconnected output signal is changed, and the disconnected signal is only passed through the D flip-flop A when the falling edge of XCLK arrives13Output a BLD signal to control the discharge tube Q via a level conversion circuit2Thereby controlling the discharge tube Q2The switch of (1); in order to prevent external interference OR overvoltage phenomenon of battery at a certain moment, a counter circuit is added in the disconnection detection unit, after several continuous high pulses, overvoltage detection signal OVP and disconnection detection signal BLD are respectively input to logic OR gate OR, and output signal of the OR gate NMOS charging tube Q is connected with circuit board and battery through level conversion circuit1Thereby controlling the charging tube Q1The switch of (2).
Compared with the prior art, the invention has at least the following beneficial effects: the voltage of each battery is acquired through the proportional resistor, and the output change of the voltage comparator can be caused when the battery is in overvoltage or disconnection, so that the overvoltage or disconnection detection is not influenced when any battery in the battery pack is in undervoltage; when the battery is in overvoltage or disconnection, the battery voltage is multiplexed with the reference voltage through different divider resistors to detect the disconnection or overvoltage of the battery, and corresponding protective measures are taken.
In the traditional circuit, the battery overvoltage detection module is also used as a battery disconnection detection module, and the traditional circuit has the advantages of more comparators, large chip area and large power consumption. The multiplexing voltage comparator in the circuit can meet the requirement of simultaneously detecting the conditions of battery disconnection and battery overvoltage, and narrow pulses are used as clock signals, so that the circuit area is reduced, and the circuit power consumption is reduced.
When battery BATjWhen overvoltage occurs, the voltage collected by the divider resistor is increased, so that the voltage comparator is converted from the original low level to the high level, the D trigger triggers the circuit protection switch to stop charging the battery, and when the battery BAT is usedjWhen the disconnection occurs, the voltage collected by the divider resistor is raised to the power supply voltage VC by the PMOS tubejAnd the output end of the voltage comparator is converted from the original low level to the high level, and the D trigger triggers the circuit protection switch to stop charging the battery. When battery BATjWhen under-voltage occurs, VCj+1～VCnThe voltage at is pulled low, and the battery BAT1～BATj-1No influence on voltage, no influence on disconnection or overvoltage detection, as described above, battery BATj+1～BATnIn which there is a battery BATkWhen overvoltage or disconnection occurs, although the voltage collected by the voltage dividing resistor is reduced, BAT is adopted as the reference voltage of the voltage comparatork-1Voltage of plus ViThe collected voltage and the voltage to be compared are reduced at the same time, and the reduction amplitude is consistent, so that the voltage comparator can still correctly turn over under the condition of overvoltage or disconnection, and the disconnection or overvoltage of the battery can still be normally detected under the condition that the battery is under-voltage.
Furthermore, the disconnection detection circuit provided by the invention can share a comparator for disconnection detection and overvoltage detection, and can effectively distinguish disconnection or overvoltage.
Drawings
FIG. 1 is a block diagram of a battery disconnection detection system of the present invention;
fig. 2 is a schematic circuit diagram of a battery disconnection detecting section in embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of the circuitry in the timing and control unit of the present invention;
fig. 4 is a schematic circuit diagram of a battery disconnection detecting section in embodiment 2 of the present invention;
fig. 5 is a schematic circuit diagram of a battery disconnection detecting section in embodiment 3 of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in FIG. 1, the present invention comprises a disconnection detecting unit A, a timing and control unit B, and a plurality of batteries BAT connected in series1～BATnN is a positive integer greater than or equal to 2;
battery BATiThrough a resistor R connected in seriesiAnd a capacitor CiThe RC filter circuit is grounded, and the battery BAT1The negative electrode is grounded, i is more than or equal to 1 and less than or equal to n; battery BATjVoltage VC of the batteryjBy connecting a voltage-dividing resistor R0jTo obtain a partial pressure VFBjInput comparator AjPositive input terminal of (1), comparator AjIs connected with a reference voltage VREFj，1≤j≤n-1；
Figure GDA0002163960440000061
VBLDIs D flip-flop A13The voltage of the output signal BLD at the output terminal Q. Resistance R01～R0(n-1)Are connected in series in sequence and are provided with a resistor R01One end is grounded;
highest battery BATnThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage VDDHVRespectively connected with a DC current source I1～In-1Is connected to a DC current source IjIs passed through a switch SWjCorresponding resistance R0jIs connected to one end of a switch SWjThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A10Generated narrow pulse signal XCLKHVControl in XCLKHVDetecting an on in the circuit when the falling edge ofSwitch SWjClosing, j is more than or equal to 1 and less than or equal to n-1;
comparator AjIs connected to the logic or gate a11J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A11And D flip-flop A13Input terminal D and counter A12Is connected to the input of D flip-flop A13CLK through an inverter A20And a delay unit A14The generated signal controls, D flip-flop A13The output signal BLD of the output terminal Q is respectively connected to the input terminals of the logic OR gate 101 and the second level shift unit 104, the output signal of the second level shift unit 104 passes through the second inverter 105 to output the signal DHC to control the NMOS transistor Q2, and the other input terminal of the logic OR gate 101 is connected to the counter A12The output end of the logic or gate 101 outputs a signal CHC through the first level shifting unit 102 and the first inverter 103 to control the NMOS transistor Q1。
As shown in FIG. 1, the battery disconnection detecting unit can eliminate the highest BAT by multiplexing the overvoltage comparatornOutside BAT1～BATn-1The battery cells are respectively subjected to disconnection and overvoltage detection. The circuit is mainly composed of a pull-up current source I1～In-1And an overvoltage comparator OV1～OVn-1And a voltage dividing resistor R01～R0(n-1)The structure can simultaneously carry out overvoltage and disconnection detection on the n-1 batteries. A narrow pulse signal XCLK with a certain period generated by a timing and control unitHVSwitch SW for controlling overvoltage and disconnection detection of each battery1～SWn-1. Only when XCLK is presentHVThe disconnection detection is effected when the signal is low, by judging the jth battery voltage VCjWhether or not it is higher than the set reference voltage VREFjThrough an overvoltage comparator OVjOutputting a disconnection or overvoltage signal of the battery; the over-voltage signal OVP controls the charging tube Q by controlling the grid signal CHC1The switch of (1); the wire-break signal BLD controls the charging tube Q by controlling the gate voltages CHC and DHC1And a discharge tube Q2Thereby functioning as a protection of the battery and the chip, whichIn the formula, j is more than or equal to 1 and less than or equal to n-1.
In example 1 of the present invention:
as shown in FIG. 2, the battery disconnection detecting unit A includes a high voltage PMOS transistor Ma0～Ma(n-1)Voltage V ofDDHVAnd a high voltage PMOS transistor Ma0～Ma(n-1)Is connected with a source electrode of the high-voltage PMOS transistor Ma0And a high voltage PMOS transistor Ma1～Ma(n-1)Respectively form a current mirror and a high-voltage PMOS tube Ma0Is a source of a current mirror and is composed of a direct current source I0Providing a mirror current, wherein the high voltage PMOS transistor Ma0And a high voltage PMOS transistor MajThe current mirror is used as a DC current source IjJ is more than or equal to 1 and less than or equal to n-1; high-voltage PMOS (P-channel Metal oxide semiconductor) tube Ma0Drain electrode of (1) and DC current source I0Is connected to a DC current source I0The output end of the transformer is grounded;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube MbjSource electrode and high voltage PMOS transistor MajIs connected to the drain of the transistor, a narrow pulse signal XCLKHVControl high-voltage PMOS tube MbjThe grid of (1), wherein the high voltage PMOS tube MbjAs a switch SWjHigh voltage PMOS transistor MbjDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjOne end of and a high voltage NMOS tube McjIs connected to the drain of the resistor RbjAnother terminal of (1) and a resistor RcjOne end of and a high voltage NMOS tube MdjIs connected to the drain of the resistor RcjIs connected to a voltage source V at the other endjThe negative electrode of (1); high-voltage NMOS tube McjIs formed by XCLKHVA signal control, the source of which is connected to the positive input end of the comparator Aj; high-voltage NMOS tube MdjGate of from CLKHVControl of signal, source and comparator AjThe positive input end of the power supply is connected; comparator AjThe reverse input end of the voltage source is connected with a voltage source VjThe provided reference voltage VREFjThe output end is connected with a logic OR gate A11Wherein j is more than or equal to 1 and less than or equal to n-1; voltage source V1The negative electrode of (2) is grounded.
In this embodiment, the counter A12Comprising an input and a logicEdit OR gate A11D flip-flop a connected to the output terminal of16D trigger A17And D flip-flop A18Logical OR gate A11The output of the over voltage protection circuit is an OVP signal which is a D trigger A in an asynchronous counter circuit16And D flip-flop A17And D flip-flop A18Providing a zero clearing signal; the output ends Q of the three D triggers pass through a logic AND gate A19Rear output signal OVP _ G, logic AND gate A19The output terminal of the narrow pulse signal XCLK is connected to the logic OR gate A15Input terminal of (1), logic OR gate A15Is connected to the D flip-flop A16Clock signal CLK, D flip-flop A17Clock signal CLK is connected to D flip-flop A16Output XQ and input D, D flip-flop A18Clock signal CLK is connected to D flip-flop A17An output XQ and an input D.
Take the second battery over-voltage as the example, when BAT2When overvoltage occurs and XCLK high level arrives, VC2The voltage at (R) is correspondingly raiseda2And Rb2Voltage rise ratio R betweenb2And Rc2A large amount of voltage rise between, and a voltage comparator A2The voltage at the forward input terminal is higher than that at the reverse input terminal, the output becomes high level, so that the logic OR gate A11The output signal OVP changes from low level to high level, and the D trigger A13The CLK signal is changed from high level to low level and is in a holding state, the high level signal of the OVP can not be sent to the BLD, the OVP is used as a zero clearing signal of a D trigger in the counter to lose zero clearing effect, the OVP _ G is raised after the counter counts for a period of time, the switch tube CHC is switched off, and the circuit enters a protection state; when BAT2When a wire break occurs, VC2The voltage is raised to VCnAt this time, no matter the NMOS tube Mc2Or NMOS tube Md2The collected levels are all higher than the reference voltage VREF2Voltage comparator A2The output is changed into high level, the OVP is also changed into high level, when XCKL is low level, the OVP is triggered by D trigger A13Then, the signal BLD also goes high, which turns to low through an inverter to turn off the switch tube DHC,the circuit enters a protection state.
The circuit of the battery disconnection detection unit is mainly used for disconnection and overvoltage detection, wherein the high-voltage PMOS tube Ma1Source of (2) is connected to VDDHVObtaining the same current by taking the same width and length of the MOS tube, wherein the current relationship is as follows:
Figure GDA0002163960440000081
wherein, IMa1Is a PMOS tube Ma0Upper drain current, I0Is a PMOS tube Ma0W/L is the width-to-length ratio of the MOS transistor.
Resistance Ra1Another end of the resistor R is connected in seriesb1And a resistance Rc1And through a resistor Rc1Connected to GND, these three resistors form a voltage divider circuit:
Figure GDA0002163960440000082
Figure GDA0002163960440000083
wherein, VC1Representing the first battery voltage, VOV1Representing the voltage division at the higher point of the first battery when the signal CLK is a narrow pulseHVWhen the voltage is high, the switch tube Md1Is opened and Mc1The power-off is used for detecting the overvoltage of the first battery when the chip works; vBLD1Representing the voltage division at the lower point of the 1 st cell when the narrow pulse signal XCLKHVAt a high level, i.e. CLKHVAt a low level, the switch tube Mc1Is opened and Md1And the power-off is used for detecting the disconnection of the first battery when the chip works. Due to the narrow pulse CLKHVAnd XCLKHVIs a periodic signal, only at CLKHVThe rising edge of the chip starts to detect whether the battery is disconnected or not, the duration time of the high level of the pulse signal is short, the chip works for a great part of time and only detects whether the battery is overvoltage or not, and the disconnection is periodicAnd (4) sex detection. Therefore, the overvoltage comparator can be multiplexed, a comparator circuit designed for disconnection detection independently is saved, and the circuit area is effectively reduced.
Referring to fig. 3, the timing and control unit circuit B includes a high voltage PMOS transistor M1High voltage PMOS transistor M1Source and high voltage PMOS transistor M2Source electrode, high voltage PMOS tube M3Source electrode, high voltage PMOS tube M4Source electrode, high voltage PMOS tube M5The source electrodes are all connected to a power supply voltage VDDHVHigh voltage PMOS transistor M1Grid and drain thereof and high-voltage PMOS (P-channel metal oxide semiconductor) transistor M2High voltage PMOS transistor M3High voltage PMOS transistor M4The grid electrode of the PMOS transistor M is connected to form a current mirror, and a high-voltage PMOS transistor M1The drain electrode is also connected with the ground through a current source I;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube M2The drain electrode is connected with a high-voltage PMOS tube M5Grid, high-voltage NMOS tube M9Drain electrode of (1) and high voltage NMOS transistor M8And through a capacitor C and a high voltage NMOS transistor M9Source electrode, high voltage NMOS tube M8Source electrode, high voltage NMOS tube M7Source electrode, high voltage NMOS transistor M6The source electrode of the transistor is connected with the back ground GND; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M3Drain and high voltage NMOS transistor M8Drain and inverter B1The input ends are connected; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M4Drain and high voltage NMOS transistor M7Drain and grid and high-voltage NMOS tube M6The grid electrodes are connected; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M5Drain and high voltage NMOS transistor M6Drain and inverter B2The input ends are connected;
inverter B2And an R-S flip-flop B4The R end of (A) is connected; inverter B1Through an inverter B3Switch-in to R-S trigger B4The S terminal of (1); R-S trigger B4Is passed through an inverter B5As an output clock signal XCLK, and from B5Output end of the NMOS transistor M is fed back to the NMOS transistor M9Wherein:
charging time t of capacitor C1Can be solved by the following differential equation:
Figure GDA0002163960440000091
wherein, US represents when PMOS tube M5Voltage at turn-on, i.e.:
Us＝VDDHV-VTHP(5)
r represents NMOS tube M9When the circuit works in a linear region, the equivalent on-resistance at two ends of a drain source and the discharge time t of a capacitor C2Can be solved by the following differential equation:
Figure GDA0002163960440000092
the parameters in the equation have disorder codes
Wherein, U0When the high voltage PMOS transistor M is used8Initial voltage of the capacitor C when conducting.
As shown in fig. 4, in embodiment 2 of the present invention, the counter has the same structure as that of embodiment 1, and the battery disconnection detecting unit a includes a resistor R1～Rn-1Voltage V ofDDHVAnd a resistor RjIs connected to one end of a resistor RjAs a direct current source IjThe other end of the resistor Rj is connected to the high-voltage PMOS tube MajWherein, the high voltage PMOS transistor MajAs a switch SWjFrom a narrow pulse signal XCLKHVControl high-voltage PMOS tube MajGrid of (1), high voltage PMOS transistor MajDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjOne end of and a high voltage NMOS tube McjIs connected to the drain of the resistor RbjAnother terminal of (1) and a resistor RcjOne end of and a high voltage NMOS tube MdjIs connected to the drain of the resistor RcjIs connected to a voltage source V at the other endjThe negative electrode of (1); high-voltage NMOS tube McjIs formed by XCLKHVSignal control with source connected to comparator AjThe positive input terminal of (1); high-voltage NMOS tube MdjGate of from CLKHVControl of signal, source and comparator AjThe positive input end of the power supply is connected; comparator AjThe reverse input end of the voltage source is connected with a voltage source VjThe provided reference voltage VREFjThe output end is connected with a logic OR gate A11Wherein j is more than or equal to 1 and less than or equal to n-1; voltage source V1The negative electrode of (2) is grounded.
In embodiment 3 of the present invention, as shown in fig. 5, the battery disconnection detecting unit a includes a high voltage PMOS transistor Ma0～Ma(n-1)Voltage V ofDDHVAnd a high voltage PMOS transistor Ma0～Ma(n-1)Is connected with a source electrode of the high-voltage PMOS transistor Ma0And a high voltage PMOS transistor Ma1～Ma(n-1)Respectively form a current mirror and a high-voltage PMOS tube Ma0Is a source of a current mirror and is composed of a direct current source I0Providing a mirror current, wherein the high voltage PMOS transistor Ma0And a high voltage PMOS transistor MajThe current mirror is used as a DC current source IjHigh voltage PMOS transistor Ma0Drain electrode of (1) and DC current source I0Is connected to a DC current source I0The output end of the transformer is grounded;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube MbjSource electrode and high voltage PMOS transistor MajIs connected to the drain of the transistor, a narrow pulse signal XCLKHVControl high-voltage PMOS tube MbjThe grid of (1), wherein the high voltage PMOS tube MbjAs a switch SWjHigh voltage PMOS transistor MbjDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjAnd a comparator AbjIs connected to the positive input terminal of the resistor RbjAnother terminal of (1) and a resistor RcjAnd a comparator AajIs connected to the positive input terminal of the resistor RcjIs connected to a voltage source V at the other endjNegative pole of (2), voltage source V1The negative electrode of (2) is grounded; comparator AbjAnd a comparator AajThe reverse input ends are connected with a voltage source VjSupplied reference voltage VREFjComparator AbjThe output end is connected with a logic OR gate A101Input terminal of, comparator AajThe output ends of the two-way switch are connected with a logic OR gate A102Wherein the comparator AajAnd a comparator AbjAs comparator a in fig. 1jLogical OR gate A101And logic OR gate A102As a logic OR gate A11，1≤j≤n-1；
The signal OVP comprises a signal OVP1 and a signal OVP2, and a logic OR gate A101The output signal of (1) is OVP1, and the signal OVP1 is D flip-flop A in the asynchronous counter circuit16And D flip-flop A17And D flip-flop A18Providing a clear signal, D flip-flop A16D trigger A17D trigger A18Respective clock signals are provided by the output end XQ of the previous D flip-flop, the input ends D of the three D flip-flops are connected to the respective output ends XQ, and the output ends Q of the three D flip-flops pass through an AND logic AND gate A19A rear output signal OVP _ G; logic OR gate A102Is OVP2 and is transmitted to D flip-flop A13Input terminal D, D flip-flop A13The input end CLK is formed by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B passing through a time delay unit A14The generated signal controls, D flip-flop A13And j is more than or equal to 1 and less than or equal to n-1.
As can be seen from the disconnection and overvoltage detection modes in the above embodiments 1 and 2, the invention can realize battery overvoltage detection by multiplexing the overvoltage comparator, and can perform disconnection detection by using different voltage dividing resistors, thereby reducing the circuit area; the narrow pulse signal is adopted to periodically detect the broken circuit, so that the power consumption of the circuit can be reduced. It can be seen from embodiment 3 that the disconnection detection function proposed by the present invention can be implemented without multiplexing the overvoltage comparator.
The above is only the best embodiment of the present invention, and does not constitute any limitation to the present invention, and it is obvious that various changes and modifications can be made to the circuit thereof under the concept of the present invention, but these are all protected by the present invention.

Claims (7)

1. A circuit for detecting disconnection of a multi-section battery core protection board is characterized by comprising a disconnection detection unit A, a time sequence and control unit B and a plurality of batteries BAT connected in series1～BATnN is a positive integer greater than or equal to 2;
battery with a battery cellBATiThrough a resistor R connected in seriesiAnd a capacitor CiThe RC filter circuit is grounded, and the battery BAT1The negative electrode is grounded, i is more than or equal to 1 and less than or equal to n; battery BATjVoltage VC of the batteryjBy connecting a voltage-dividing resistor R0jTo obtain a partial pressure VFBjInput comparator AjPositive input terminal of (1), comparator AjIs connected with a reference voltage VREFjJ is more than or equal to 1 and less than or equal to n-1, and the resistance R01～R0(n-1)Are connected in series in sequence and are provided with a resistor R01One end is grounded;
highest battery BATnThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage VDDHVRespectively connected with a DC current source I1～In-1Is connected to a DC current source IjIs passed through a switch SWjCorresponding resistance R0jIs connected to one end of a switch SWjThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A10Generated narrow pulse signal XCLKHVControlling j to be more than or equal to 1 and less than or equal to n-1;
comparator AjIs connected to the logic or gate a11J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A11And D flip-flop A13Input terminal D and counter A12Is connected to the input of D flip-flop A13The input end CLK is formed by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B passing through a time delay unit A14The generated signal controls, D flip-flop A13The output signal BLD of the output end Q is respectively connected to the input ends of the logic OR gate (101) and the second level conversion unit (104), the output end signal of the second level conversion unit (104) passes through the second inverter (105) to output a signal DHC to control the NMOS tube Q2, and the other input end of the logic OR gate (101) is connected with the counter A12The output end of the logic or gate (101) outputs a signal CHC through a first level conversion unit (102) and a first phase inverter (103) to control an NMOS tube Q1；
The battery disconnection detection unit A comprises a high-voltage PMOS tube Ma0～Ma(n-1)Voltage V ofDDHVAnd a high voltage PMOS transistor Ma0～Ma(n-1)Is connected with a source electrode of the high-voltage PMOS transistor Ma0And a high voltage PMOS transistor Ma1～Ma(n-1)Respectively form a current mirror and a high-voltage PMOS tube Ma0Is a source of a current mirror and is composed of a direct current source I0Providing a mirror current, wherein the high voltage PMOS transistor Ma0And a high voltage PMOS transistor MajThe current mirror is used as a DC current source IjJ is more than or equal to 1 and less than or equal to n-1; high-voltage PMOS (P-channel Metal oxide semiconductor) tube Ma0Drain electrode of (1) and DC current source I0Is connected to a DC current source I0The output end of the transformer is grounded;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube MbjSource electrode and high voltage PMOS transistor MajIs connected to the drain of the transistor, a narrow pulse signal XCLKHVControl high-voltage PMOS tube MbjThe grid of (1), wherein the high voltage PMOS tube MbjAs a switch SWjHigh voltage PMOS transistor MbjDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjOne end of and a high voltage NMOS tube McjIs connected to the drain of the resistor RbjAnother terminal of (1) and a resistor RcjOne end of and a high voltage NMOS tube MdjIs connected to the drain of the resistor RcjIs connected to a voltage source V at the other endjThe negative electrode of (1); high-voltage NMOS tube McjIs formed by XCLKHVA signal control, the source of which is connected to the positive input end of the comparator Aj; high-voltage NMOS tube MdjGate of from CLKHVControl of signal, source and comparator AjThe positive input end of the power supply is connected; comparator AjThe reverse input end of the voltage source is connected with a voltage source VjThe provided reference voltage VREFjThe output end is connected with a logic OR gate A11Wherein j is more than or equal to 1 and less than or equal to n-1; voltage source V1The negative electrode of (2) is grounded.
2. A circuit for detecting disconnection of a multi-section battery core protection board is characterized by comprising a disconnection detection unit A, a time sequence and control unit B and a plurality of batteries BAT connected in series1～BATnN is a positive integer greater than or equal to 2;
battery BATiBy series connection of positive electrodesResistance R ofiAnd a capacitor CiThe RC filter circuit is grounded, and the battery BAT1The negative electrode is grounded, i is more than or equal to 1 and less than or equal to n; battery BATjVoltage VC of the batteryjBy connecting a voltage-dividing resistor R0jTo obtain a partial pressure VFBjInput comparator AjPositive input terminal of (1), comparator AjIs connected with a reference voltage VREFjJ is more than or equal to 1 and less than or equal to n-1, and the resistance R01～R0(n-1)Are connected in series in sequence and are provided with a resistor R01One end is grounded;
highest battery BATnThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage VDDHVRespectively connected with a DC current source I1～In-1Is connected to a DC current source IjIs passed through a switch SWjCorresponding resistance R0jIs connected to one end of a switch SWjThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A10Generated narrow pulse signal XCLKHVControlling j to be more than or equal to 1 and less than or equal to n-1;
comparator AjIs connected to the logic or gate a11J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A11And D flip-flop A13Input terminal D and counter A12Is connected to the input of D flip-flop A13The input end CLK is formed by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B passing through a time delay unit A14The generated signal controls, D flip-flop A13The output signal BLD of the output end Q is respectively connected to the input ends of the logic OR gate (101) and the second level conversion unit (104), the output end signal of the second level conversion unit (104) passes through the second inverter (105) to output a signal DHC to control the NMOS tube Q2, and the other input end of the logic OR gate (101) is connected with the counter A12The output end of the logic or gate (101) outputs a signal CHC through a first level conversion unit (102) and a first phase inverter (103) to control an NMOS tube Q1；
The battery disconnection detecting unit A includes a resistor R1～Rn-1Voltage V ofDDHVAnd a resistor RjIs connected to one end of a resistor RjAs a direct current source IjThe other end of the resistor Rj is connected to the high-voltage PMOS tube MajWherein, the high voltage PMOS transistor MajAs a switch SWjFrom a narrow pulse signal XCLKHVControl high-voltage PMOS tube MajGrid of (1), high voltage PMOS transistor MajDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjOne end of and a high voltage NMOS tube McjIs connected to the drain of the resistor RbjAnother terminal of (1) and a resistor RcjOne end of and a high voltage NMOS tube MdjIs connected to the drain of the resistor RcjIs connected to a voltage source V at the other endjThe negative electrode of (1); high-voltage NMOS tube McjIs formed by XCLKHVSignal control with source connected to comparator AjThe positive input terminal of (1); high-voltage NMOS tube MdjGate of from CLKHVControl of signal, source and comparator AjThe positive input end of the power supply is connected; comparator AjThe reverse input end of the voltage source is connected with a voltage source VjThe provided reference voltage VREFjThe output end is connected with a logic OR gate A11Wherein j is more than or equal to 1 and less than or equal to n-1; voltage source V1The negative electrode of (2) is grounded.
3. A circuit for detecting disconnection of a multi-section battery core protection board is characterized by comprising a disconnection detection unit A, a time sequence and control unit B and a plurality of batteries BAT connected in series1～BATnN is a positive integer greater than or equal to 2;
battery BATiThrough a resistor R connected in seriesiAnd a capacitor CiThe RC filter circuit is grounded, and the battery BAT1The negative electrode is grounded, i is more than or equal to 1 and less than or equal to n; battery BATjVoltage VC of the batteryjBy connecting a voltage-dividing resistor R0jTo obtain a partial pressure VFBjInput comparator AjPositive input terminal of (1), comparator AjIs connected with a reference voltage VREFjJ is more than or equal to 1 and less than or equal to n-1, and the resistance R01～R0(n-1)Are connected in series in sequence and are provided with a resistor R01One end is grounded;
highest battery BATnThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage VDDHVRespectively connected with a DC current source I1～In-1Is connected to a DC current source IjIs passed through a switch SWjCorresponding resistance R0jIs connected to one end of a switch SWjThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A10Generated narrow pulse signal XCLKHVControlling j to be more than or equal to 1 and less than or equal to n-1;
comparator AjIs connected to the logic or gate a11J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A11And D flip-flop A13Input terminal D and counter A12Is connected to the input of D flip-flop A13The input end CLK is formed by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B passing through a time delay unit A14The generated signal controls, D flip-flop A13The output signal BLD of the output end Q is respectively connected to the input ends of the logic OR gate (101) and the second level conversion unit (104), the output end signal of the second level conversion unit (104) passes through the second inverter (105) to output a signal DHC to control the NMOS tube Q2, and the other input end of the logic OR gate (101) is connected with the counter A12The output end of the logic or gate (101) outputs a signal CHC through a first level conversion unit (102) and a first phase inverter (103) to control an NMOS tube Q1；
The battery disconnection detection unit A comprises a high-voltage PMOS tube Ma0～Ma(n-1)Voltage V ofDDHVAnd a high voltage PMOS transistor Ma0～Ma(n-1)Is connected with a source electrode of the high-voltage PMOS transistor Ma0And a high voltage PMOS transistor Ma1～Ma(n-1)Respectively form a current mirror and a high-voltage PMOS tube Ma0Is a source of a current mirror and is composed of a direct current source I0Providing a mirror current, wherein the high voltage PMOS transistor Ma0And a high voltage PMOS transistor MajThe current mirror is used as a DC current source IjHigh voltage PMOS transistor Ma0Drain electrode of (1) and DC current source I0Is connected to a DC current source I0The output end of the transformer is grounded;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube MbjSource and high voltage PMOS pipe MajIs connected to the drain of the transistor, a narrow pulse signal XCLKHVControl high-voltage PMOS tube MbjThe grid of (1), wherein the high voltage PMOS tube MbjAs a switch SWjHigh voltage PMOS transistor MbjDrain electrode connection resistance RajOne terminal of (1), battery voltage VCjAnd a voltage source V(j+1)Negative electrode of (2), resistance RajAnother terminal of (1) and a resistor RbjAnd a comparator AbjIs connected to the positive input terminal of the resistor RbjAnother terminal of (1) and a resistor RcjAnd a comparator AajIs connected to the positive input terminal of the resistor RcjIs connected to a voltage source V at the other endjNegative pole of (2), voltage source V1The negative electrode of (2) is grounded; comparator AbjAnd a comparator AajThe reverse input ends are connected with a voltage source VjSupplied reference voltage VREFjComparator AbjThe output end is connected with a logic OR gate A101Input terminal of, comparator AajThe output ends of the two-way switch are connected with a logic OR gate A102Wherein the comparator AajAnd a comparator AbjAs a comparator AjLogical OR gate A101And logic OR gate A102As a logic OR gate A11，1≤j≤n-1；
The signal OVP comprises a signal OVP1 and a signal OVP2, and a logic OR gate A101The output signal of (1) is OVP1, and the signal OVP1 is D flip-flop A in the asynchronous counter circuit16And D flip-flop A17And D flip-flop A18Providing a clear signal, D flip-flop A16D trigger A17D trigger A18Respective clock signals are provided by the output end XQ of the previous D flip-flop, the input ends D of the three D flip-flops are connected to the respective output ends XQ, and the output ends Q of the three D flip-flops pass through an AND logic AND gate A19A rear output signal OVP _ G; logic OR gate A102Is OVP2 and is transmitted to D flip-flop A13Input terminal D, D flip-flop A13The input end CLK is formed by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B passing through a time delay unit A14The generated signal controls, D flip-flop A13The output signal BLD at the output terminal Q, wherein,1≤j≤n-1。
4. the circuit for detecting disconnection of a multi-section battery cell protection plate according to any one of claims 1 to 3, wherein the timing and control unit circuit B comprises a high-voltage PMOS (P-channel metal oxide semiconductor) transistor M1High voltage PMOS transistor M1Source and high voltage PMOS transistor M2Source electrode, high voltage PMOS tube M3Source electrode, high voltage PMOS tube M4Source electrode, high voltage PMOS tube M5The source electrodes are all connected to a power supply voltage VDDHVHigh voltage PMOS transistor M1Grid and drain thereof and high-voltage PMOS (P-channel metal oxide semiconductor) transistor M2High voltage PMOS transistor M3High voltage PMOS transistor M4The grid electrode of the PMOS transistor M is connected to form a current mirror, and a high-voltage PMOS transistor M1The drain electrode is also connected with the ground through a current source I;
high-voltage PMOS (P-channel Metal oxide semiconductor) tube M2The drain electrode is connected with a high-voltage PMOS tube M5Grid, high-voltage NMOS tube M9Drain electrode of (1) and high voltage NMOS transistor M8And through a capacitor C and a high voltage NMOS transistor M9Source electrode, high voltage NMOS tube M8Source electrode, high voltage NMOS tube M7Source electrode, high voltage NMOS transistor M6The source electrode of the transistor is connected with the back ground GND; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M3Drain and high voltage NMOS transistor M8Drain and inverter B1The input ends are connected; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M4Drain and high voltage NMOS transistor M7Drain and grid and high-voltage NMOS tube M6The grid electrodes are connected; high-voltage PMOS (P-channel Metal oxide semiconductor) tube M5Drain and high voltage NMOS transistor M6Drain and inverter B2The input ends are connected;
inverter B2And an R-S flip-flop B4The R end of (A) is connected; inverter B1Through an inverter B3Switch-in to R-S trigger B4The S terminal of (1); R-S trigger B4Is passed through an inverter B5As an output clock signal XCLK, and from B5Output end of the NMOS transistor M is fed back to the NMOS transistor M9A gate electrode of (1).
5. The multi-section battery protection board disconnection detecting circuit according to any one of claims 1 to 3,
Figure FDA0002163960430000051
VBLDis D flip-flop A13The voltage of the output signal BLD at the output terminal Q.
6. The multi-section battery protection board disconnection detection circuit of any one of claims 1 to 3, wherein the counter A is arranged in the circuit board12Comprises an input end and a logic OR gate A11D flip-flop a connected to the output terminal of16D trigger A17And D flip-flop A18Logical OR gate A11The output of the over voltage protection circuit is an OVP signal which is a D trigger A in an asynchronous counter circuit16And D flip-flop A17And D flip-flop A18Providing a zero clearing signal; the output ends Q of the three D triggers pass through a logic AND gate A19Rear output signal OVP _ G, logic AND gate A19The output terminal of the narrow pulse signal XCLK is connected to the logic OR gate A15Input terminal of (1), logic OR gate A15Is connected to the D flip-flop A16Clock signal CLK, D flip-flop A17Clock signal CLK is connected to D flip-flop A16Output XQ and input D, D flip-flop A18Clock signal CLK is connected to D flip-flop A17An output XQ and an input D.
7. The circuit for detecting disconnection of a plurality of sections of battery cell protection boards according to any one of claims 1 to 3, wherein the D trigger A is13CLK through an inverter A20And a delay unit A14The generated signal controls.
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