CN219802150U - Buffer power supply and control circuit thereof - Google Patents
Buffer power supply and control circuit thereof Download PDFInfo
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- CN219802150U CN219802150U CN202320156950.8U CN202320156950U CN219802150U CN 219802150 U CN219802150 U CN 219802150U CN 202320156950 U CN202320156950 U CN 202320156950U CN 219802150 U CN219802150 U CN 219802150U
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- power supply
- mos tube
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- buffer
- electrode
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- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 230000003071 parasitic effect Effects 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 3
- 230000000151 anti-reflux effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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Abstract
The utility model relates to the field of button battery power supply of Internet of things equipment, and discloses a buffer power supply and a control circuit thereof, wherein the buffer power supply comprises a power supply control circuit, and the power supply control circuit comprises a power supply input end, a power supply output end and a control end for conducting a power supply at a low level; a source electrode and a drain electrode of the MOS tube are connected in series between the power input end and the power output end; and a grid electrode of the MOS tube is connected with the control end, and a capacitor is connected in parallel between a source electrode and the grid electrode of the MOS tube. The scheme utilizes the capacitor to enable the battery to discharge in an equalizing mode all the time, controls the rising speed of the output voltage, reduces the heat loss of the internal resistance as much as possible, and further prolongs the service time of the battery.
Description
Technical Field
The utility model belongs to the field of button battery power supply of Internet of things equipment, and particularly relates to a buffer power supply and a control circuit thereof.
Background
Along with the wide application of the internet of things equipment, the requirements on miniaturization and standby time of battery products are also higher and higher, and it is more important to reduce the power consumption of the products and prolong the service time (reduce the frequency of battery replacement).
Based on the current situation that the button battery has poor instant discharging capability and large internal resistance, if the battery is directly enabled to output current with maximum capability (between the maximum pulse current and the short-circuit current), the heat loss (internal resistance loss) of the electric quantity of the battery is greatly increased.
Disclosure of Invention
The utility model provides a buffer power supply and a control circuit thereof, which are used for solving the problem of poor instantaneous power supply capability of battery application products.
In order to solve the technical problems, the technical scheme and the corresponding beneficial effects of the technical scheme are as follows:
the utility model provides a scheme of a buffer power supply control circuit, which comprises a power supply input end, a power supply output end and a control end, wherein the power supply input end is used for connecting a power supply, the power supply output end is used for outputting a power supply to the outside, and the control end is used for conducting the power supply at a low level; a source electrode and a drain electrode of the MOS tube are connected in series between the power input end and the power output end; and a grid electrode of the MOS tube is connected with the control end, and a capacitor is connected in parallel between a source electrode and the grid electrode of the MOS tube.
The beneficial effects of the technical scheme are as follows: the traditional power supply control circuit outputs low level to the grid electrode of the MOS tube through the control end, and forms bias voltage between the grid electrodes of the MOS tube and the source electrode of the MOS tube, so that the MOS tube is conducted, the power supply voltage is output to the outside, but the instant maximum conduction can impact the power supply, and the internal resistance loss of the power supply is increased. According to the scheme, the capacitor is connected in parallel between the grid sources of the MOS tube, when the control end outputs low level, the capacitor is charged by the low level of the control end and the voltage between the positive poles of the power supply, the capacitor voltage is slowly increased in the charging process, the MOS tube is gradually conducted, and the voltage between the grid sources of the MOS tube is prevented from being suddenly changed to be instantaneously conducted so that the power supply can directly output the maximum capacity. The utility model uses the capacitor to make the power supply discharge in a balanced way all the time, controls the rising speed of the output voltage, reduces the heat loss of the internal resistance as much as possible, and further prolongs the service time of the battery.
Further, the grid electrode of the MOS tube is grounded through a pull-down resistor.
Furthermore, the grid electrode of the MOS tube is connected with the control end through a voltage dividing resistor, and the capacitor obtains proper voltage division through the voltage dividing resistor so as to ensure that the MOS tube is reliably conducted.
Furthermore, the MOS tube adopts a P-type MOS tube.
Furthermore, a parasitic diode is connected in parallel between the drain electrode and the source electrode of the MOS tube, when a large instant reverse current is generated in the circuit, the reverse current is led out through the parasitic diode, the source electrode and the drain electrode of the MOS tube are protected from being broken down and burned, and the anti-reflux protection of the MOS tube is realized.
The utility model also provides a scheme for buffering the power supply, which comprises a battery and a power supply control circuit, wherein the power supply control circuit comprises a power supply input end connected with the positive electrode of the battery, a power supply output end for outputting a power supply to the outside and a control end for conducting the power supply at a low level; a source electrode and a drain electrode of the MOS tube are connected in series between the power input end and the power output end; and a grid electrode of the MOS tube is connected with the control end, and a capacitor is connected in parallel between a source electrode and a drain electrode of the MOS tube.
The beneficial effects of the technical scheme are as follows: the scheme utilizes the capacitor to enable the battery to discharge in an equalizing mode all the time, controls the rising speed of the output voltage, reduces the heat loss of the internal resistance as much as possible, and further prolongs the service time of the battery.
Further, the grid electrode of the MOS tube is grounded through a pull-down resistor.
Furthermore, the grid electrode of the MOS tube is connected with the control end through a voltage dividing resistor, and the capacitor obtains proper voltage division through the voltage dividing resistor so as to ensure that the MOS tube is reliably conducted.
Furthermore, the MOS tube adopts a P-type MOS tube.
Furthermore, a parasitic diode is connected in parallel between the drain electrode and the source electrode of the MOS tube, when a large instant reverse current is generated in the circuit, the reverse current is led out through the parasitic diode, the source electrode and the drain electrode of the MOS tube are protected from being broken down and burned, and the anti-reflux protection of the MOS tube is realized.
Drawings
Fig. 1 is a circuit diagram of a buffer power control of the present utility model.
Detailed Description
The following describes the embodiments of the present utility model further with reference to the drawings.
Control circuit embodiment:
the buffer power supply control circuit diagram shown in fig. 1 comprises a P-type MOS tube Q1, a pull-down resistor R1, a voltage dividing resistor R2 and a capacitor C1; the source electrode 2 of the P-type MOS tube Q1 is connected with the signal input end Vin, the drain electrode 3 of the P-type MOS tube Q1 is connected with the signal output end Vout, and a parasitic diode is connected between the source electrode and the drain electrode of the P-type MOS tube Q1 in parallel; the grid electrode 1 of the P-type MOS tube Q1 is connected with the first end of a pull-down resistor R1, and the second end of the pull-down resistor R1 is grounded; the grid electrode 1 of the P-type MOS tube Q1 is connected with the first end of a voltage dividing resistor R2, and the second end of the voltage dividing resistor R2 is connected with a control signal CTRL; the source electrode of the P-type MOS tube Q1 is connected with the first end of a capacitor C2, and the second end of the capacitor C1 is connected with the first end of a divider resistor R2.
The principle of the buffer power supply control circuit of the utility model is as follows:
the power supply of Vout is controlled by CTRL signal, when CTRL signal is high level, MOS tube is not conducted, vout voltage is 0V at this moment;
when the CTRL signal is changed from high level to low level, the voltage difference at two ends of the capacitor C1 cannot be suddenly changed, the MOS tube is not conducted at the moment, the voltage difference at two ends of the capacitor C1 is gradually increased along with the charging of the capacitor, the MOS tube starts to be conducted and the conduction internal resistance is gradually reduced in the process, the capacitor of the back-electrode circuit is charged in a small current mode, and the voltage of Vout is gradually increased in the conduction period.
The comparison of the impact current effect graph before improvement and the impact current effect graph after improvement according to the utility model can be known: the highest impact current before improvement is about 940mA, the highest impact current after improvement is about 172mA, and the current after improvement is reduced to about 1/6;
capacitor charge q=cu=i×t; from the initial state to full power, the charging quantity is the same, the charging current is reduced to 1/6, and the time is correspondingly increased by 6 times; wherein C is capacitance; u is the capacitance difference (capacitance full charge voltage-initial voltage); i is the average charging current; t is the charging time.
W0=i according to the resistance heating power 2 RT; as a result, w1= (I/6) × (I/6) ×r× (6T) =w0/6, the heat generation amount was reduced to P/6, that is, the heat generation amount was reduced to 1/6 before improvement; wherein W0 is the heat productivity of the internal resistance before improvement; w1 is the heat generation amount of the improved internal resistance.
Therefore, the scheme utilizes the capacitor to enable the battery to discharge in a balanced mode all the time, controls the rising speed of the output voltage, reduces the heat loss of the internal resistance as much as possible, and further prolongs the service time of the battery.
Buffer power supply embodiment:
the hardware structure and the working principle of the buffer power supply of the present utility model are sufficiently clear that they are described in the embodiment of the control circuit, and are not described herein.
The above gives a specific embodiment to which the present utility model relates, but the present utility model is not limited to the described embodiment. Under the thought of the utility model, the technical means in the embodiment are changed, replaced and modified in a manner which is easily thought to a person skilled in the art, and the technical means have basically the same functions as the corresponding technical means in the utility model, and the aim of the utility model is also basically the same, so that the technical scheme is formed by fine tuning the embodiment, and the technical scheme still falls within the protection scope of the utility model.
Claims (10)
1. The buffer power supply control circuit is characterized by comprising a power supply input end, a power supply output end and a control end, wherein the power supply input end is used for connecting a power supply, the power supply output end is used for outputting a power supply to the outside, and the control end is used for conducting the power supply at a low level; a source electrode and a drain electrode of the MOS tube are connected in series between the power input end and the power output end; and a grid electrode of the MOS tube is connected with the control end, and a capacitor is connected in parallel between a source electrode and the grid electrode of the MOS tube.
2. The buffer power supply control circuit of claim 1, wherein the gate of the MOS transistor is grounded through a pull-down resistor.
3. The buffer power supply control circuit according to claim 2, wherein the gate of the MOS transistor is connected to the control terminal through a voltage dividing resistor.
4. The buffer power control circuit of claim 3, wherein the MOS transistor is a P-type MOS transistor.
5. The buffer power control circuit of claim 4, wherein a parasitic diode is connected in parallel between the drain and source of the MOS transistor.
6. The buffer power supply is characterized by comprising a battery and a power supply control circuit, wherein the power supply control circuit comprises a power supply input end connected with the positive electrode of the battery, a power supply output end for outputting a power supply to the outside and a control end for conducting the power supply at a low level; a source electrode and a drain electrode of the MOS tube are connected in series between the power input end and the power output end; and a grid electrode of the MOS tube is connected with the control end, and a capacitor is connected in parallel between a source electrode and the grid electrode of the MOS tube.
7. The buffer power supply of claim 6, wherein the gate of the MOS transistor is grounded through a pull-down resistor.
8. The buffer power supply of claim 7, wherein the gate of the MOS transistor is connected to the control terminal through a voltage dividing resistor.
9. The buffer power supply of claim 8, wherein the MOS transistor is a P-type MOS transistor.
10. The buffer power supply of claim 9, wherein a parasitic diode is connected in parallel between the drain and source of the MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320156950.8U CN219802150U (en) | 2023-02-08 | 2023-02-08 | Buffer power supply and control circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320156950.8U CN219802150U (en) | 2023-02-08 | 2023-02-08 | Buffer power supply and control circuit thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219802150U true CN219802150U (en) | 2023-10-03 |
Family
ID=88188478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320156950.8U Active CN219802150U (en) | 2023-02-08 | 2023-02-08 | Buffer power supply and control circuit thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219802150U (en) |
-
2023
- 2023-02-08 CN CN202320156950.8U patent/CN219802150U/en active Active
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