CN219802150U - Buffer power supply and control circuit thereof - Google Patents

Abstract

The utility model relates to the field of button battery power supply for Internet of Things equipment. It discloses a buffer power supply and its control circuit, including a power control circuit. The power control circuit includes a power input terminal, a power output terminal and a low-level conduction power supply. The control terminal; the source and drain of the MOS tube are connected in series between the power input terminal and the power output terminal; the gate of the MOS tube is connected to the control terminal, and the source and gate of the MOS tube are connected in parallel. There is a capacitor. This solution uses capacitors to always discharge the battery in a balanced manner, control the rising speed of the output voltage, minimize the heat loss of the internal resistance, and thereby extend the battery life.

Description

A kind of buffer shock power supply and its control circuit

Technical field

The utility model belongs to the field of button battery power supply for Internet of Things equipment, and specifically relates to a buffer power supply and a control circuit thereof.

Background technique

As IoT devices are increasingly widely used, the requirements for miniaturization and standby time of battery products are becoming higher and higher. It has become more important to reduce the power consumption of products and extend their use time (reduce the frequency of battery replacement).

Based on the current situation of button batteries with poor instantaneous discharge capability and large internal resistance, if the battery is directly allowed to output current at its maximum capacity (between the maximum pulse current and short-circuit current), the heat loss (internal resistance loss) of the battery will be greatly increased. .

Utility model content

The utility model provides a buffer power supply and a control circuit thereof to solve the problem of poor instantaneous power supply capability of battery application products.

In order to solve the above technical problems, the technical solutions included in the present utility model and the corresponding beneficial effects of the technical solutions are as follows:

The utility model provides a solution for buffering a power supply control circuit, which includes a power input terminal for connecting a power supply, a power output terminal for external power output, and a control terminal for low-level conduction power supply; the power input terminal The source and drain of the MOS tube are connected in series with the power output terminal; the gate of the MOS tube is connected to the control terminal, and a capacitor is connected in parallel between the source and gate of the MOS tube.

The beneficial effect of the above technical solution is that the traditional power supply control circuit outputs a low level to the gate of the MOS tube through the control terminal, and the positive electrode of the power supply connected to the source of the MOS tube forms a bias voltage between the gate and source of the MOS tube, causing the MOS tube to When it is turned on, the power supply voltage is output to the outside. However, the instantaneous maximum turn-on will have an impact on the power supply and increase the internal resistance loss of the power supply. This solution connects a capacitor in parallel between the gate and source of the MOS tube. When the control terminal outputs a low level, the voltage between the low level of the control terminal and the positive electrode of the power supply will charge the capacitor. During the charging process, the capacitor voltage slowly increases, and the MOS tube gradually It is conductive to prevent the voltage between the gate and source of the MOS tube from suddenly turning on and causing the power supply to directly output at its maximum capacity. The invention uses the capacitor to always discharge the power supply in a balanced manner, controls the rising speed of the output voltage, minimizes the heat loss of the internal resistance, and thereby extends the battery life.

Further, the gate of the MOS tube is connected to ground through a pull-down resistor.

Further, the gate of the MOS tube is connected to the control terminal through a voltage dividing resistor, and the capacitor obtains a suitable voltage division through the voltage dividing resistor to ensure reliable conduction of the MOS tube.

Further, the MOS tube is a P-type MOS tube.

Furthermore, a parasitic diode is connected in parallel between the drain and source of the MOS tube. When a large instantaneous reverse current occurs in the circuit, the reverse current is derived through the parasitic diode to protect the source and drain of the MOS tube. It was broken down and burned, realizing the anti-reflux protection of the MOS tube.

The invention also provides a solution for buffering power supply, including a battery and a power supply control circuit. The power supply control circuit includes a power input terminal connected to the positive electrode of the battery, a power output terminal for outputting power to the outside and a low-level The control terminal of the power supply is turned on; the source and drain of the MOS tube are connected in series between the power input terminal and the power output terminal; the gate of the MOS tube is connected to the control terminal, and the source and drain of the MOS tube There is a capacitor connected in parallel.

The beneficial effects of the above technical solution are: this solution uses capacitors to always discharge the battery in a balanced manner, control the rising speed of the output voltage, minimize the heat loss of the internal resistance, and thereby extend the battery life.

Further, the gate of the MOS tube is connected to ground through a pull-down resistor.

Further, the gate of the MOS tube is connected to the control terminal through a voltage dividing resistor, and the capacitor obtains a suitable voltage division through the voltage dividing resistor to ensure reliable conduction of the MOS tube.

Further, the MOS tube is a P-type MOS tube.

Furthermore, a parasitic diode is connected in parallel between the drain and source of the MOS tube. When a large instantaneous reverse current occurs in the circuit, the reverse current is derived through the parasitic diode to protect the source and drain of the MOS tube. It is not broken down and burned, and the anti-reflux protection of the MOS tube is realized.

Description of the drawings

Figure 1 is a circuit diagram of the buffer power supply control circuit of the present invention.

Detailed ways

The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

Control circuit example:

As shown in Figure 1, the buffer power control circuit diagram includes P-type MOS tube Q1, pull-down resistor R1, voltage dividing resistor R2, and capacitor C1; source 2 of P-type MOS tube Q1 is connected to the signal input terminal Vin, and P-type MOS tube The drain 3 of Q1 is connected to the signal output terminal Vout, and a parasitic diode is connected in parallel between the source and drain of the P-type MOS transistor Q1; the gate 1 of the P-type MOS transistor Q1 is connected to the first end of the pull-down resistor R1, and the pull-down resistor The second end of R1 is connected to ground; the gate 1 of the P-type MOS tube Q1 is connected to the first end of the voltage dividing resistor R2, and the second end of the voltage dividing resistor R2 is connected to the control signal CTRL; the source of the P-type MOS tube Q1 is connected to the capacitor C2 The first end of the capacitor C1 is connected to the first end of the voltage dividing resistor R2.

The principle of the buffer power supply control circuit of this utility model is:

The power supply of Vout is controlled by the CTRL signal. When the CTRL signal is high level, the MOS tube is not conducting, and the Vout voltage is 0V at this time;

When the CTRL signal changes from high level to low level, the voltage difference across the capacitor C1 cannot change suddenly. At this time, the MOS tube is also non-conductive. As the capacitor charges, the voltage difference across the capacitor C1 gradually increases. During this process The middle MOS tube begins to conduct and the conduction internal resistance gradually decreases, charging the rear circuit capacitor with a small current, and the voltage of Vout gradually increases during the conduction period.

Comparing the impact current effect diagram before improvement and the impact current effect diagram after improvement according to the present invention, it can be seen that the highest impact current before improvement is about 940mA, the maximum impact current after improvement is about 172mA, and the current after improvement is reduced to about 1/6;

Capacitor charging Q=CU=I*T; from the initial state to full power, the charging amount is the same, the charging current is reduced to 1/6, and the time increases accordingly by 6 times; where, C is the capacitor capacity; U is the capacitor voltage difference (capacitor Fully charged voltage - initial voltage); I is the average charging current; T is the charging time.

According to the heating power of the resistor, W0=I ² RT; it can be concluded that W1=(I/6)×(I/6)×R×(6T)=W0/6, and the calorific value is reduced to P/6, that is, the calorific value is reduced. It is 1/6 of the value before improvement; among them, W0 is the internal resistance calorific value before improvement; W1 is the internal resistance calorific value after improvement.

Therefore, this solution uses capacitors to always discharge the battery in a balanced manner, control the rising speed of the output voltage, minimize the heat loss of the internal resistance, and thereby extend the battery life.

Buffered power supply example:

The hardware structure and working principle of a buffer power supply of the present invention have been clearly introduced in the embodiment of the control circuit and will not be described again here.

The specific embodiments related to the present utility model are given above, but the utility model is not limited to the described embodiments. Under the ideas given by the present utility model, the technical means in the above embodiments are transformed, replaced, and modified in ways that are easy for those skilled in the art to think of, and have the same effect as the corresponding technical means in the present utility model. They are basically the same and achieve basically the same purpose of the utility model. The technical solution formed in this way is formed by fine-tuning the above embodiment. This technical solution still falls within the protection scope of the present utility model.

Claims (10)

1. The buffer power supply control circuit is characterized by comprising a power supply input end, a power supply output end and a control end, wherein the power supply input end is used for connecting a power supply, the power supply output end is used for outputting a power supply to the outside, and the control end is used for conducting the power supply at a low level; a source electrode and a drain electrode of the MOS tube are connected in series between the power input end and the power output end; and a grid electrode of the MOS tube is connected with the control end, and a capacitor is connected in parallel between a source electrode and the grid electrode of the MOS tube.

2. The buffer power supply control circuit of claim 1, wherein the gate of the MOS transistor is grounded through a pull-down resistor.

3. The buffer power supply control circuit according to claim 2, wherein the gate of the MOS transistor is connected to the control terminal through a voltage dividing resistor.

4. The buffer power control circuit of claim 3, wherein the MOS transistor is a P-type MOS transistor.

5. The buffer power control circuit of claim 4, wherein a parasitic diode is connected in parallel between the drain and source of the MOS transistor.

6. The buffer power supply is characterized by comprising a battery and a power supply control circuit, wherein the power supply control circuit comprises a power supply input end connected with the positive electrode of the battery, a power supply output end for outputting a power supply to the outside and a control end for conducting the power supply at a low level; a source electrode and a drain electrode of the MOS tube are connected in series between the power input end and the power output end; and a grid electrode of the MOS tube is connected with the control end, and a capacitor is connected in parallel between a source electrode and the grid electrode of the MOS tube.

7. The buffer power supply of claim 6, wherein the gate of the MOS transistor is grounded through a pull-down resistor.

8. The buffer power supply of claim 7, wherein the gate of the MOS transistor is connected to the control terminal through a voltage dividing resistor.

9. The buffer power supply of claim 8, wherein the MOS transistor is a P-type MOS transistor.

10. The buffer power supply of claim 9, wherein a parasitic diode is connected in parallel between the drain and source of the MOS transistor.