CN107527923B - Array substrate and preparation method thereof, display panel - Google Patents
Array substrate and preparation method thereof, display panel Download PDFInfo
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- CN107527923B CN107527923B CN201710713452.8A CN201710713452A CN107527923B CN 107527923 B CN107527923 B CN 107527923B CN 201710713452 A CN201710713452 A CN 201710713452A CN 107527923 B CN107527923 B CN 107527923B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
- G02F1/133784—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Abstract
The invention discloses a kind of array substrates and preparation method thereof, display panel.Preparation method includes: marked region the first indicia patterns of formation in non-display area, and forms the first insulating layer of covering non-display area；Semiconductor pattern is formed in non-display area, semiconductor pattern is used to reduce the segment difference between marked region and adjacent area；The second insulating layer for forming covering non-display area etches the second insulating layer of marked region by patterning processes.By forming semiconductor pattern in non-display area, and the second insulating layer of marked region is etched, reduces the segment difference between marked region and adjacent area, improve damage of the segment difference to friction roller flannelette fiber, improve friction matching yield.The embodiment of the present invention also proposed a kind of array substrate being prepared using above-mentioned preparation method, while also proposed a kind of display panel including the array substrate.
Description
Technical field
The present invention relates to technical field of liquid crystal display, and in particular to a kind of array substrate and preparation method thereof, display panel.
Background technique
Liquid crystal display panel (liquid crystal displays, LCDs) includes array substrate, color membrane substrates and therebetween
Liquid crystal layer.It is respectively coated alignment film in array substrate and color membrane substrates, after carrying out orientation processing to alignment film, by array base
Plate and color membrane substrates form liquid crystal display panel to box.Existing alignment technique has non-model control (Non-Rubbing) type and friction
(Rubbing) type two major classes.Non-model control type alignment technique includes light orientation and ion beam orientation etc..Although light orientation and ion beam
Alignment technique has preferable orientation effect, but production efficiency is low, at high cost, less to apply in the field LCD.Friction-type orientation
It is the orientation mechanical friction for carrying out contact with flannelette idler wheel in orientation film surface, energy provided by friction matching film surface makes
The strand of alignment film is aligned because of extension, to control LCD alignment arrangement.Friction-type orientation because its fraction time is short,
Production is high and is widely applied.
In LCD panel processing procedure, there are some marked regions on frictional direction, when the label being located on frictional direction
It, can be because of the pressing-in force of flannelette surface capillary fibers when carrying out friction matching when the segment difference of region and adjacent area is more than threshold value
Degree changes with the contact strength of alignment film, damages the flannelette fiber of rub running roller.After flannelette fibre damage, cause to rub
Appearance rubs bad when roller carries out friction matching to viewing area, causes liquid crystal deflection disorder.In black state, liquid crystal occurs inclined
Turn, the black line formed on frictional direction is bad.
Summary of the invention
The embodiment of the present invention is the technical problem to be solved is that, provide a kind of array substrate and preparation method thereof, display surface
Plate, the defect of existing damage friction roller flannelette fiber when solving existing friction matching.
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of preparation method of array substrate, array bases
Plate includes viewing area and non-display area, which includes:
The first indicia patterns are formed in the marked region of non-display area, and form the first insulating layer of covering non-display area；
The semiconductor pattern for reducing the segment difference between marked region and adjacent area is formed in non-display area；
The second insulating layer for forming covering non-display area etches the second insulating layer of marked region by patterning processes.
Optionally, first indicia patterns and the gate electrode same layer for the thin film transistor (TFT) for being located at viewing area are arranged, and lead to
A patterning processes are crossed to be formed.
Optionally, the active layer same layer of the semiconductor pattern and the thin film transistor (TFT) for being located at viewing area is arranged, and passes through
One time patterning processes are formed.
Optionally, the semiconductor pattern includes the first semiconductor pattern in the marked region formation of non-display area.
Optionally, the second insulating layer that marked region is etched by patterning processes, comprising: etched by patterning processes
The second insulating layer of marked region makes the second insulating layer of marked region and the second insulating layer flush of adjacent area, or
The second insulating layer for completely removing marked region exposes the first semiconductor pattern of marked region.
Optionally, the semiconductor pattern includes the second semiconductor figure that the non-display area except marked region is formed
Case.
Optionally, preparation method further includes forming the second indicia patterns, second indicia patterns and position in marked region
In the source-drain electrode same layer setting of the thin film transistor (TFT) of viewing area, and formed by a patterning processes.
Optionally, the second insulating layer that marked region is etched by patterning processes includes: to be etched by patterning processes
The second insulating layer of marked region makes the second insulating layer of marked region and the second insulating layer flush of adjacent area, or
The second insulating layer for completely removing marked region exposes the second indicia patterns of marked region.
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of array substrate, the array substrate use with
The upper preparation method is prepared.
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of display panels, including array base above-mentioned
Plate.
The embodiment of the invention provides a kind of array substrates and preparation method thereof, display panel, by non-display area shape
At semiconductor pattern, and using the second insulating layer of patterning processes etching marked region, marked region and adjacent area are reduced
Between segment difference.Damage so as to improve segment difference to friction roller flannelette fiber reduces black on frictional direction under black state
Line is bad, improves friction matching yield.Meanwhile the segment difference between marked region and adjacent area reduces, and is conducive to alignment liquid
Uniformly diffusion and the uniform diffusion of liquid crystal play certain prevention to the bad equal displays of thus caused LCD alignment extremely and make
With improving picture quality.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 a and 1b are respectively illustrated to be shown positioned at the marked region 1 of array substrate non-display area and the structure of marked region 2
It is intended to；
Fig. 2 is the preparation method flow chart of array substrate of the embodiment of the present invention；
Fig. 3 is to form the structural schematic diagram after the first insulating layer in first embodiment of the invention；
Fig. 4 is to form the structural schematic diagram after the first semiconductor pattern in first embodiment of the invention；
Fig. 5 is that the structural schematic diagram after source electrode and drain electrode is formed in first embodiment of the invention；
Fig. 6 a and 6b are the structural schematic diagram after forming second insulating layer in first embodiment of the invention and etching；
Fig. 7 is to form the structural schematic diagram after the second semiconductor pattern in second embodiment of the invention；
Fig. 8 is to form the structural schematic diagram after the second indicia patterns in second embodiment of the invention；
Fig. 9 a and 9b are the structural schematic diagram after forming second insulating layer in second embodiment of the invention and etching.
Description of symbols:
1-marked region；2-marked regions；11-gate electrodes；
12-the first indicia patterns；21-the first insulating layer；31-active layers；
32-the first semiconductor pattern；33-the second semiconductor pattern；41-source electrodes；
42-drain electrodes；43-the second indicia patterns；51-second insulating layers；
60-marked regions.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Through present inventor the study found that in LCD panel processing procedure, there are signal wire cablings, array substrate for non-display area
The indispensable pictorial symbolization that test pattern, liquid crystal display panel test pattern and the contraposition of each mask plate and exposure machine need.In general,
The label of non-display area can be moved on non-model control direction in the design, it is biggish to avoid occurring segment difference on frictional direction
Label.But for some special labels, for example, alignment mark needed for exposure machine, label for fixing glass position etc.,
It can not then be moved on non-model control direction.It is undesirable hidden that these labels for being located on frictional direction have buried friction matching
Suffer from.
Fig. 1 a shows the structural schematic diagram of the marked region 1 of the non-display area on frictional direction.Marked region 1 is under
It upwards successively include the first indicia patterns 12, the first insulating layer 21 and second insulating layer 51 in substrate.It can from Fig. 1 a
To find out, due to the presence of the first indicia patterns 12, lead between marked region 1 and adjacent area that there are segment difference H1, segment difference H1
The about thickness of the first indicia patterns 12.When segment difference H1 is more than threshold value, when carrying out friction matching, segment difference H1 can damage friction
The flannelette fiber of roller, and then cause viewing area friction matching bad, cause liquid crystal deflection disorder.
Fig. 1 b shows the structural schematic diagram of the marked region 2 of the non-display area on frictional direction.Marked region 2 is under
It upwards successively include the first indicia patterns 12, the first insulating layer 21, the second indicia patterns 43 and the second insulation in substrate
Layer 51.It can be seen that the presence due to the first indicia patterns 12 and the second indicia patterns 43 from Fig. 1 b, lead to marked region 2
There are thickness H11 and the second indicia patterns 43 that segment difference H2, segment difference H2 are about the first indicia patterns 12 between adjacent area
The sum of thickness H14, i.e. segment difference H2 are about H11+H14.When segment difference H2 is more than threshold value, when carrying out friction matching, segment difference H2 meeting
The flannelette fiber of rub running roller is damaged, and then causes viewing area friction matching bad, causes liquid crystal deflection disorder.
In order to overcome in existing array substrate processing procedure, segment difference is excessive between marked region and adjacent area, is easy to damage and rubs
The flannelette fiber for wiping roller, causes to occur friction when carrying out friction matching to viewing area to cause liquid crystal deflection disorderly with as bad
Random technical problem, the embodiment of the invention provides a kind of preparation methods of array substrate.
Fig. 2 is the preparation method flow chart of array substrate of the embodiment of the present invention, and array substrate includes viewing area and non-display
Area, this method comprises:
S1: the first indicia patterns are formed in the marked region of non-display area, and form the first insulation of covering non-display area
Layer；
S2: the semiconductor pattern for reducing the segment difference between marked region and adjacent area is formed in non-display area；
S3: forming the second insulating layer of covering non-display area, and the second insulating layer of marked region is etched by patterning processes.
Wherein, the first indicia patterns can be arranged with the gate electrode same layer for the thin film transistor (TFT) for being located at viewing area, and pass through
One time patterning processes are formed；
Semiconductor pattern can be arranged with the active layer same layer for the thin film transistor (TFT) for being located at viewing area, and pass through a composition
Technique is formed.
In one embodiment, semiconductor pattern includes the first semiconductor figure in the marked region formation of non-display area
Case.
The second insulating layer that marked region is etched by patterning processes, may include: to etch mark zone by patterning processes
The second insulating layer in domain makes the second insulating layer of marked region and the second insulating layer flush of adjacent area, or goes completely
Except the second insulating layer of marked region, the first semiconductor pattern of marked region is exposed.
In another embodiment, semiconductor pattern includes the second half leading of being formed of non-display area except marked region
Body pattern.
Wherein, further include forming the second indicia patterns in marked region, second indicia patterns can be located at viewing area
The source-drain electrode same layer of thin film transistor (TFT) is arranged, and is formed by a patterning processes.
It include: to etch the of marked region by patterning processes by the second insulating layer that patterning processes etch marked region
Two insulating layers make the second insulating layer of marked region and the second insulating layer flush of adjacent area, or completely remove label
The second insulating layer in region exposes the second indicia patterns of marked region.
The preparation method of array substrate provided in an embodiment of the present invention, by forming semiconductor pattern in non-display area, and
Using the second insulating layer of patterning processes etching marked region, the segment difference between marked region and adjacent area is reduced.To
Damage of the segment difference to friction roller flannelette fiber is improved, the black line reduced under black state on frictional direction is bad, improves and rubs
Wipe orientation yield.Meanwhile segment difference between marked region and adjacent area reduces, and is conducive to alignment liquid and uniformly spreads and liquid crystal
Uniformly diffusion plays certain prevention effect to the bad equal displays of thus caused LCD alignment extremely, improves picture product
Matter.
In the embodiment of the present invention, the active layer same layer of semiconductor pattern and thin film transistor (TFT) is arranged and passes through a composition
Technique is formed, to will not increase the number of mask of array substrate, is with a wide range of applications.
The technical solution of the embodiment of the present invention will be discussed in detail by the preparation process of array substrate below.Wherein, implement
Described " patterning processes " include the processing such as coating photoresist, mask exposure, development, etching, stripping photoresist in example, are existing
Mature preparation process.The already known processes such as sputtering, vapor deposition, chemical vapor deposition can be used in deposition, and known painting can be used in coating
Coating process, etching can be used known method, do not do specific restriction herein.
In the present embodiment, " adjacent area " refers to, positioned at non-display area and the region adjacent with marked region.
First embodiment:
Fig. 3~Fig. 6 is the schematic diagram that first embodiment of the invention prepares array substrate.Left side of dotted line is illustrated as showing in figure
Area, right side of dotted line are illustrated as non-display area.
First time patterning processes: the first indicia patterns are formed in the marked region of non-display area, and it is non-display to form covering
First insulating layer in area, it is preferable that the gate electrode same layer of the thin film transistor (TFT) of the first indicia patterns and viewing area is arranged, specific to wrap
It includes: depositing grid metal film in substrate, a layer photoresist is coated in grid metal film；Using monotone mask plate to photoetching
Glue is exposed and develops, and forms unexposed area in gate electrode, grid line and the first indicia patterns position, retains photoresist, In
Other positions form complete exposure area, and unglazed photoresist exposes grid metal film；To the grid metal film of complete exposure area
Remaining photoresist is performed etching and removed, gate electrode 11, grid line (not shown) and the first indicia patterns 12, grid electricity are formed
Pole 11 is located at viewing area, and the first indicia patterns 12 are located at the marked region 60 of non-display area；In the substrate for forming above-mentioned pattern
The first insulating layer 21 is deposited, as shown in Figure 3.Wherein, substrate can use substrate of glass or quartz substrate, and grid metal film can be with
Using one of metals such as platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminium Al, tantalum Ta, titanium Ti, tungsten W or a variety of, grid are exhausted
Edge film can be using the composite layer of silicon nitride SiNx, silicon oxide sio x or SiNx/SiOx.
Second of patterning processes: the first semiconductor pattern is formed in the marked region of non-display area, it is preferable that the first half lead
The setting of the active layer same layer of body pattern and the thin film transistor (TFT) of viewing area, specifically includes: depositing on the first insulating layer 21 active
Film coats a layer photoresist on active film；Photoresist is exposed and is developed using monotone mask plate, active
Layer and the first semiconductor pattern position form unexposed area, retain photoresist, form complete exposure area, nothing in other positions
Photoresist exposes active film；Remaining photoresist is performed etching and removed to the active film of complete exposure area, is formed
Active layer 31 and the first semiconductor pattern 32, active layer 31 are located at viewing area, and the first semiconductor pattern 32 is located at non-display area
Marked region 60, as shown in Figure 4.Herein, the first semiconductor pattern 32 is for reducing between marked region and adjacent area
Segment difference.Wherein, active film can be amorphous silicon, polysilicon or microcrystalline silicon materials, be also possible to metal oxide materials, metal
Oxide material can be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or indium tin zinc oxide
(Indium Tin Zinc Oxide, ITZO).
Third time patterning processes: source-drain electrode is formed, is specifically included: depositing source/drain metallic film, In on active layer
A layer photoresist is coated on source/drain metallic film；Photoresist is exposed and is developed using monotone mask plate, in source electricity
Pole, drain electrode and linear position data form unexposed area, retain photoresist, form complete exposure area, nothing in other positions
Photoresist exposes source/drain metallic film；The source/drain metallic film of complete exposure area is performed etching and removed remaining
Photoresist forms source electrode 41, drain electrode 42 and data line (not shown), as shown in Figure 5.Wherein, source/drain metallic film
One of metals such as platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminium Al, tantalum Ta, titanium Ti, tungsten W or a variety of can be used.
4th patterning processes: the second insulating layer of covering non-display area is formed, etches marked region by patterning processes
Second insulating layer.It specifically includes: depositing insulation film in the substrate for forming aforementioned pattern, and coat one on insulation film
Layer photoresist；Photoresist is exposed and is developed using monotone mask plate, crosses hole site and non-display area in viewing area
Marked region formed complete exposure area, unglazed photoresist, other positions formed unexposed area, retain photoresist；Etching
The insulation film for crossing hole site for falling viewing area forms second insulating layer, and the second insulation to the marked region of non-display area
Layer performs etching.When being performed etching to the second insulating layer of marked region, it may appear that two different results:
The first result:, can be with by etching the second insulating layer of marked region when second insulating layer thickness is sufficiently thick
So that the second insulating layer of marked region and the second insulating layer flush of adjacent area, without exposing marked region
First semiconductor pattern 32, as shown in Figure 6 a.Since the insulation performance of the first semiconductor pattern 32 is relatively good, so, although mark
Remember that the second insulating layer 51 in region 60 is relatively thin, but not influences the insulation performance of array substrate.
Second of result:, can be with by etching the second insulating layer of marked region when second insulating layer thickness is less thick
The second insulating layer of marked region is completely removed, to expose the first semiconductor pattern 32 of marked region, as shown in Figure 6 b.
Equally, the first semiconductor pattern 32 can guarantee the insulation performance of non-display area.
In the 4th patterning processes, is performed etching by the second insulating layer to marked region, reduce marked region
Segment difference between adjacent area, in Fig. 6 a, the segment difference between marked region 60 and adjacent area is reduced to 0, it is clear that is less than
Segment difference H1 in Fig. 1 a.In figure 6b, although exposing the first semiconductor pattern 32, in common processing procedure, the first half are led
The thickness H13 of body pattern 32 is less than the thickness H12 (as shown in Figure 1a) of second insulating layer, therefore, the marked region in Fig. 6 b
Segment difference H1 ' between 60 and adjacent area is less than the segment difference H1 in Fig. 1 a.
In the embodiment of the present invention, the first semiconductor pattern is formed by the marked region in non-display area, and etch label
The second insulating layer in region, so that segment difference between marked region and adjacent area is 0 or reduces, so as to improve segment difference to rubbing
The damage of idler wheel flannelette fiber is wiped, the black line reduced under black state on frictional direction is bad, improves friction matching yield.Together
When, segment difference between marked region and adjacent area is 0 or reduces, and is conducive to alignment liquid and uniformly spreads and the uniform expansion of liquid crystal
It dissipates, certain prevention effect is played to the bad equal displays of thus caused LCD alignment extremely, improves picture quality.
The array substrate of preparation of the embodiment of the present invention, comprising:
Gate electrode 11 in substrate and the first indicia patterns 12 are set, and the first indicia patterns 12 are located at the mark of non-display area
Remember region 60；
First insulating layer 21 of covering grid electrode 11 and the first indicia patterns 12；
Active layer 31 on first insulating layer 21 and the first semiconductor pattern 32 positioned at marked region are set；
On active layer 31 source electrode 41 and drain electrode 42 are set；
Second insulating layer 51 in source electrode 41 and drain electrode 42 is set, and second insulating layer 51 covers the first semiconductor figure
Case 32 exposes the first semiconductor pattern 32.
Second embodiment:
First time patterning processes form the first indicia patterns in the marked region of non-display area, and it is non-display to form covering
First insulating layer in area, it is preferable that the gate electrode same layer of the thin film transistor (TFT) of the first indicia patterns and viewing area is arranged.Such as Fig. 3
It is shown.The first time patterning processes of the present embodiment and the first time patterning processes of first embodiment are identical, and which is not described herein again.
Second of patterning processes, the non-display area except marked region form the second semiconductor pattern, it is preferable that second
The setting of the active layer same layer of semiconductor pattern and the thin film transistor (TFT) of viewing area, specifically includes: depositing on the first insulating layer 21
Active film coats a layer photoresist on active film；Photoresist is exposed and is developed using monotone mask plate, In
Active layer, the second semiconductor pattern position form unexposed area, retain photoresist, form complete exposure region in other positions
Domain, unglazed photoresist expose active film；The active film of complete exposure area is performed etching and removes remaining photoetching
Glue forms the second semiconductor pattern 33 of active layer 31 and the non-display area except marked region, as shown in Figure 7.Wherein,
Active film can be amorphous silicon, polysilicon or microcrystalline silicon materials, be also possible to metal oxide materials, metal oxide materials
It can be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or indium tin zinc oxide (Indium Tin
Zinc Oxide, ITZO).
Third time patterning processes: source electrode, drain electrode and the second indicia patterns positioned at marked region are formed.Specific packet
It includes: depositing source/drain metallic film in the substrate for forming aforementioned pattern, a layer photoresist is coated on source/drain metallic film；It adopts
Photoresist is exposed and is developed with monotone mask plate, in source electrode, drain electrode, data line and the second indicia patterns position
Unexposed area is formed, photoresist is retained, forms complete exposure area in other positions, unglazed photoresist exposes source/drain metal
Film；Remaining photoresist is performed etching and removed to the source/drain metallic film of complete exposure area, forms source electrode 41, leakage
Electrode 42, data line (not shown) and the second indicia patterns 43.As shown in Figure 8.Wherein, source/drain metallic film can be adopted
With one of metals such as platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminium Al, tantalum Ta, titanium Ti, tungsten W or a variety of.
4th patterning processes: the second insulating layer of covering non-display area is formed, etches marked region by patterning processes
Second insulating layer.It specifically includes: depositing insulation film in the substrate for forming aforementioned pattern, and coat one on insulation film
Layer photoresist；Photoresist is exposed and is developed using monotone mask plate, crosses hole site and non-display area in viewing area
Marked region formed complete exposure area, unglazed photoresist, other positions formed unexposed area, retain photoresist；Etching
The insulation film for crossing hole site for falling viewing area forms second insulating layer, and the second insulation to the marked region of non-display area
Layer performs etching.When being performed etching to the second insulating layer of marked region, it may appear that two different results:
The first result:, can be with by etching the second insulating layer of marked region when second insulating layer thickness is sufficiently thick
So that the second insulating layer of marked region and the second insulating layer flush of adjacent area, without exposing marked region
First indicia patterns 43, as illustrated in fig. 9.Herein, the second semiconductor pattern 33 being arranged in adjacent area, increases label
The thickness of the second insulating layer of region and adjacent area, so will not influence the insulation performance of array substrate.
Second of result:, can be with by etching the second insulating layer of marked region when second insulating layer thickness is less thick
The second insulating layer of marked region is completely removed, to expose the second indicia patterns 43 of marked region, as shown in figure 9b.Together
Sample, the second semiconductor pattern 33 of adjacent area setting, ensure that the insulation performance of non-display area.
In the 4th patterning processes, is performed etching by the second insulating layer to marked region, reduce marked region
Segment difference between adjacent area, in fig. 9 a, the segment difference between marked region 60 and adjacent area are reduced to 0, it is clear that are less than
Segment difference H2 in Fig. 1 b.In figure 9b, although exposing the second indicia patterns 43, the second semiconductor figure of adjacent area setting
Case 33 improves the height of adjacent area, so that the segment difference between marked region and adjacent area is approximately equal to the first label figure
Then the sum of the thickness of case 12 and the thickness of the second indicia patterns 43 subtract the thickness of the second semiconductor pattern, mark zone in Fig. 9 b
Segment difference between domain and adjacent area is about H11+H14-H13, it is clear that the segment difference H2 ' in Fig. 9 b is less than the segment difference H2 in Fig. 1 b.
In the embodiment of the present invention, the second semiconductor pattern being arranged by adjacent area, and etch the second of marked region
Insulating layer, so that the segment difference between marked region and adjacent area is 0 or reduces, so as to improve segment difference to friction roller flannelette
The damage of fiber, the black line reduced under black state on frictional direction is bad, improves friction matching yield.Meanwhile marked region
Segment difference between adjacent area is 0 or reduces, and is conducive to alignment liquid and uniformly spreads and the uniform diffusion of liquid crystal, to thus causing
The bad equal displays of LCD alignment play certain prevention effect extremely, improve picture quality.
The array substrate of preparation of the embodiment of the present invention, comprising:
Gate electrode 11 in substrate and the first indicia patterns 12 are set, and the first indicia patterns 12 are located at the mark of non-display area
Remember region 60；
First insulating layer 21 of covering grid electrode 11 and the first indicia patterns 12；It is arranged in active on the first insulating layer 21
Second semiconductor pattern 33 of layer 31 and the non-display area except marked region；
Second indicia patterns 43 of marked region are set；
Second insulating layer 51 in source electrode 41 and drain electrode 42 is set, and second insulating layer 51 covers the second indicia patterns
43 or expose the second indicia patterns 43.
The embodiment of the present invention is equally applicable to form the array substrate of horizontal electric field mode, when forming horizontal component of electric field, In
Public electrode pattern is additionally provided with below first indicia patterns.In general, the thickness of public electrode pattern is at 400-500 angstroms, on business
The thickness of common electrode pattern is smaller, therefore can reduce marked region and adjacent area using method same as the previously described embodiments
Between segment difference.
In practical applications, the indicia patterns of non-display area can also be the mistake sectional hole patterns in second insulating layer, base
In the inventive concept of previous embodiment, semiconductor pattern can be set in the lower section for crossing sectional hole patterns, to reduce sectional hole patterns
Depth improves damage of the segment difference to friction roller flannelette fiber so that the segment difference crossed at sectional hole patterns reduces.
3rd embodiment:
Inventive concept based on previous embodiment, the embodiment of the invention also provides a kind of array substrate, the array substrates
It is prepared using the preparation method of previous embodiment.
Fourth embodiment:
Inventive concept based on previous embodiment, the embodiment of the invention also provides a kind of display panel, the display panels
Including the array substrate using previous embodiment.Display panel can be with are as follows: mobile phone, tablet computer, television set, display, notes
Any products or components having a display function such as this computer, Digital Frame, navigator.
In the description of the embodiment of the present invention, it is to be understood that term " middle part ", "upper", "lower", "front", "rear",
The orientation or positional relationship of the instructions such as "vertical", "horizontal", "top", "bottom" "inner", "outside" be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In the description of the embodiment of the present invention, it should be noted that unless otherwise clearly defined and limited, term " peace
Dress ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integrally
Connection；It can be mechanical connection, be also possible to be electrically connected；Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection inside two elements.For the ordinary skill in the art, above-mentioned art can be understood with concrete condition
The concrete meaning of language in the present invention.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (9)
1. a kind of preparation method of array substrate, array substrate include viewing area and non-display area characterized by comprising
The first indicia patterns are formed in the marked region of non-display area, and form the first insulating layer of covering non-display area；
The semiconductor pattern for reducing the segment difference between marked region and adjacent area, the semiconductor are formed in non-display area
Pattern includes the second semiconductor pattern that the non-display area except marked region is formed；
The second indicia patterns are formed in the marked region of non-display area；
The second insulating layer for forming covering non-display area etches the second insulating layer of marked region by patterning processes.
2. preparation method according to claim 1, which is characterized in that first indicia patterns be located at viewing area it is thin
The gate electrode same layer of film transistor is arranged, and is formed by a patterning processes.
3. preparation method according to claim 1, which is characterized in that the semiconductor pattern and the film for being located at viewing area
The active layer same layer of transistor is arranged, and is formed by a patterning processes.
4. preparation method described in any one of -3 according to claim 1, which is characterized in that the semiconductor pattern is included in
The first semiconductor pattern that the marked region of non-display area is formed.
5. the preparation method according to claim 4, which is characterized in that described to etch the of marked region by patterning processes
Two insulating layers, comprising: the second insulating layer that marked region is etched by patterning processes makes the second insulating layer of marked region and phase
The second insulating layer flush in neighbouring region, or the second insulating layer of marked region is completely removed, expose the of marked region
Semiconductor pattern.
6. preparation method according to claim 1, which is characterized in that second indicia patterns be located at viewing area it is thin
The source-drain electrode same layer of film transistor is arranged, and is formed by a patterning processes.
7. preparation method according to claim 6, which is characterized in that described to etch the of marked region by patterning processes
Two insulating layers include: the second insulating layer that marked region is etched by patterning processes, make the second insulating layer of marked region and phase
The second insulating layer flush in neighbouring region, or the second insulating layer of marked region is completely removed, expose the of marked region
Two indicia patterns.
8. a kind of array substrate, which is characterized in that prepared using preparation method described in any one of claim 1-7.
9. a kind of display panel, which is characterized in that including array substrate according to any one of claims 8.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474438A (en) * | 2013-09-26 | 2013-12-25 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and liquid crystal display panel |
| CN103941497A (en) * | 2013-06-28 | 2014-07-23 | 上海中航光电子有限公司 | Thin film transistor array substrate, manufacturing method and liquid crystal display panel |
| CN104392920A (en) * | 2014-10-24 | 2015-03-04 | 合肥京东方光电科技有限公司 | TFT (Thin Film Transistor) array substrate, manufacturing method thereof, and display device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103941497A (en) * | 2013-06-28 | 2014-07-23 | 上海中航光电子有限公司 | Thin film transistor array substrate, manufacturing method and liquid crystal display panel |
| CN103474438A (en) * | 2013-09-26 | 2013-12-25 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and liquid crystal display panel |
| CN104392920A (en) * | 2014-10-24 | 2015-03-04 | 合肥京东方光电科技有限公司 | TFT (Thin Film Transistor) array substrate, manufacturing method thereof, and display device |
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