CN107517049A - A kind of control method, system and the FPGA of multichannel PWM outputs - Google Patents
A kind of control method, system and the FPGA of multichannel PWM outputs Download PDFInfo
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- CN107517049A CN107517049A CN201710791601.2A CN201710791601A CN107517049A CN 107517049 A CN107517049 A CN 107517049A CN 201710791601 A CN201710791601 A CN 201710791601A CN 107517049 A CN107517049 A CN 107517049A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Abstract
The invention discloses control method, system and the FPGA of a kind of multichannel PWM outputs, timing at the time of including where the rising edge of the pulse in each cycle of default first reference clock, after timing time reaches default first dead time, before at the time of where the trailing edge of pulse in each cycle of first reference clock, N the first pulses of road are generated, to ultimately generate the pwm signal of N roads first；Timing at the time of where the rising edge of the pulse in each cycle of default second reference clock, after timing time reaches default second dead time, before at the time of where the trailing edge of pulse in each cycle of second reference clock, generate N the second pulses of road, to generate the pwm signal of N roads second, the phase of the second reference clock and the opposite in phase of the first reference clock.Present invention, avoiding the generation of straight-through phenomenon, ensure that the accuracy of dead time, makes multichannel PWM outputs reliable and stable.
Description
Technical field
The present invention relates to multichannel export technique field, the control method exported more particularly to a kind of multichannel PWM, is
System and FPGA.
Background technology
With the development of multichannel PWM (Pulse Width Modulation, pulse width modulation) technology, multichannel
Application of the PWM control systems in automated system is more and more extensive.Fig. 1 is refer to, Fig. 1 is a kind of multichannel in the prior art
The circuit diagram of the control circuit of PWM outputs.The control circuit includes interlock logic circuit and dead-zone circuit, interlock logic circuit
Two inputs of two output ends and dead-zone circuit connect one to one, and interlock logic circuit for being by the dutycycle of input
50% pwm signal is changed into the pwm signal of two-way opposite in phase.When dead-zone circuit is used for the charging according to its resistance-capacitance
Between there is dead band when the pwm signal of two-way opposite in phase is exported accordingly from two output ends, it is therefore prevented that the hair of straight-through phenomenon
It is raw.
But because the resistance in dead-zone circuit and the precision of electric capacity are low, heat endurance is poor, easy to aging, so can not protect
The accuracy of dead time is demonstrate,proved, and temperature drift phenomenon easily occurs in the output signal of dead-zone circuit, may result in straight-through phenomenon
Occur, so that control circuit is unstable, even can not normal work.
Therefore, how to provide a kind of scheme for solving above-mentioned technical problem is that those skilled in the art needs to solve at present
The problem of.
The content of the invention
It is an object of the invention to provide control method, system and the FPGA of a kind of multichannel PWM outputs, avoids straight-through existing
The generation of elephant, it ensure that the accuracy of dead time so that multichannel PWM outputs are reliable and stable.
In order to solve the above technical problems, the invention provides a kind of control method of multichannel PWM outputs, including：
Timing at the time of where the rising edge of the pulse in each cycle of default first reference clock, works as meter
When the time reach default first dead time after, where the trailing edge of the pulse in each cycle of first reference clock
At the time of before, generate N the first pulses of road, to ultimately generate N roads the first pulse width modulation (PWM) signal, N is more than 1
Integer；
Timing at the time of where the rising edge of the pulse in each cycle of default second reference clock, works as meter
When the time reach default second dead time after, where the trailing edge of the pulse in each cycle of second reference clock
At the time of before, generate N the second pulses of road, to ultimately generate the pwm signal of N roads second, wherein, second reference clock
Phase and the opposite in phase of first reference clock.
Preferably, second dead time is equal to first dead time.
Preferably, the preset procedures of first dead time and second dead time are specially：
The pulse number of the system clock according to corresponding to the predetermined frequency dead time of system clock, during the dead band
Between be first dead time or second dead time；
Then the timing time reaches default first dead time and the timing time reaches default second dead time
Process be specially：
The pulse number of the accumulative system clock reaches default pulse number.
Preferably, the clock that the system clock to external clock obtain after M frequencys multiplication specifically by phaselocked loop, its
In, M is the integer more than 1.
Preferably, this method also includes：
In advance first reference clock disappear and tremble processing.
Preferably, this method also includes：
When there are abnormal conditions, first reference clock and second reference clock are resetted.
In order to solve the above technical problems, present invention also offers a kind of control system of multichannel PWM outputs, including：
First pulse generation module, for the rising edge institute from the pulse in each cycle of default first reference clock
At the time of start timing, after timing time reaches default first dead time, each week of first reference clock
Before at the time of where the trailing edge of interim pulse, N the first pulses of road are generated, to ultimately generate the pulse width of N roads first
Modulation (PWM) signal, N are the integer more than 1；
Second pulse generation module, for the rising edge institute from the pulse in each cycle of default second reference clock
At the time of start timing, after timing time reaches default second dead time, each week of second reference clock
Before at the time of where the trailing edge of interim pulse, N the second pulses of road are generated, to ultimately generate the pwm signal of N roads second,
Wherein, the phase of second reference clock and the opposite in phase of first reference clock.
Preferably, the system also includes：
Disappear and tremble module, processing is trembled for by first reference clock disappear in advance.
Preferably, the system also includes：
Reseting module, for when there are abnormal conditions, resetting first reference clock and second reference clock.
In order to solve the above technical problems, present invention also offers a kind of FPGA, including the multichannel described in any of the above-described
The control system of PWM outputs.
The invention provides a kind of control method of multichannel PWM outputs, including from the every of default first reference clock
Start timing at the time of where the rising edge of pulse in the individual cycle, after timing time reaches default first dead time,
Before at the time of where the trailing edge of pulse in each cycle of first reference clock, N the first pulses of road are generated, so as to final
N roads the first pulse width modulation (PWM) signal is generated, N is the integer more than 1；From each cycle of default second reference clock
In pulse rising edge where at the time of start timing, after timing time reaches default second dead time, the second base
Before at the time of where the trailing edge of pulse in each cycle of punctual clock, N the second pulses of road are generated, to ultimately generate N
The pwm signal of road second, wherein, the phase of the second reference clock and the opposite in phase of the first reference clock.
Compared with the set-up mode of dead time of the prior art, the present invention sets the first dead time in advance, then
Timing at the time of where the rising edge of the pulse in each cycle of default first reference clock, when timing time arrives
Up to after the first dead time, at the time of where the trailing edge of the pulse in each cycle of the first reference clock before, generation
The pulse of multichannel first, the generating principle of the second pulse is identical, simply the phase of the second reference clock and the phase of the first reference clock
Position is on the contrary, so as to avoid the generation of straight-through phenomenon, and the set-up mode of the dead time of the present invention ensure that dead time
Accuracy so that multichannel PWM output it is reliable and stable.
Present invention also offers the control system and FPGA of a kind of multichannel PWM outputs, there is phase with above-mentioned control method
Same beneficial effect.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, below will be to institute in prior art and embodiment
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is a kind of circuit diagram of the control circuit that multichannel PWM is exported in the prior art；
Fig. 2 is a kind of flow chart of the control method of multichannel PWM outputs provided by the invention；
Fig. 3 is a kind of circuit diagram of H-bridge inverter circuit in the prior art；
Fig. 4 is a kind of oscillogram of multichannel PWM outputs provided by the invention；
Fig. 5 is a kind of structural representation of the control system of multichannel PWM outputs provided by the invention.
Embodiment
The core of the present invention is to provide a kind of control method, system and the FPGA of multichannel PWM outputs, avoids straight-through existing
The generation of elephant, it ensure that the accuracy of dead time so that multichannel PWM outputs are reliable and stable.
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
It refer to Fig. 2, Fig. 2 is a kind of flow chart of the control method of multichannel PWM outputs provided by the invention, this method
Including：
Step S1：Counted at the time of where the rising edge of the pulse in each cycle of default first reference clock
When, after timing time reaches default first dead time, the trailing edge of the pulse in each cycle of the first reference clock
Before at the time of place, generate N the first pulses of road, to ultimately generate N roads the first pulse width modulation (PWM) signal, N be more than
1 integer；
Specifically, here default sets in advance, it is only necessary to sets once, is repaiied unless needed for according to actual conditions
Change, otherwise need not reset.Equivalent to one time base of the first reference clock set in advance, i.e., from the first benchmark
Start timing at the time of where the rising edge of pulse in each cycle of clock, timing time reach set in advance the
After one dead time, at the time of where the trailing edge of the pulse in each cycle of the first reference clock before, generation is more
The pulse of road first.That is, dead time and the time sum of the first pulse is in each cycles of the first reference clock
The time of pulse.According to the loop cycle of the first reference clock, the first pwm signal of N roads is finally just generated.
Step S2：Counted at the time of where the rising edge of the pulse in each cycle of default second reference clock
When, after timing time reaches default second dead time, the trailing edge of the pulse in each cycle of the second reference clock
Before at the time of place, N the second pulses of road are generated, to ultimately generate the pwm signal of N roads second, wherein, the second reference clock
Phase and the opposite in phase of the first reference clock.
Specifically, here default and set in advance, it is only necessary to set once, unless needed for according to actual conditions
Modification, otherwise need not reset.Here the second reference clock obtains by the way that the first reference clock is anti-phase, equally
Ground, the second reference clock also correspond to a time base, the i.e. rising from the pulse in each cycle of the second reference clock
Start timing at the time of along place, after timing time reaches the second dead time set in advance, in the second benchmark
Before at the time of where the trailing edge of pulse in each cycle of clock, the pulse of multichannel second is generated.Similarly, dead time and
The time sum of second pulse is the time of the pulse in each cycle of the second reference clock.According to the week of the second reference clock
Phase is circulated, and finally just generates the second pwm signal of N roads.
Realized because more commonly used bridge-type full-controlled rectifier and H bridge inversions are required to multichannel PWM technologies, here with more logical
Application of the road PWM technologies in H-bridge inverter circuit is illustrated.
Fig. 3 and Fig. 4 are refer to, Fig. 3 is a kind of circuit diagram of H-bridge inverter circuit in the prior art, and Fig. 4 provides for the present invention
A kind of multichannel PWM output oscillogram.
Specifically, the principle of H-bridge inverter circuit is：Four diodes are by 2000V AC rectifications into direct current, Ran Houzhi
The stable output after capacitor filtering of stream electricity.When PWM1 switches and PWM4 switches are opened simultaneously, the polarity of voltage of transformer is
On it is just lower negative；When PWM2 switches and PWM3 switches are opened simultaneously, the polarity of voltage of transformer for it is upper it is negative under just, it is achieved thereby that
Direct current becomes the inversion output of alternating current.During whole inversion, PWM1 switches and PWM2 switches are to forbid opening simultaneously
, the direct current electrical short exported after filtering otherwise can be caused, so as to burn whole circuit.Similarly, PWM3 switches and PWM4 are opened
Close and forbid what is opened simultaneously.Therefore, the dead time for accurately controlling each PWM switches is very important.
CLK1 in Fig. 4 is the first reference clock, and CLK2 is the second reference clock, t1~t2For the first dead time, t3~
t4For the second dead time, PWM1 and PWM4 are the first pwm signal, and PWM2 and PWM3 are the second pwm signal.By PWM1 and
PWM4 correspondingly inputs the input of PWM1 switches and the input of PWM4 switches, is opened to open PWM1 switches and PWM4 simultaneously
Close.Similarly, PWM2 and PWM3 is correspondingly inputted in the input of PWM2 switches and the input of PWM3 switches, so as to simultaneously
Open PWM2 switches and PWM3 switches.
It can be seen that due to CLK2 phase and CLK1 opposite in phase, avoid PWM1 switches and PWM2 switches while open,
Equally avoid PWM3 switches and PWM4 switches while open.Further, since t1~t2 and t3~t4 presence, is accurately controlled
Dead time, the generation of straight-through phenomenon is avoided, so as to protect whole circuit.
The invention provides a kind of control method of multichannel PWM outputs, including from the every of default first reference clock
Start timing at the time of where the rising edge of pulse in the individual cycle, after timing time reaches default first dead time,
Before at the time of where the trailing edge of pulse in each cycle of first reference clock, N the first pulses of road are generated, so as to final
N roads the first pulse width modulation (PWM) signal is generated, N is the integer more than 1；From each cycle of default second reference clock
In pulse rising edge where at the time of start timing, after timing time reaches default second dead time, the second base
Before at the time of where the trailing edge of pulse in each cycle of punctual clock, N the second pulses of road are generated, to ultimately generate N
The pwm signal of road second, wherein, the phase of the second reference clock and the opposite in phase of the first reference clock.
Compared with the set-up mode of dead time of the prior art, the present invention sets the first dead time in advance, then
Timing at the time of where the rising edge of the pulse in each cycle of default first reference clock, when timing time arrives
Up to after the first dead time, at the time of where the trailing edge of the pulse in each cycle of the first reference clock before, generation
The pulse of multichannel first, the generating principle of the second pulse is identical, simply the phase of the second reference clock and the phase of the first reference clock
Position is on the contrary, so as to avoid the generation of straight-through phenomenon, and the set-up mode of the dead time of the present invention ensure that dead time
Accuracy so that multichannel PWM output it is reliable and stable.
On the basis of above-described embodiment：
As a kind of preferred embodiment, the second dead time is equal to the first dead time.
Specifically, the first dead time and the second dead time could be arranged to the identical time.Certainly, during the first dead band
Between and the second dead time can also be the different time, it is of the invention not to be particularly limited herein, depending on actual conditions.
As a kind of preferred embodiment, the preset procedures of the first dead time and the second dead time are specially：
According to the pulse number of system clock corresponding to the predetermined frequency dead time of system clock, dead time first
Dead time or the second dead time；
Then timing time reaches default first dead time and the process of default second dead time of timing time arrival is equal
Specially：
The pulse number of accumulative system clock reaches default pulse number.
Specifically, the first dead time and the second dead time are referred to as dead time.The set-up mode of dead time
Can be：The cycle of system clock is obtained by the frequency of system clock, due to the umber of pulse in each cycle of system clock
Mesh is fixed, can be to obtain the pulse number of system clock corresponding to dead time, so as to reach the purpose for setting dead time.
Therefore, the pulse number of accumulation system clock at the time of the timing course of subsequent execution is specially since timing, until accumulative
Pulse number stop when reaching default pulse number accumulative, now reach dead time equivalent to timing time.
Certainly, the application can also utilize other modes to set dead time, and the present invention is not particularly limited herein, root
Depending on actual conditions.
As a kind of preferred embodiment, system clock obtains after carrying out M frequencys multiplication to external clock specifically by phaselocked loop
The clock arrived, wherein, M is the integer more than 1.
Specifically, system clock here is the high frequency clock for external clock obtain after M frequencys multiplication by phaselocked loop,
It is capable of the output of preferably parallel processing multichannel PWM high speed signals.
Certainly, the application can also obtain system clock using other modes, and the present invention is not particularly limited herein, root
Depending on actual conditions.
As a kind of preferred embodiment, this method also includes：
In advance the first reference clock disappear and tremble processing.
Specifically, here pre- advanced processing before this is good, it is only necessary to handles once, unless actual conditions require, otherwise
It need not handle again.First reference clock disappear and trembles processing, makes its frequency more stable, adds the first reference clock
Accuracy and reliability as time base.
As a kind of preferred embodiment, this method also includes：
When there are abnormal conditions, the first reference clock and the second reference clock are resetted.
In view of system it is possible that abnormal situation, when abnormal conditions occur, the first reference clock and the are resetted
Two reference clocks, prevent multichannel PWM to export the occurrence of unstable, so as to avoid the generation of straight-through phenomenon, make
It is reliable to obtain multichannel PWM output safeties.
Fig. 5 is refer to, Fig. 5 is a kind of structural representation of the control system of multichannel PWM outputs provided by the invention, should
System includes：
First pulse generation module 1, for the rising edge from the pulse in each cycle of default first reference clock
Start timing at the time of place, after timing time reaches default first dead time, each cycle of the first reference clock
In pulse trailing edge where at the time of before, generate N the first pulses of road, adjusted to ultimately generate N roads first pulse widths
Pwm signal processed, N are the integer more than 1；
Second pulse generation module 2, for the rising edge from the pulse in each cycle of default second reference clock
Start timing at the time of place, after timing time reaches default second dead time, each cycle of the second reference clock
In pulse trailing edge where at the time of before, generate N the second pulses of road, to ultimately generate the pwm signal of N roads second, its
In, the phase of the second reference clock and the opposite in phase of the first reference clock.
As a kind of preferred embodiment, the system also includes：
Disappear and tremble module, processing is trembled for by the first reference clock disappear in advance.
As a kind of preferred embodiment, the system also includes：
Reseting module, for when there are abnormal conditions, resetting the first reference clock and the second reference clock.
The introduction of system provided by the invention refer to above method embodiment, and the present invention will not be repeated here.
Present invention also offers a kind of FPGA, includes the control system that any of the above-described multichannel PWM is exported.
Specifically, FPGA (Field-Programmable Gate Array, field programmable gate array) not only supports number
The modularization of word circuit is built, and supports Verilog and VHDL language programming, and design method is more flexible.Therefore, multichannel
Each module in the control system of PWM outputs can be integrated in one piece of FPGA, simplified the design of peripheral circuit, reduced into
This.
FPGA provided by the invention other introductions refer to said system embodiment, and the present invention will not be repeated here.
It should also be noted that, in this manual, term " comprising ", "comprising" or its any other variant are intended to contain
Lid nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Other identical element also be present in process, method, article or equipment including the key element.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (10)
- A kind of 1. control method of multichannel PWM outputs, it is characterised in that including：Timing at the time of where the rising edge of the pulse in each cycle of default first reference clock, when timing Between reach default first dead time after, where the trailing edge of the pulse in each cycle of first reference clock when Before quarter, N the first pulses of road are generated, to ultimately generate N roads the first pulse width modulation (PWM) signal, N is the integer more than 1；Timing at the time of where the rising edge of the pulse in each cycle of default second reference clock, when timing Between reach default second dead time after, where the trailing edge of the pulse in each cycle of second reference clock when Before quarter, N the second pulses of road are generated, to ultimately generate the pwm signal of N roads second, wherein, the phase of second reference clock With the opposite in phase of first reference clock.
- 2. the method as described in claim 1, it is characterised in that second dead time is equal to first dead time.
- 3. method as claimed in claim 2, it is characterised in that first dead time and second dead time it is pre- If process is specially：The pulse number of the system clock according to corresponding to the predetermined frequency dead time of system clock, the dead time are First dead time or second dead time；Then the timing time reaches default first dead time and the timing time reaches the mistake of default second dead time Cheng Jun is specially：The pulse number of the accumulative system clock reaches default pulse number.
- 4. method as claimed in claim 3, it is characterised in that the system clock is specifically by phaselocked loop to external clock The clock obtained after M frequencys multiplication is carried out, wherein, M is the integer more than 1.
- 5. method as claimed in claim 4, it is characterised in that this method also includes：In advance first reference clock disappear and tremble processing.
- 6. method as claimed in claim 5, it is characterised in that this method also includes：When there are abnormal conditions, first reference clock and second reference clock are resetted.
- A kind of 7. control system of multichannel PWM outputs, it is characterised in that including：First pulse generation module, for where the rising edge of the pulse in each cycle of default first reference clock Moment starts timing, after timing time reaches default first dead time, in each cycle of first reference clock Pulse trailing edge where at the time of before, generate N the first pulses of road, to ultimately generate the pulse width modulation of N roads first Pwm signal, N are the integer more than 1；Second pulse generation module, for where the rising edge of the pulse in each cycle of default second reference clock Moment starts timing, after timing time reaches default second dead time, in each cycle of second reference clock Pulse trailing edge where at the time of before, generate N the second pulses of road, to ultimately generate the pwm signal of N roads second, wherein, The phase of second reference clock and the opposite in phase of first reference clock.
- 8. system as claimed in claim 7, it is characterised in that the system also includes：Disappear and tremble module, processing is trembled for by first reference clock disappear in advance.
- 9. system as claimed in claim 8, it is characterised in that the system also includes：Reseting module, for when there are abnormal conditions, resetting first reference clock and second reference clock.
- 10. a kind of FPGA, it is characterised in that include the control system of the multichannel PWM outputs as described in claim any one of 7-9 System.
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| CN109088641A (en) * | 2018-07-04 | 2018-12-25 | 华南理工大学 | A kind of digital receiver system and radio frequency analogue-digital conversion method based on FPGA |
| CN111988021A (en) * | 2019-05-24 | 2020-11-24 | 北京车和家信息技术有限公司 | PWM generation method and device, motor controller and vehicle |
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| CN104734678A (en) * | 2015-01-25 | 2015-06-24 | 东北石油大学 | PWM dead-time generation method based on FPGA |
| CN105811937A (en) * | 2016-03-15 | 2016-07-27 | 珠海格力电器股份有限公司 | Waveform output method and device |
| CN106374893A (en) * | 2016-09-22 | 2017-02-01 | 北方电子研究院安徽有限公司 | Configurable PWM wave generating circuit of universal dead zone in embedded SoC system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109088641A (en) * | 2018-07-04 | 2018-12-25 | 华南理工大学 | A kind of digital receiver system and radio frequency analogue-digital conversion method based on FPGA |
| CN111988021A (en) * | 2019-05-24 | 2020-11-24 | 北京车和家信息技术有限公司 | PWM generation method and device, motor controller and vehicle |
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