CN107505113B - Impact tester - Google Patents

Impact tester Download PDF

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Publication number
CN107505113B
CN107505113B CN201710761889.9A CN201710761889A CN107505113B CN 107505113 B CN107505113 B CN 107505113B CN 201710761889 A CN201710761889 A CN 201710761889A CN 107505113 B CN107505113 B CN 107505113B
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China
Prior art keywords
pin
resistor
comparator
flop
flip
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CN107505113A (en
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杜寿余
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Yangzhou Yun Sheng Electronic Technology Co Ltd
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Yangzhou Yun Sheng Electronic Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
    • G01M7/00—Vibration-testing of structures; Shock-testing of structures
    • G01M7/08—Shock-testing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

An impact tester. Relate to an instrument and meter, especially relate to an impact tester. The impact tester with stable and accurate numerical display is provided. The pulse width suppression circuit is connected with the peak suppression circuit, and the peak suppression circuit comprises a pulse width definition circuit, a secondary wave suppression circuit, a threshold comparison circuit and a peak holding circuit; the pulse width defining circuit is connected with the secondary wave suppression circuit, the threshold comparison circuit and the peak value holding circuit are sequentially connected, and the peak value holding circuit is respectively connected with the voltmeter and the nixie tube digital display. In the invention, after the double-peak holding circuit and the threshold comparison circuit are adopted, the pulse peak value and the pulse width data can be updated only when a certain proportion of the peak value is reached, the secondary wave is effectively inhibited, the pulse peak value and the pulse width data are stable and accurate, and the peak value and the pulse width of the main wave can be automatically updated.

Description

Impact tester
Technical Field
The invention relates to an instrument, in particular to an impact tester.
Background
Many equipment need carry out the impact test before leaving the factory, put the product on the impact bench and carry out the impact test to record the relevant parameter in the impact test process, original impact measurement appearance is when measuring peak value, the width of pulse, does not adopt the dual peak value to keep the circuit, does not adopt threshold value comparison circuit either, can not restrain the secondary wave to pulse peak value display and pulse width display are beated, unstable, inaccurate.
The national intellectual property office 2016-1-27 discloses an invention patent application (CN 105277305A, impact test device for quantitatively measuring low impact energy) which comprises a frame, an impact block, a release device and a speed measuring system; the rack comprises a guide rail and a support clamping groove for placing a sample, and the support clamping groove is positioned in the middle of the rack; the impact block is arranged on the guide rail and can slide; the release device comprises an electromagnet sucker; the speed measuring system comprises two laser speed measuring instruments which are symmetrically arranged, the height of the two laser speed measuring instruments is lower than that of the sample supporting clamping groove, and the two laser speed measuring instruments are parallel and level to the groove of the impact block. The impact energy of brittle materials of the instrument is difficult to measure, the manufacturing cost is high, and the like, so that a low-cost simple and practical test device is provided. The impact tester adopts free falling body impact, the velocimeter accurately measures the velocity and calculates the impact energy, and the traditional falling ball or pendulum impact tester with ten thousand yuan can be replaced by hundreds of yuan of cost advantage. The display circuit aiming at the shock wave is not improved, and the problem of unstable and inaccurate display still exists in the measurement process.
Disclosure of Invention
Aiming at the problems, the invention provides the impact tester with stable and accurate numerical display.
The technical scheme of the invention is as follows: the pulse width suppression circuit is connected with the peak suppression circuit, and the peak suppression circuit comprises a pulse width definition circuit, a secondary wave suppression circuit, a threshold comparison circuit and a peak holding circuit;
the pulse width defining circuit is connected with the secondary wave suppression circuit, the threshold comparison circuit and the peak value holding circuit are sequentially connected, and the peak value holding circuit is respectively connected with the voltmeter and the nixie tube digital display.
The pulse width suppression circuit comprises an inverting amplifier N7A, an inverting amplifier N7B, a comparator N8, a double-D trigger N9B and a monostable trigger N11B;
two pins of the inverting amplifier N7A are respectively connected with a resistor R28 and a resistor R29, a resistor R29 is arranged between a first pin and a second pin of the inverting amplifier N7A, a first pin of the inverting amplifier N7A is connected with a sixth pin of the inverting amplifier N7B, and a third pin of the inverting amplifier N7A is grounded;
a resistor R30 is arranged between a first pin of the N7A and a sixth pin of the N7B, the sixth pin of the inverting amplifier N7B is connected with a peak holding circuit V2P through a resistor R32a, a fifth pin of the inverting amplifier N7B is grounded, a seventh pin of the inverting amplifier N7B is connected with the sixth pin of the inverting amplifier N7B, and a resistor R31 is arranged between the seventh pin of the inverting amplifier N7B and the sixth pin of the inverting amplifier N7B;
a pin III of the comparator N8 is connected with a pin VII of an inverting amplifier N7B, a resistor R32b is arranged between a pin III of the comparator N8 and a pin VII of the comparator N7B, a resistor R33 is arranged between a pin III of the comparator N8 and a pin VI of the comparator N8, a pin II of the comparator N8 is respectively connected with a resistor R35 and a resistor R34, one end of the resistor R35 is connected with a pin II of the comparator N8, the other end of the resistor R35 is grounded, one end of the comparator R34 is connected with a pin II of the comparator N8, and the other end of the comparator R34 is connected with a positive power supply;
a pin six of the comparator N8 is connected with a pin eleven of a double-D flip-flop N9B, a resistor R36 is arranged between a pin six of the comparator N8 and the pin eleven of the double-D flip-flop N9B, a diode D10 is arranged between the pin eleven of the flip-flop N9B and the resistor R36, a cathode of the diode D10 is connected with the pin eleven of the double-D flip-flop N9B, and an anode of the diode D10 is grounded;
pin twelve of the double D flip-flop N9B is connected with pin ten of the double D flip-flop N9B, and pin nine of the double D flip-flop is connected with pin eleven of the monostable flip-flop N11B;
the pin fifteen and the pin twelve of the monostable flip-flop N11B are grounded respectively, a capacitor C6 is arranged between the pin fifteen and the pin fourteen of the flip-flop, the pin fourteen of the flip-flop N11B is connected with a positive power supply after being connected with a resistor R39, the pin thirteen of the flip-flop N11B is connected with the positive power supply, and the pin nine of the flip-flop N11B is connected with a nixie tube digital display.
The pulse width definition circuit comprises an inverting amplifier N6A and a comparator N6B, a resistor R23 is arranged on a second pin of an inverting amplifier N6A, a second pin of the inverting amplifier N6A is connected with a first pin of an inverting amplifier N6A, a third pin of an inverting amplifier N6A is grounded, a resistor R24 is arranged between the second pin of the inverting amplifier N6A and the first pin of the inverting amplifier N6A, a first pin of the inverting amplifier N6A is connected with a sixth pin of an inverting amplifier N6B, and a resistor R25 is arranged between the first pin of the inverting amplifier N6A and the sixth pin of the comparator N6B;
a pin six of a comparator N6B is respectively connected with a resistor R27 and a resistor R26, a pin five of the comparator N6B is grounded, a resistor R27 is connected with a potentiometer RS2, one end of the potentiometer RS2 is connected with a positive power supply, the other end of the potentiometer RS2 is connected with a negative power supply, and the resistor R26 is connected with a peak holding circuit V2P;
the input signal VIN is connected to the second pin of the inverting amplifier N6A via a resistor R23, and the peak hold circuit V2P is connected to the sixth pin of the comparator N6B via a resistor R26. The output of the part of the circuit is VIN-V2P/10;
the seventh pin of the comparator N6B is connected to the thirteen pin of the dual D flip-flop N9B and the fourth pin of the monostable flip-flop N11A, respectively.
The threshold comparison circuit comprises an adder N5A and a comparator N5B, wherein a first pin of the adder N5A is connected with a second pin of the adder N5A, a resistor R17 is arranged between the first pin of the adder N5A and the second pin of the adder N5A, a first pin of the adder N5A is connected with a fifth pin of the comparator N5B, and a resistor R18 is arranged between the first pin of the adder N5A and the fifth pin of the comparator N5B. Pin two of the adder N5A is connected to V2P of the peak hold circuit via a resistor R16, and pin three of the adder N5A is connected to V1P of the peak hold circuit via a resistor R15;
a fifth pin of the comparator N5B is connected with a seventh pin of the comparator N5B, a resistor R19 is arranged between the fifth pin of the comparator N5B and the seventh pin of the comparator N5B, a sixth pin of the comparator N5B is respectively connected with a resistor R20 and a resistor R21, the resistor R21 is grounded, the resistor R20 is connected with the potentiometer RS1, one end of the potentiometer RS1 is connected with a positive power supply, and the other end of the potentiometer RS1 is connected with a negative power supply;
a seventh pin of the comparator N5B is connected with the secondary wave suppression circuit, and a resistor R22 is arranged between the seventh pin of the comparator N5B and the secondary wave suppression circuit;
the secondary wave suppression circuit comprises a monostable trigger N11A and a monostable trigger N10B, wherein a first pin of a trigger N11A is grounded, a second pin of the trigger N11A is connected with a positive power supply, a capacitor C5 is arranged between the first pin of the trigger N11A and the second pin of the trigger N11A, a resistor R38 is arranged between the second pin of the trigger N11A and the positive power supply, a fourth pin of the trigger N11A is connected with a seventh pin of a comparator N6B, a third pin of a trigger N11A is connected with the positive power supply, a fifth pin of the trigger N11A is connected with a third pin, and a sixth pin of the trigger N11A is connected with a peak value holding circuit;
a pin fourteen of a monostable flip-flop N10B is connected with a positive power supply, a resistor R37 is arranged between the pin fourteen of a flip-flop N10B and the positive power supply, a pin fifteen of a flip-flop N10B is grounded, a capacitor C3 is arranged between the pin fourteen of the flip-flop N10B and the pin fifteen of a flip-flop N10B, a pin twelve of the flip-flop N10B is connected with a pin seven of a comparator N5B, a resistor R22 is arranged between the pin twelve of the flip-flop N10B and the pin seven of the comparator N5B, a diode D9 is arranged between the resistor R22 and the pin seven of the comparator N5B, an anode of the diode D9 is grounded, a pin eleven of the flip-flop N10B is connected with a pin thirteen of the flip-flop N10B, a pin thirteen of the flip-flop N10B is connected with the positive power supply.
The peak holding circuit comprises operational amplifiers N1-N4, a second pin of an operational amplifier N1 is connected with a sixth pin of an operational amplifier N1, a diode D2 is arranged between the second pin of the operational amplifier N1 and the sixth pin of an operational amplifier N1, a resistor R1 is arranged between the second pin of the operational amplifier N1 and the second pin of the operational amplifier N2, the sixth pin of the operational amplifier N1 is connected with a diode D3 and a transistor D1, the anode of the transistor D1 is connected with the sixth pin of the N2 through the resistor R2, and the cathode of the transistor D1 is connected with a third pin of a comparator N2;
a resistor R3 is arranged between a pin III of the operational amplifier N2 and the cathode of the transistor D1, and a pin VI of the operational amplifier N2 is connected with a pin II of the operational amplifier N2;
the cathode of the transistor D1 is sequentially connected with a resistor R4 and a resistor R5, the resistor R5 is connected with the collector of the triode D4, the emitter of the triode D4 is grounded, the base of the triode D4 is respectively connected with a resistor R6 and a resistor R7, a resistor R7 is grounded, the resistor R6 contacts with a pin six of the generator N11A, a capacitor C1 is connected between the resistor R4 and the resistor R5, and the capacitor C1 is grounded;
a pin six of the operational amplifier N2 is connected with a pin three of the operational amplifier N3, a pin two of the operational amplifier N3 is connected with a pin six of the operational amplifier N3, a diode D6 is arranged between a pin two of the operational amplifier N3 and a pin six of the operational amplifier N3, a resistor R8 is arranged between a pin two of the operational amplifier N3 and a pin two of the operational amplifier N4, a pin six of the operational amplifier N3 is connected with a diode D7 and a diode D6, and a resistor R9 is arranged between an anode of a diode D7 and the resistor R8;
the three pins of the operational amplifier N4 are connected with a resistor R10, a resistor R10 is connected with the cathode of a diode D5, and a peak holding circuit is formed by the resistor R11 and a capacitor C2. The resistor R12 is connected with a collector of the triode D6, an emitter of the triode D6 is grounded, a base of the triode D6 is respectively connected with the resistor R13 and the resistor R14, the resistor R14 is grounded, the resistor R13 is connected with a pin ten of the trigger N10B, a capacitor C2 is connected between the resistor R11 and the resistor R12, and the capacitor C2 is grounded;
a second pin of the operational amplifier N4 is connected with a second pin of the operational amplifier N5A through a resistor R16, a second pin of the operational amplifier N2 is connected with a third pin of the operational amplifier N5A through a resistor R15, and a sixth pin of the operational amplifier N4 is connected with a voltmeter.
The nixie tube digital display comprises a BCD code counter N13B, a NOT gate N12A, a NOT gate N12F and a seven-segment code decoder N15, eleven pins to fourteen pins of the BCD code counter N13B are correspondingly connected with seven pins, one pins, two pins and six pins of a seven-segment code decoder N15, pins of N13B are connected with a first pin of the NOT gate N12A, a thirteen pin of a double-D trigger N9B and a seventh pin of a comparator N6B, and a fifteenth pin of the trigger N13B is connected with a twelve pin of the NOT gate N12F;
a pin thirteen of the NOT gate N12F is respectively connected with a resistor R40 and a capacitor C7, the resistor R40 is connected with a positive power supply, and the capacitor C7 is connected with a pin two of the NOT gate N12A;
and a third pin of the seven-segment code decoder N15 is connected with a fourth pin and is connected with a positive power supply, a fifth pin of the seven-segment code decoder N15 is connected with a ninth pin of the monostable flip-flop N11B, and ninth to fifteenth pins of the N15 are digital output display.
The nixie tube digital display is provided with an oscillating circuit, the oscillating circuit is connected with a pin nine of a BCD code counter N13B, the oscillating circuit comprises a NOT gate N12E and a NOT gate N12D, a pin nine of a NOT gate N12E is connected with a pin nine of a NOT gate N12D, a pin nine of a BCD code counter N13B is sequentially connected with a resistor R41 and a potentiometer RS3, one end of the potentiometer RS3 is connected with a pin eleven of the NOT gate N12E, the other end of the potentiometer is connected with a resistor R41, a resistor R42 is arranged between the pin eleven of the NOT gate N12E and the potentiometer, the resistor R42 is respectively connected with the potentiometer RS3 and connected with a pin eight of the NOT gate N12D, and a capacitor C10 is arranged between the resistor R42 and the pin eight of the NOT gate N12.
In the invention, after the double-peak holding circuit and the threshold comparison circuit are adopted, the pulse peak value and the pulse width data can be updated only when a certain proportion of the peak value is reached, the secondary wave is effectively inhibited, the pulse peak value and the pulse width data are stable and accurate, and the peak value and the pulse width of the main wave can be automatically updated.
Drawings
Figure 1 is a circuit diagram of the present invention,
figure 2 is a circuit diagram of the pulse width suppression circuit of the present invention,
figure 3 is a circuit diagram of the pulse width definition circuit of the present invention,
figure 4 is a circuit diagram of the threshold comparison circuit of the present invention,
figure 5 is a circuit diagram of the inventive subwave suppression circuit,
figure 6 is a circuit diagram of the peak hold circuit of the present invention,
figure 7 is a circuit diagram of a nixie tube digital display of the present invention,
fig. 8 is a circuit diagram of an oscillator of the present invention.
Detailed Description
The invention is shown in fig. 1-8, which comprises a pulse width suppression circuit and a peak value suppression circuit, wherein the pulse width suppression circuit is connected with the peak value suppression circuit, and the peak value suppression circuit comprises a pulse width definition circuit, a secondary wave suppression circuit, a threshold value comparison circuit and a peak value holding circuit;
the pulse width defining circuit is connected with the secondary wave suppression circuit, the threshold comparison circuit and the peak value holding circuit are sequentially connected, and the peak value holding circuit is respectively connected with the voltmeter and the nixie tube digital display.
The pulse width suppression circuit comprises an inverting amplifier N7A, an inverting amplifier N7B, a comparator N8, a double-D trigger N9B and a monostable trigger N11B;
two pins of the inverting amplifier N7A are respectively connected with a resistor R28 and a resistor R29, a resistor R29 is arranged between a first pin and a second pin of the inverting amplifier N7A, a first pin of the inverting amplifier N7A is connected with a sixth pin of the inverting amplifier N7B, and a third pin of the inverting amplifier N7A is grounded;
a resistor R30 is arranged between a first pin of the N7A and a sixth pin of the N7B, the sixth pin of the inverting amplifier N7B is connected with a peak holding circuit V2P through a resistor R32a, a fifth pin of the inverting amplifier N7B is grounded, a seventh pin of the inverting amplifier N7B is connected with the sixth pin of the inverting amplifier N7B, and a resistor R31 is arranged between the seventh pin of the inverting amplifier N7B and the sixth pin of the inverting amplifier N7B;
a pin III of the comparator N8 is connected with a pin VII of an inverting amplifier N7B, a resistor R32b is arranged between a pin III of the comparator N8 and a pin VII of the comparator N7B, a resistor R33 is arranged between a pin III of the comparator N8 and a pin VI of the comparator N8, a pin II of the comparator N8 is respectively connected with a resistor R35 and a resistor R34, one end of the resistor R35 is connected with a pin II of the comparator N8, the other end of the resistor R35 is grounded, one end of the comparator R34 is connected with a pin II of the comparator N8, and the other end of the comparator R34 is connected with a positive power supply;
a pin six of the comparator N8 is connected with a pin eleven of a double-D flip-flop N9B, a resistor R36 is arranged between a pin six of the comparator N8 and the pin eleven of the double-D flip-flop N9B, a diode D10 is arranged between the pin eleven of the flip-flop N9B and the resistor R36, a cathode of the diode D10 is connected with the pin eleven of the double-D flip-flop N9B, and an anode of the diode D10 is grounded;
pin twelve of the double D flip-flop N9B is connected with pin ten of the double D flip-flop N9B, and pin nine of the double D flip-flop is connected with pin eleven of the monostable flip-flop N11B;
the pin fifteen and the pin twelve of the monostable flip-flop N11B are grounded respectively, a capacitor C6 is arranged between the pin fifteen and the pin fourteen of the flip-flop, the pin fourteen of the flip-flop N11B is connected with a positive power supply after being connected with a resistor R39, the pin thirteen of the flip-flop N11B is connected with the positive power supply, and the pin nine of the flip-flop N11B is connected with a nixie tube digital display.
The pulse width definition circuit comprises an inverting amplifier N6A and a comparator N6B, a resistor R23 is arranged on a second pin of an inverting amplifier N6A, a second pin of the inverting amplifier N6A is connected with a first pin of an inverting amplifier N6A, a third pin of an inverting amplifier N6A is grounded, a resistor R24 is arranged between the second pin of the inverting amplifier N6A and the first pin of the inverting amplifier N6A, a first pin of the inverting amplifier N6A is connected with a sixth pin of an inverting amplifier N6B, and a resistor R25 is arranged between the first pin of the inverting amplifier N6A and the sixth pin of the comparator N6B;
a pin six of a comparator N6B is respectively connected with a resistor R27 and a resistor R26, a pin five of the comparator N6B is grounded, a resistor R27 is connected with a potentiometer RS2, one end of the potentiometer RS2 is connected with a positive power supply, the other end of the potentiometer RS2 is connected with a negative power supply, and the resistor R26 is connected with a peak holding circuit V2P;
the input signal VIN is connected to the second pin of the inverting amplifier N6A via a resistor R23, and the peak hold circuit V2P is connected to the sixth pin of the comparator N6B via a resistor R26. The output of the part of the circuit is VIN-V2P/10, namely a pulse width definition circuit;
a seventh pin of the comparator N6B is respectively connected with a thirteen pin of the double-D flip-flop N9B and a fourth pin of the monostable flip-flop N11A;
the threshold comparison circuit comprises an adder N5A and a comparator N5B, the output of a pin I of the adder N5A is 4V 1P-3V 2P, the comparator N5B is a zero-crossing comparator, and a potentiometer RS1 adjusts the zero point of the comparator. When V1P > 3/4V2P, pin seven of comparator V5B generates a positive pulse. The first pin of the adder N5A is connected with the second pin of the adder N5A, a resistor R17 is arranged between the first pin of the adder N5A and the second pin of the adder N5A, the first pin of the adder N5A is connected with the fifth pin of the comparator N5B, and a resistor R18 is arranged between the first pin of the adder N5A and the fifth pin of the comparator N5B. A second pin of the adder N5A is connected to the peak hold circuit V2P via a resistor R16, and a third pin is connected to the peak hold circuit V1P via a resistor R15;
a fifth pin of the comparator N5B is connected with a seventh pin of the comparator N5B, a resistor R19 is arranged between the fifth pin of the comparator N5B and the seventh pin of the comparator N5B, a sixth pin of the comparator N5B is respectively connected with a resistor R20 and a resistor R21, the resistor R21 is grounded, the resistor R20 is connected with the potentiometer RS1, one end of the potentiometer RS1 is connected with a positive power supply, and the other end of the potentiometer RS1 is connected with a negative power supply;
a seventh pin of the comparator N5B is connected with the secondary wave suppression circuit, and a resistor R22 is arranged between the seventh pin of the comparator N5B and the secondary wave suppression circuit;
the secondary wave suppression circuit comprises a monostable trigger N11A and a monostable trigger N10B, wherein a first pin of the trigger N11A is grounded, a second pin of the trigger N11A is connected with a positive power supply, a capacitor C2 is arranged between the first pin of the trigger N11A and the second pin of the trigger N11A, a resistor R38 is arranged between the second pin of the trigger N11A and the positive power supply, a fourth pin of the trigger N11A is connected with a seventh pin of a comparator N6B, a third pin of the trigger N11A is connected with the positive power supply, a fifth pin of the trigger N11A is connected with a third pin, and a sixth pin of the trigger N11A is connected with a reset circuit of a peak value holding circuit V1P;
a pin fourteen of a monostable trigger N10B is connected with a positive power supply, a resistor R37 is arranged between the pin fourteen of the trigger N10B and the positive power supply, a pin fifteen of the trigger N10B is grounded, a capacitor C3 is arranged between the pin fourteen of the trigger N10B and the pin fifteen of the trigger N10B, a pin twelve of the trigger N10B is connected with a pin seven of a comparator N5B, a resistor R22 is arranged between a pin twelve of the trigger N10B and a pin seven of the comparator N5B, a diode D9 is arranged between the resistor R22 and the pin seven of the comparator N5B, an anode of the diode D9 is grounded, a pin eleven of the trigger N10B is connected with a pin thirteen of the trigger N10B, a pin thirteen of the trigger N10B is connected with the positive power supply, and a pin of the trigger N10B is connected with a reset circuit of a peak holding circuit V2P;
the peak holding circuit comprises operational amplifiers N1-N4, a second pin of an operational amplifier N1 is connected with a sixth pin of an operational amplifier N1, a diode D2 is arranged between the second pin of the operational amplifier N1 and the sixth pin of an operational amplifier N1, a resistor R1 is arranged between the second pin of the operational amplifier N1 and the second pin of the operational amplifier N2, the sixth pin of the operational amplifier N1 is connected with a diode D3 and a transistor D1, the anode of the transistor D1 is connected with the sixth pin of the N2 through the resistor R2, and the cathode of the transistor D1 is connected with a third pin of a comparator N2;
a resistor R3 is arranged between a pin III of the operational amplifier N2 and the cathode of the transistor D1, and a pin VI of the operational amplifier N2 is connected with a pin II of the operational amplifier N2;
the cathode of the transistor D1 is sequentially connected with a resistor R4 and a resistor R5, the resistor R5 is connected with the collector of the triode D4, the emitter of the triode D4 is grounded, the base of the triode D4 is respectively connected with a resistor R6 and a resistor R7, a resistor R7 is grounded, the resistor R6 is in contact with a pin six of the N11A of the generator, a capacitor C1 is connected between the resistor R4 and the resistor R5, and a capacitor C1 is grounded, which is a reset circuit of the peak holding circuit V1P;
the six pin of the operational amplifier N2 is connected to the three pin of the operational amplifier N3, i.e., the output of the peak hold circuit V1P is connected to the input of the peak hold circuit V2P. A second pin of the operational amplifier N3 is connected with a sixth pin of the operational amplifier N3, a diode D6 is arranged between the second pin of the operational amplifier N3 and the sixth pin of the operational amplifier N3, a resistor R8 is arranged between the second pin of the operational amplifier N3 and the second pin of the operational amplifier N4, the sixth pin of the operational amplifier N3 is connected with a diode D7 and a diode D6, and a resistor R9 is arranged between the anode of the diode D7 and the resistor R8;
the three pins of the operational amplifier N4 are connected with a resistor R10, a resistor R10 is connected with the cathode of a diode D5, and a peak holding circuit is formed by the resistor R11 and a capacitor C2. The resistor R12 is connected with the collector of the triode D6, the emitter of the triode D6 is grounded, the base of the triode D6 is respectively connected with the resistor R13 and the resistor R14, the resistor R14 is grounded, the resistor R13 is connected with the pin ten of the trigger N10B, the capacitor C2 is connected between the resistor R11 and the resistor R12, the capacitor C2 is grounded, and the part is the reset circuit of the peak holding circuit;
and a second pin of the operational amplifier N4 is connected with a second pin of the operational amplifier N5A through a resistor R16, and a second pin of the operational amplifier N2 is connected with a third pin of the operational amplifier N5A through a resistor R15 to form a subtracter. And a six-pin voltage meter of the operational amplifier N4.
The nixie tube digital display comprises a BCD code counter N13B, a NOT gate N12A, a NOT gate N12F and a seven-segment code decoder N15, eleven pins to fourteen pins of the BCD code counter N13B are correspondingly connected with seven pins, one pins, two pins and six pins of a seven-segment code decoder N15, pins of N13B are connected with a first pin of the NOT gate N12A, a thirteen pin of a double-D trigger N9B and a seventh pin of a comparator N6B, and a fifteenth pin of the trigger N13B is connected with a twelve pin of the NOT gate N12F;
a thirteen pin of the NOT gate N12F is respectively connected with a resistor R40 and a capacitor C7, the resistor R40 is connected with a positive power supply, the capacitor C7 is connected with a second pin of the NOT gate N12A, and the part is used as a reset circuit of the BCD code counter N13B;
the three pins and the four pins of the seven-segment code decoder N15 are connected with a positive power supply, the five pins of the N15 are connected with the nine pins of the monostable flip-flop N11B and used as latch signals of the decoder, and the nine pins to the fifteen pins of the N15 are digital output display.
The nixie tube digital display is provided with an oscillating circuit, the oscillating circuit is connected with a pin nine of a BCD code counter N13B and used as counting input of a BCD code counter N13B, the oscillating circuit comprises a not gate N12E and a not gate N12D, a pin ten of the not gate N12E is connected with a pin nine of the not gate N12D, a pin nine of the BCD code counter N13B is sequentially connected with a resistor R41 and a potentiometer RS3, one end of the potentiometer RS3 is connected with a pin eleven of the not gate N12E, the other end of the potentiometer is connected with the resistor R41, a resistor R42 is arranged between the pin eleven of the not gate N12E and the potentiometer, the resistor R42 is respectively connected with the potentiometer RS3 and connected with a pin eight of the not gate N12D, and a capacitor C10 is arranged between the resistor R42 and the pin eight of the not gate N12D.
In the figure, V1P (point T1) is the peak hold circuit output of signal VIN (point T3), V2P (point T2) is the peak hold circuit output of V1P, and V2P is sent to the front panel of the instrument for peak display.
The output of the N5A operational amplifier is 4V 1P-3V 2P, and N5B is a zero-crossing comparator. When V1P is greater than 3/4V2P, the N5B operational amplifier generates a positive pulse signal, which is sent to the N10B one-shot. The N10B one shot 10 pin (T7) generates a positive pulse signal to the V2P reset circuit so that new peak data enters the V2P peak circuit and is displayed. Therefore, the wavelet signals can not enter a peak circuit, and signals close to the peak can be acquired (because the signals of the collision table and the impact table have fluctuation).
The output (zero-crossing comparator) of the N6B operational amplifier (T5) is VIN-V2P/10, which is the pulse width of the main wave pulse, and when VIN is greater than V2P/10, a positive pulse signal is generated at point T5. The T5 signal is sent to N11A one-shot, the pin 6 output of N11A one-shot is sent to V1P reset circuit. The T5 signal is sent to N13B counter for pulse width measurement, and also sent to N12A and N12F NOT gate to generate differential signal and sent to reset terminal of counter. T12 is a 100KHz oscillating signal used to measure pulse width.
VIN is sent to N7A and N7B operational amplifiers, and the signal at the T6 point is VIN-0.82V 2P. When VIN is greater than 0.82V2P, the N8 zero-crossing comparator generates a positive pulse signal. N9B is a 74HC74 dual D flip-flop, and the T5 (pulse width) signal is connected to the reset terminal of N9B. When VIN is greater than 0.82V2P (dominant wave active, secondary wave removed), the 9-pin output of N9B generates a waveform with the same pulse width.
The T9 signal is sent to the N11B one-shot flip-flop, which is a negative edge trigger. When T9 is at the falling edge, the output of pin N11B 9 produces a negative pulse output T10. T10N 15 CD4511
And the latch end of the (BCD code seven-segment decoder) enables the number (pulse width value) of the counter to be collected and latched and sent to the front panel for pulse display. A double-peak circuit is adopted to remove secondary waves, and the main wave peak value and the pulse width of signals generated by a collision table and an impact table are automatically displayed, and the peak value and the pulse width value are not influenced by the secondary waves.

Claims (7)

1. An impact tester comprises a pulse width suppression circuit and a peak suppression circuit, and is characterized in that the pulse width suppression circuit is connected with the peak suppression circuit, and the peak suppression circuit comprises a pulse width definition circuit, a secondary wave suppression circuit, a threshold comparison circuit and a peak holding circuit;
the pulse width defining circuit is connected with a secondary wave suppression circuit, the threshold comparison circuit and the peak holding circuit are sequentially connected, and the peak holding circuit is respectively connected with a voltmeter and a nixie tube digital display;
the pulse width suppression circuit comprises an inverting amplifier N7A, an inverting amplifier N7B, a comparator N8, a double-D trigger N9B and a monostable trigger N11B;
two pins of the inverting amplifier N7A are respectively connected with a resistor R28 and a resistor R29, a resistor R29 is arranged between a first pin and a second pin of the inverting amplifier N7A, a first pin of the inverting amplifier N7A is connected with a sixth pin of the inverting amplifier N7B, and a third pin of the inverting amplifier N7A is grounded;
a resistor R30 is arranged between a first pin of the N7A and a sixth pin of the N7B, the sixth pin of the inverting amplifier N7B is connected with a peak holding circuit V2P through a resistor R32a, a fifth pin of the inverting amplifier N7B is grounded, a seventh pin of the inverting amplifier N7B is connected with the sixth pin of the inverting amplifier N7B, and a resistor R31 is arranged between the seventh pin of the inverting amplifier N7B and the sixth pin of the inverting amplifier N7B;
a pin III of the comparator N8 is connected with a pin VII of an inverting amplifier N7B, a resistor R32b is arranged between a pin III of the comparator N8 and a pin VII of the comparator N7B, a resistor R33 is arranged between a pin III of the comparator N8 and a pin VI of the comparator N8, a pin II of the comparator N8 is respectively connected with a resistor R35 and a resistor R34, one end of the resistor R35 is connected with a pin II of the comparator N8, the other end of the resistor R35 is grounded, one end of the comparator R34 is connected with a pin II of the comparator N8, and the other end of the comparator R34 is connected with a positive power supply;
a pin six of the comparator N8 is connected with a pin eleven of a double-D flip-flop N9B, a resistor R36 is arranged between a pin six of the comparator N8 and the pin eleven of the double-D flip-flop N9B, a diode D10 is arranged between the pin eleven of the flip-flop N9B and the resistor R36, a cathode of the diode D10 is connected with the pin eleven of the double-D flip-flop N9B, and an anode of the diode D10 is grounded;
pin twelve of the double D flip-flop N9B is connected with pin ten of the double D flip-flop N9B, and pin nine of the double D flip-flop is connected with pin eleven of the monostable flip-flop N11B;
the pin fifteen and the pin twelve of the monostable flip-flop N11B are grounded respectively, a capacitor C6 is arranged between the pin fifteen and the pin fourteen of the flip-flop, the pin fourteen of the flip-flop N11B is connected with a positive power supply after being connected with a resistor R39, the pin thirteen of the flip-flop N11B is connected with the positive power supply, and the pin nine of the flip-flop N11B is connected with a nixie tube digital display.
2. The impact tester of claim 1, wherein the pulse width definition circuit comprises an inverting amplifier N6A and a comparator N6B, a resistor R23 is arranged on a second pin of an inverting amplifier N6A, the second pin of the inverting amplifier N6A is connected with a first pin of an inverting amplifier N6A, a third pin of an inverting amplifier N6A is grounded, a resistor R24 is arranged between the second pin of the inverting amplifier N6A and the first pin of the inverting amplifier N6A, the first pin of the inverting amplifier N6A is connected with a sixth pin of an inverting amplifier N6B, and a resistor R25 is arranged between the first pin of the inverting amplifier N6A and the sixth pin of the comparator N6B;
a pin six of a comparator N6B is respectively connected with a resistor R27 and a resistor R26, a pin five of the comparator N6B is grounded, a resistor R27 is connected with a potentiometer RS2, one end of the potentiometer RS2 is connected with a positive power supply, the other end of the potentiometer RS2 is connected with a negative power supply, and the resistor R26 is connected with a peak holding circuit V2P;
the input signal VIN is connected with a second pin of the inverting amplifier N6A through a resistor R23, the peak holding circuit V2P is connected with a sixth pin of the comparator N6B through a resistor R26, and the output of the circuit is VIN-V2P/10;
the seventh pin of the comparator N6B is connected to the thirteen pin of the dual D flip-flop N9B and the fourth pin of the monostable flip-flop N11A, respectively.
3. The impact tester of claim 2, wherein the threshold comparison circuit comprises an adder N5A and a comparator N5B, a first pin of the adder N5A is connected with a second pin of the adder N5A, a resistor R17 is arranged between the first pin of the adder N5A and the second pin of the adder N5A, the first pin of the adder N5A is connected with a fifth pin of the comparator N5B, a resistor R18 is arranged between the first pin of the adder N5A and the fifth pin of the comparator N5B, the second pin of the adder N5A is connected with a V2P of the peak-hold circuit via a resistor R16, and the third pin of the adder N5A is connected with a V1P of the peak-hold circuit via a resistor R15;
a fifth pin of the comparator N5B is connected with a seventh pin of the comparator N5B, a resistor R19 is arranged between the fifth pin of the comparator N5B and the seventh pin of the comparator N5B, a sixth pin of the comparator N5B is respectively connected with a resistor R20 and a resistor R21, the resistor R21 is grounded, the resistor R20 is connected with the potentiometer RS1, one end of the potentiometer RS1 is connected with a positive power supply, and the other end of the potentiometer RS1 is connected with a negative power supply;
a seventh pin of the comparator N5B is connected with the secondary wave suppression circuit, and a resistor R22 is arranged between the seventh pin of the comparator N5B and the secondary wave suppression circuit.
4. The impact tester of claim 3, wherein the secondary wave suppression circuit comprises a monostable flip-flop N11A and a monostable flip-flop N10B, a first pin of the flip-flop N11A is grounded, a second pin of the flip-flop N11A is connected with a positive power supply, a capacitor C5 is arranged between the first pin of the flip-flop N11A and the second pin of the flip-flop N11A, a resistor R38 is arranged between the second pin of the flip-flop N11A and the positive power supply, a fourth pin of the flip-flop N11A is connected with a seventh pin of a comparator N6B, a third pin of the flip-flop N11A is connected with the positive power supply, a fifth pin of the flip-flop N11A is connected with a third pin, and a sixth pin of the flip-flop N11A is connected with a peak hold circuit;
a pin fourteen of a monostable flip-flop N10B is connected with a positive power supply, a resistor R37 is arranged between the pin fourteen of a flip-flop N10B and the positive power supply, a pin fifteen of a flip-flop N10B is grounded, a capacitor C3 is arranged between the pin fourteen of the flip-flop N10B and the pin fifteen of a flip-flop N10B, a pin twelve of the flip-flop N10B is connected with a pin seven of a comparator N5B, a resistor R22 is arranged between the pin twelve of the flip-flop N10B and the pin seven of the comparator N5B, a diode D9 is arranged between the resistor R22 and the pin seven of the comparator N5B, an anode of the diode D9 is grounded, a pin eleven of the flip-flop N10B is connected with a pin thirteen of the flip-flop N10B, a pin thirteen of the flip-flop N10B is connected with the positive power supply.
5. The impact tester of claim 4, wherein the peak holding circuit comprises operational amplifiers N1-N4, a second pin of the operational amplifier N1 is connected with a sixth pin of the operational amplifier N1, a diode D2 is arranged between the second pin of the operational amplifier N1 and the sixth pin of the operational amplifier N1, a resistor R1 is arranged between the second pin of the operational amplifier N1 and the second pin of the operational amplifier N2, the sixth pin of the operational amplifier N1 is connected with a diode D3 and a transistor D1, the anode of the transistor D1 is connected with the sixth pin of the N2 through the resistor R2, and the cathode of the transistor D1 is connected with a third pin of the comparator N2;
a resistor R3 is arranged between a pin III of the operational amplifier N2 and the cathode of the transistor D1, and a pin VI of the operational amplifier N2 is connected with a pin II of the operational amplifier N2;
the cathode of the transistor D1 is sequentially connected with a resistor R4 and a resistor R5, the resistor R5 is connected with the collector of the triode D4, the emitter of the triode D4 is grounded, the base of the triode D4 is respectively connected with a resistor R6 and a resistor R7, a resistor R7 is grounded, the resistor R6 contacts with a pin six of the generator N11A, a capacitor C1 is connected between the resistor R4 and the resistor R5, and the capacitor C1 is grounded;
a pin six of the operational amplifier N2 is connected with a pin three of the operational amplifier N3, a pin two of the operational amplifier N3 is connected with a pin six of the operational amplifier N3, a diode D6 is arranged between a pin two of the operational amplifier N3 and a pin six of the operational amplifier N3, a resistor R8 is arranged between a pin two of the operational amplifier N3 and a pin two of the operational amplifier N4, a pin six of the operational amplifier N3 is connected with a diode D7 and a diode D6, and a resistor R9 is arranged between an anode of a diode D7 and the resistor R8;
a pin III of the operational amplifier N4 is connected with a resistor R10, a resistor R10 is connected with the cathode of a diode D5, and a peak holding circuit is formed by the resistor R11 and a capacitor C2;
the resistor R12 is connected with a collector of the triode D6, an emitter of the triode D6 is grounded, a base of the triode D6 is respectively connected with the resistor R13 and the resistor R14, the resistor R14 is grounded, the resistor R13 is connected with a pin ten of the trigger N10B, a capacitor C2 is connected between the resistor R11 and the resistor R12, and the capacitor C2 is grounded;
a second pin of the operational amplifier N4 is connected with a second pin of the operational amplifier N5A through a resistor R16, a second pin of the operational amplifier N2 is connected with a third pin of the operational amplifier N5A through a resistor R15, and a sixth pin of the operational amplifier N4 is connected with a voltmeter.
6. The impact tester of claim 5, wherein the nixie tube digital display comprises a BCD code counter N13B, a NOT gate N12A, a NOT gate N12F and a seven-segment code decoder N15, wherein eleven to fourteen pins of the BCD code counter N13B are correspondingly connected with seven pins, one pin, two pins and six pins of the seven-segment code decoder N15, pins of N13B are respectively connected with one pin of the NOT gate N12A, thirteen pin of a double-D trigger N9B and seven pin of a comparator N6B, and fifteen pin of the trigger N13B is connected with twelve pin of the NOT gate N12F;
a pin thirteen of the NOT gate N12F is respectively connected with a resistor R40 and a capacitor C7, the resistor R40 is connected with a positive power supply, and the capacitor C7 is connected with a pin two of the NOT gate N12A;
and a third pin of the seven-segment code decoder N15 is connected with a fourth pin and is connected with a positive power supply, a fifth pin of the seven-segment code decoder N15 is connected with a ninth pin of the monostable flip-flop N11B, and ninth to fifteenth pins of the N15 are digital output display.
7. The impact tester of claim 6, wherein the nixie tube digital display is provided with an oscillation circuit, the oscillation circuit is connected with a pin nine of a BCD code counter N13B, the oscillation circuit comprises a NOT gate N12E and a NOT gate N12D, a pin nine of the NOT gate N12E is connected with a pin ten of the NOT gate N12D, a pin nine of the BCD code counter N13B is sequentially connected with a resistor R41 and a potentiometer RS3, one end of the potentiometer RS3 is connected with a pin eleven of the NOT gate N12E, the other end of the potentiometer is connected with the resistor R41, a resistor R42 is arranged between the pin eleven of the NOT gate N12E and the potentiometer, the resistor R42 is respectively connected with the potentiometer RS3 and an pin eight of the NOT gate N12D, and a capacitor C10 is arranged between the resistor R42 and the pin eight of the NOT gate N12D.
CN201710761889.9A 2017-08-30 2017-08-30 Impact tester Active CN107505113B (en)

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JPS6030132B2 (en) * 1980-06-09 1985-07-15 日本電信電話株式会社 Pulse width control circuit
JPS6027840A (en) * 1983-07-26 1985-02-12 Nippon Denso Co Ltd Shock tester
CN2271711Y (en) * 1996-11-29 1997-12-31 中国航天工业总公司第一计量测试研究所 Simple drop hammer type deflectometer
CN100386610C (en) * 2004-12-09 2008-05-07 南京航空航天大学 Pneumatic type multiple waveform active shock waveform generator
CN101660925B (en) * 2009-09-23 2011-01-12 宁波大学 Processing method of interference signals in decoding process of digital coder

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