CN107491223A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN107491223A CN107491223A CN201710882448.4A CN201710882448A CN107491223A CN 107491223 A CN107491223 A CN 107491223A CN 201710882448 A CN201710882448 A CN 201710882448A CN 107491223 A CN107491223 A CN 107491223A
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- test signal
- signal line
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- ground wire
- line region
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention provides a kind of display panel, including viewing area and the non-display area positioned at viewing area both sides, underlay substrate, multiple thin film transistor (TFT)s, a plurality of touching signals line, the first test signal line region, array base palte horizontal drive circuit, the second test signal line region and ground wire region；There is insulating barrier between thin film transistor (TFT) and touching signals line；Thin film transistor (TFT) includes grid, gate insulator, source electrode and drain electrode；The non-display area includes first side and second side；First test signal line region includes the first side and the second side；First side is adjacent with the first side, array base palte horizontal drive circuit forms the first gap and the second gap with the first test signal line region and the second test signal line region respectively, there is third space between ground wire region and second side, orthographic projection part of the ground wire region on underlay substrate is located at the second test signal line region in the projection of underlay substrate.The present invention also provides a kind of display device.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of display panel and display device.
Background technology
In current illumination and display field, due to have low temperature polycrystalline silicon (Low Temperature Poly-Silicon,
LIPS) the characteristics of high mobility, more and more it is widely studied for developing in illuminating product and panel industry, to reach
The industry requirement of ultra-narrow frame.
For the display panel of ultra-narrow frame, antistatic impact ability be detect one of display panel quality it is important because
Element.In current display panel industry, mainly by adding a circle to be grounded in panel surrounding, drive signal is all wrapped in ground connection
Inside the loop that line is surrounded, when plate carries out antistatic effect test over there, electrostatic can be grounded line loop and discharge, still
Because antistatic impact ability and ground wire apart from the distance on panel border, the width of ground wire and ground wire and signal away from
From directly proportional, the design of ultra-narrow frame can then cause the width of three, and to narrower development, this is also greatly lowered the anti-of panel
Electrostatic impacts ability.
The content of the invention
It is an object of the invention to provide a kind of display panel and display device, for improve ultra-narrow frame display panel and
The antistatic impact ability of display device.
Display panel of the present invention includes viewing area and the non-display area positioned at the viewing area both sides；
The display panel also includes underlay substrate, multiple thin film transistor (TFT), a plurality of touch-control letters on underlay substrate
Number line, the first test signal line region, array base palte horizontal drive circuit, the second test signal line region and ground wire region；
Wherein, there is insulating barrier between the thin film transistor (TFT) and the touching signals line, the thin film transistor (TFT) includes grid
Pole, gate insulator, source electrode and drain electrode；
The non-display area include first side and with the spaced second side in first side；The first test letter
Number line region includes the first side and the second side being oppositely arranged with the first side；In the non-display area, the first side
It is adjacent with first side in the first test signal line region, the second side and the array in the first test signal line region
Formed with the first gap, the array base palte horizontal drive circuit and the second test signal line area between substrate horizontal drive circuit
Formed with the second gap between domain, formed with third space between the ground wire region and the second side；The ground connection
Orthographic projection part part of the line region on the underlay substrate is located at the second test signal line region in the substrate base
In the projection of plate.
Wherein, the second test signal line region is formed at same layer, the ground wire region and institute with the grid
State source electrode and drain electrode is formed at same layer.
Wherein, the second test signal line region is formed at same layer, the ground wire region and institute with the grid
State touching signals line and be formed at same layer.
Wherein, the second test signal line region is formed at same layer, the ground wire area with the source electrode and drain electrode
Domain is formed at same layer with the touching signals line.
Wherein, the second test signal line region is formed at same layer with the grid, and the ground wire region is formed
In the source electrode and the drain electrode overlapping place double-deck with the touching signals line, the source electrode and drain electrode are led to the touching signals line
It is overlapping together to cross drilling short circuit bilayer.
The present invention also provides a kind of display device, and the display device includes above-mentioned display panel.
Wherein, the second test signal line region is formed at same layer, the ground wire region and institute with the grid
State source electrode and drain electrode is formed at same layer.
Wherein, the second test signal line region is formed at same layer, the ground wire region and institute with the grid
State touching signals line and be formed at same layer.
Wherein, the second test signal line region is formed at same layer, the ground wire area with the source electrode and drain electrode
Domain is formed at same layer with the touching signals line.
Wherein, the second test signal line region is formed at same layer with the grid, and the ground wire region is formed
In the source electrode and the drain electrode overlapping place double-deck with the touching signals line, the source electrode and drain electrode are led to the touching signals line
It is overlapping together to cross drilling short circuit bilayer.
A kind of display panel provided by the invention and display device will not influence the final display effect of panel for testing
Test signal line region moves to outside, is overlapped by being grounded region with this partial test signal wire region, in the panel edges
In the case that frame is certain, the distance of increase ground wire region distance closing signal, so as to improve display panel and display device
Antistatic impact ability.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the display panel schematic diagram of the present invention.
Fig. 2 is viewing area side structure schematic diagram described in Fig. 1.
Fig. 3 is the side structure schematic diagram of thin film transistor (TFT) in viewing area described in Fig. 1.
Fig. 4 is non-display area enlarged diagram shown in Fig. 1
Fig. 5 is the side structure schematic diagram of ground wire and the first embodiment of secondary signal p-wire region shown in Fig. 4.
Fig. 6 is the side structure schematic diagram of ground wire and second of region of secondary signal p-wire embodiment shown in Fig. 4.
Fig. 7 is the side structure schematic diagram of ground wire and the third embodiment of secondary signal p-wire region shown in Fig. 4.
Fig. 8 is the side structure schematic diagram of ground wire and the 4th kind of embodiment in secondary signal p-wire region shown in Fig. 4.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
Referring to Fig. 1, the embodiment of the present invention provides a kind of display panel, for improving the antistatic impact of narrow frame panel
Ability.Display panel 100 includes viewing area 10 and non-display area 20.Wherein, the display panel 100 includes and is not limited to low temperature
Polysilicon panel, amorphous silicon face plate and metal oxide panel.
Referring to Fig. 2, the viewing area 10 includes underlay substrate 11, multiple film crystalline substances on the underlay substrate 11
Body pipe 12 (one is only shown in Fig. 2) and a plurality of touching signals line 13.Wherein, the underlay substrate 11 can be glass or thoroughly
Bright plastics, the thin film transistor (TFT) 12 are arranged at intervals on the underlay substrate and arranged with array way.The viewing area is also
Including flatness layer 14 and insulating barrier 15, the flatness layer 14 between the thin film transistor (TFT) 12 and touching signals line 13,
The insulating barrier 15 covers the touching signals line 13.
Referring to Fig. 3, the thin film transistor (TFT) 12 includes：Grid 121, gate insulator 122, source electrode 123 and drain electrode
124, the gate insulator 122 is located between the grid 12 and the source electrode 123 and the drain electrode 133.Wherein, the grid
Pole 121 controls the switch of the thin film transistor (TFT) 12, conducting channel is formed between the source electrode 123 and drain electrode 14, for described
The conductance effect of thin film transistor (TFT) 12.The grid 121, source electrode 123 and drain 124 material be metal, for example, can for copper,
Any individual layer or wherein several laminations in aluminium, copper alloy or aluminium alloy；The material of the gate insulator 122 includes nitrogen
SiClx (SiNx) and silica (SiOx).
It should be noted that for the ease of description, the part knot of the viewing area related to the embodiment of the present invention illustrate only
Structure, rather than the entire infrastructure of the viewing area.
Referring to Fig. 4, the non-display area 20 includes first side 21, second side 22, the first test signal line region
23, array base palte horizontal drive circuit 24, the second test signal line region 25 and ground wire region 26.The first test signal line
Region 23 includes the first side 231 and the second side 232 for being oppositely arranged with the first side, and the of the first test signal line region 23
Side 231 contacts with the second side 21, second side 232 in the first test signal line region 23 and the array base palte
Formed with the first gap 27 between horizontal drive circuit 24；The array base palte row driving 24 and the second test signal line region
Formed with the second gap 28 between 25；Formed with third space 29 between the ground wire region 26 and the second side 22.
Wherein, orthographic projection part of the ground wire region 26 on the underlay substrate 11 is located at the second test signal line region
25 in the projection of the underlay substrate 11..
It is related to the 100 final display effect of display panel that the first test signal line region 23 is used for placement test
Signal signal wire；The second test signal line region 25 is used to place to test finally to be shown with the display panel 100
The signal wire of the unrelated signal of effect (such as array base palte test signal, display panel test signal and touching signals), these
Even if signal by damage by static electricity, also will not the final display effect of counter plate have an impact.The ground wire region 26 is used to put
Ground wire is put, the ground wire region 26 forms loop around the viewing area 10, by the described first test wire size line region
23 and in the array base palte horizontal drive circuit 24 is wrapped in, antistatic impact ability is being carried out to the display panel 100
In test process, electrostatic can be discharged by loop through the ground wire in the ground wire region 26, so as to protect the display surface
Plate 100 is not by damage by static electricity.
In general, the ground wire region 26 drives the distance between 24 A, the ground wire with the array base palte row
The width B in region 26 and the width C of the third space 29 are to influence the weight of the antistatic impact ability of display panel 100
Want factor.In the case where B, C are certain, A is bigger, and the antistatic impact ability of panel is stronger；In the case where A, C are certain, B is got over
Greatly, the antistatic impact ability of panel is stronger；Equally in the case where A, B are certain, C is bigger, and the antistatic impact ability of panel is just
It is stronger, wherein, the influence of the width C of third space 29 to the antistatic impact ability of the display panel 100 is maximum.The present embodiment
In, the second test signal line region 25 for not influenceing display panel test signal line will be placed with and be moved to outside, pass through ground connection
Line region 26 is overlapping with it, now described to be grounded region 26 and the array in the case of certain on the border of display panel
Substrate row drives the distance between 24 A and the width B in the ground wire region 26 not to change, and adds the described 3rd
The width C in gap 29, so as to improve the antistatic impact ability of the display panel 100.
The first embodiment of the present embodiment is that the second test signal line region 25 is formed same with the grid 121
One layer, ground wire region 26 and the source electrode 123 and the formation of drain electrode 124 are in same layer, as shown in Figure 5.
Second of embodiment of the present embodiment is that the second test signal line region 25 is formed at together with the grid 121
One layer, the ground wire region 26 is formed at same layer with the touching signals line 13, as shown in Figure 6.
The third embodiment of the present embodiment is the second test signal line region 25 and the source electrode 123 and drain electrode
124 are formed at same layer, and the ground wire region 26 connection is formed at same layer with the touching signals line 13, as shown in Figure 7.
The 4th kind of embodiment of the present embodiment is that the second test signal line region 25 is formed same with the grid 121
One layer, the ground wire region 26 is formed at the source electrode 123 and drain electrode 124 and the touching signals line 13 is double-deck overlaps
Place.Wherein, the source electrode 123 and drain electrode 124 and the cabling of the touching signals line 13 overlap on one by the short circuit bilayer that drills
Rise, as shown in Figure 8.
Compared with prior art, the present invention will be used to place to test in display panel does not influence the final display effect of panel
Test signal line region is moved to outside, by way of being grounded region and being overlapped with this partial test signal wire region, in institute
State display floater frame it is certain in the case of, add the width on ground wire region and display panel border, it is aobvious so as to improve
Show the antistatic impact ability of panel.
The present invention also provides a kind of display device, and the display device includes above-mentioned display panel 100 and backlight module.Institute
State backlight module and fit in the back side of display panel 100, light source is provided for the display panel 100.
Display device provided by the invention will not influence display panel for placement test in original display panel and finally show
Show that the test signal line region of effect is moved to outside, and ground wire region is overlapped with this partial test signal wire region,
In the case that display floater frame is certain, the width in ground wire region and display panel border is added, so as to improve display
The antistatic impact ability of device.Above disclosure is only preferred embodiment of present invention, can not be limited certainly with this
The interest field of the present invention, one of ordinary skill in the art will appreciate that all or part of flow of above-described embodiment is realized, and
The equivalent variations made according to the claims in the present invention, still fall within and invent covered scope.
Claims (10)
- A kind of 1. display panel, it is characterised in that including：Viewing area and the non-display area positioned at the viewing area both sides；The display panel also include underlay substrate, multiple thin film transistor (TFT)s on the underlay substrate, a plurality of touching signals line, First test signal line region, array base palte horizontal drive circuit, the second test signal line region and ground wire region；Wherein, in viewing area, there are insulating barrier, the film crystal between the thin film transistor (TFT) and the touching signals line Pipe includes grid, gate insulator, source electrode and drain electrode；The non-display area include first side and with the spaced second side in first side；The first test signal line Region includes the first side and the second side being oppositely arranged with the first side；In the non-display area, the first side and institute State that first side in the first test signal line region is adjacent, the second side and the array base palte in the first test signal line region Formed with the first gap between horizontal drive circuit, the array base palte horizontal drive circuit and the second test signal line region it Between formed with the second gap, formed with third space between the ground wire region and the second side；Orthographic projection part of the ground wire region on the underlay substrate is located at the second test signal line region in institute State in the orthographic projection of underlay substrate.
- 2. display panel as claimed in claim 1, it is characterised in that the second test signal line region and the grid shape Into in same layer, the ground wire region same layer is formed at the source electrode and drain electrode.
- 3. display panel as claimed in claim 1, it is characterised in that the second test signal line region and the grid shape Into in same layer, the ground wire region same layer is formed at the touching signals line.
- 4. display panel as claimed in claim 1, it is characterised in that the second test signal line region and the source electrode and Drain electrode is formed at same layer, and the ground wire region is formed at same layer with the touching signals line.
- 5. display panel as claimed in claim 1, it is characterised in that the second test signal line region and the grid shape The source electrode and drain electrode and the overlapping place of touching signals line bilayer, institute are formed at into same layer, the ground wire region State together with source electrode and drain electrode overlap with the touching signals line by the way that the short circuit that drills is double-deck.
- A kind of 6. display device, it is characterised in that including display panel, the display panel, including：Viewing area and positioned at described The non-display area of viewing area both sides；The display panel also includes underlay substrate, multiple thin film transistor (TFT)s on underlay substrate and a plurality of touching signals Line, the first test signal line region, array base palte horizontal drive circuit, the second test signal line region, ground wire region；Wherein, in viewing area, there are insulating barrier, the film crystal between the thin film transistor (TFT) and the touching signals line Pipe includes grid, gate insulator, source electrode and drain electrode；The non-display area include first side and with the spaced second side in first side；The first test signal line region includes the first side and the second side being oppositely arranged with the first side；Positioned at described non-display In area, the first side is adjacent with first side in the first test signal line region, the first test signal line region The second side and the array base palte horizontal drive circuit between formed with the first gap, the array base palte horizontal drive circuit and institute State between the second test signal line region formed with the second gap, between the ground wire region and the second side formed with Third space；Orthographic projection part of the ground wire region on the underlay substrate is located at the second test signal line region in institute State in the orthographic projection of underlay substrate.
- 7. display device as claimed in claim 6, it is characterised in that the second test signal line region and the grid shape Into in same layer, the ground wire region same layer is formed at the source electrode and drain electrode.
- 8. display device as claimed in claim 6, it is characterised in that the second test signal line region with the grid Same layer is formed at, the ground wire region is formed at same layer with the touching signals line.
- 9. display device as claimed in claim 6, it is characterised in that the second test signal line region and the source electrode and Drain electrode is formed at same layer, and the ground wire region is formed at same layer with the touching signals line.
- 10. display device as claimed in claim 6, it is characterised in that the second test signal line region and the grid Same layer is formed at, the ground wire region is formed at the source electrode and drain electrode and the overlapping place of touching signals line bilayer, Together with the source electrode and drain electrode overlap with the touching signals line by the way that the short circuit that drills is double-deck.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710882448.4A CN107491223B (en) | 2017-09-26 | 2017-09-26 | Display panel and display device |
| US15/744,615 US10714509B2 (en) | 2017-09-26 | 2017-12-21 | Display panel and display device |
| PCT/CN2017/117794 WO2019061885A1 (en) | 2017-09-26 | 2017-12-21 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710882448.4A CN107491223B (en) | 2017-09-26 | 2017-09-26 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107491223A true CN107491223A (en) | 2017-12-19 |
| CN107491223B CN107491223B (en) | 2020-02-04 |
Family
ID=60652805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710882448.4A Active CN107491223B (en) | 2017-09-26 | 2017-09-26 | Display panel and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107491223B (en) |
| WO (1) | WO2019061885A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019061885A1 (en) * | 2017-09-26 | 2019-04-04 | 武汉华星光电技术有限公司 | Display panel and display device |
| US10367010B2 (en) | 2017-09-26 | 2019-07-30 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate and display device |
| US10714509B2 (en) | 2017-09-26 | 2020-07-14 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Display panel and display device |
| CN113437128A (en) * | 2021-06-29 | 2021-09-24 | 京东方科技集团股份有限公司 | Display panel narrow frame testing method and display panel |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN107491223B (en) | 2020-02-04 |
| WO2019061885A1 (en) | 2019-04-04 |
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