CN107483868A - Processing method, FPGA and the laser television of VBO signals - Google Patents
Processing method, FPGA and the laser television of VBO signals Download PDFInfo
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- CN107483868A CN107483868A CN201710850200.XA CN201710850200A CN107483868A CN 107483868 A CN107483868 A CN 107483868A CN 201710850200 A CN201710850200 A CN 201710850200A CN 107483868 A CN107483868 A CN 107483868A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Abstract
The embodiment of the present invention provides a kind of processing method, FPGA and the laser television of VBO signals, and this method includes：Parallel signal will be respectively converted into per road VBO signals, clock signal all the way is recovered in the parallel signal of Bing Congmei roads；Multi-path parallel signal is cached respectively；Read operation is performed to all parallel signals of caching based on target clock signal；Wherein, the target clock signal is the clock signal all the way in the multipath clock signal recovered from multi-path parallel signal.Method provided in an embodiment of the present invention and FPGA, it is possible to increase the accuracy that VBO signals transmit between SOC and FPGA, improve the stability of hardware system in laser television.
Description
Technical field
The present embodiments relate to laser television technology field, more particularly to a kind of processing method of VBO signals, FPGA and
Laser television.
Background technology
With the development of Display Technique, 4K TVs are that ultra high-definition TV is very universal.The species of 4K TVs has a lot,
Wherein, 4K laser televisions are a kind of more universal 4K TVs.
Existing 4K laser televisions mainly use " system level chip (System on Chip, abbreviation SOC)+field-programmable
The hardware system of logic gate array (Field Programmable Gate Array, abbreviation FPGA)+lasing light emitter " is realized.
Using Digital Interface Standard (V-by-One, the abbreviation VBO) letter specially developed towards image transmitting between wherein SOC and FPGA
Number it is attached, VBO signals are converted into multi-path parallel signal all the way in FPGA, are individually transmitted per road parallel signal, due to
The problem of propagation delay time between parallel signal be present, the VBO signals inaccuracy that FPGA sides finally obtain so is resulted in, so as to lead
The less stable of cause system, it is easy to the display problems such as flower screen, blank screen occur.
The content of the invention
The embodiment of the present invention provides a kind of processing method, FPGA and the laser television of VBO signals, to improve VBO signals
The accuracy of transmission, improve the stability of hardware system in laser television.
First aspect of the embodiment of the present invention provides a kind of processing method of VBO signals, and this method includes：
Parallel signal will be respectively converted into per road VBO signals, clock signal all the way is recovered in the parallel signal of Bing Congmei roads；
Multi-path parallel signal is cached respectively；
Read operation is performed to all parallel signals of caching based on target clock signal；Wherein, the target clock letter
Number for the clock signal all the way in the multipath clock signal that is recovered from multi-path parallel signal.
Optionally, the deviation of the target clock signal and other road clock signals recovered from multi-path parallel signal
It is minimum.
Optionally, it is described that read operation is performed to all parallel signals of caching based on target clock signal, specifically include：
Bit wide conversion process is performed to all parallel signals of caching；
All parallel signals after bit width conversion is handled are read based on target clock signal.
Second aspect of the embodiment of the present invention provides a kind of FPGA, including：
Memory, for storing computer program；
And processor, for performing the computer program, to perform the method for above-mentioned first aspect.
The third aspect of the embodiment of the present invention provides a kind of FPGA for being handled VBO signals, wherein, the FPGA bags
Include GTP modules, cache module and control parsing module；
The GTP modules are used to that parallel signal will to be respectively converted into per road VBO signals, recover in the parallel signal of Bing Congmei roads
Go out clock signal all the way；
The cache module is used to cache parallel signal；
The control parsing module is used for all parallel signals that caching is read based on target clock signal；
Wherein, the target clock signal be in the multipath clock signal that is recovered from multi-path parallel signal all the way when
Clock signal.
Optionally, the control parsing module is additionally operable to all parallel signals of reading resolving to vision signal.
Optionally, the FPGA also includes bit width conversion module, for performing bit wide to the parallel signal in cache module
Conversion process；
The function of the control parsing module replaces with：Handled for being read based on target clock signal by bit width conversion
All parallel signals afterwards.
Fourth aspect of the embodiment of the present invention provides a kind of laser television, and the laser television is included described in above-mentioned each side
FPGA。
Based on above various aspects, the embodiment of the present invention has the advantages that：
The embodiment of the present invention, it is extensive in the parallel signal of Bing Congmei roads by that will be respectively converted into parallel signal per road VBO signals
Appear again clock signal all the way, cache multi-path parallel signal respectively, during so as to based on the multichannel recovered from multi-path parallel signal
Clock signal all the way in clock signal performs read operation to all parallel signals of caching.Due to being base in the embodiment of the present invention
Clock signal all the way in the multipath clock signal recovered in multi-path parallel signal is carried out to all parallel signals of caching
Read operation, thus, it is possible to due to the difference in transmission time being present between solving each road parallel signal, improve VBO letters
The accuracy of number transmission, and then improves the stability of whole TV hardware system.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is a kind of schematic flow sheet of the processing method for VBO signals that one embodiment of the invention provides；
Fig. 2 is a kind of hardware system structure figure for laser television that one embodiment of the invention provides；
Fig. 3 is a kind of hardware system structure figure for laser television that further embodiment of this invention provides；
Fig. 4 is a kind of hardware system structure figure for laser television that further embodiment of this invention provides；
Fig. 5 is a kind of structural representation for FPGA that one embodiment of the invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The term " comprising " and " having " of description and claims of this specification and their any deformation, it is intended that
Be to cover it is non-exclusive include, for example, the device for the process or structure for containing series of steps is not necessarily limited to clearly arrange
It is that those structures or step for going out but may include are not listed clearly or for the intrinsic other steps of these processes or device
Rapid or structure.
The embodiment of the present invention provides a kind of processing method of VBO signals, and this method can be performed by FPGA, and the FPGA is set
Put in laser television, be attached with the system level chip SOC in laser television hardware system by VBO signals.
Fig. 1 is a kind of schematic flow sheet of the processing method for VBO signals that one embodiment of the invention provides.As shown in figure 1,
The method that the present embodiment provides comprises the following steps：
Step 101, parallel signal will be respectively converted into per road VBO signals, be recovered all the way in the parallel signal of Bing Congmei roads
Clock signal.
In the present embodiment, the FPGA in laser television hardware system can include one or more GTP.Wherein, often
The SOC signals of VBO all the way inputted can be converted to multi-path parallel signal, such as 4 road parallel signals by individual GTP.By VBO signals
After being converted to multi-path parallel signal, GTP can also recover corresponding clock signal from every road parallel signal.
By taking 4K laser televisions (i.e. ultra high-definition laser television) as an example, FPGA includes two in the hardware system of 4K laser televisions
Individual GTP, each GTP are converted to VBO signals all the way 4 road 20bit parallel signal.VBO signals are being converted into multidiameter delay
After signal, recover clock signal all the way from every road parallel signal, two GTP recover 8 tunnel clock signals altogether.Certainly here only
For illustrate rather than to the present invention unique restriction, in fact, FPGA includes a GTP, or more than three GTP feelings
Shape, it is similar with situations of the FPGA including two GTP, repeat no more herein.
Step 102, multi-path parallel signal is cached respectively.
In the present embodiment, every road parallel signal of each GTP outputs is required to be cached.In a kind of possible scheme
In, the corresponding cache module of parallel signal, GTP write after VBO is converted into multi-path parallel signal per road parallel signal all the way
Cached in cache module corresponding to entering, i.e. the quantity of cache module and the quantity of parallel signal is identical.Alternatively possible
Scheme in, parallel signal corresponds to multiple cache modules all the way, now the quantity of cache module be more than parallel signal quantity.
By taking a GTP as an example, it is assumed that a GTP will be converted to 4 road parallel signals by VBO signals all the way, per road parallel signal
A corresponding cache module, i.e. corresponding four cache modules of a GTP, by that analogy, and corresponding eight cache modules of two GTP, n
Individual GTP corresponds to 4n cache module.Certainly it is only for illustrating, rather than unique restriction to the present invention.
Step 103, all parallel signals execution read operation based on target clock signal to caching；Wherein, the mesh
Mark clock signal is the clock signal all the way in the multipath clock signal recovered from multi-path parallel signal.
Optionally, the target clock signal being related in the present embodiment can be the multichannel recovered from multi-path parallel signal
In clock signal in randomly selected clock signal all the way or the clock signal recovered from multi-path parallel signal with
The minimum clock signal all the way of the deviation of other road clock signals.When preferably obtaining target using latter approach in the present embodiment
Clock signal.
As an example it is assumed that FPGA includes a GTP, GTP exports 4 road parallel signals, then recovers from 4 road parallel signals
The selection all the way clock signal minimum with other three roads clock signal deviations is as target clock information number in the clock signal gone out.
If FPGA includes multiple GTP, including two kinds of possible modes：
In a kind of possible mode, a target clock signal is selected for each GTP, wherein defeated from each GTP
Recover the method for target clock signal in the multi-path parallel signal gone out and above-mentioned FPGA include a GTP situation it is identical
Here repeat no more.
In alternatively possible mode, the clock signal that all parallel signals exported recover is changed from all GTP
Target clock signal of the clock signal all the way of middle selection and other road deviations minimums as all GTP.Such as in two GTP
Corotation is changed under the scene of 8 road parallel signals of output, if the clock signal recovered from first via parallel signal with from other 7 tunnels
The deviation of the clock signal recovered in parallel signal is minimum, it is determined that the minimum clock signal of this deviation is believed for target clock
Number.
Further, GTP situation is included for FPGA, it is determined that after target clock signal, based on target
Clock signal performs read operation to all parallel signals cached in cache module, i.e., based on same clock signal to GTP
Every road parallel signal of conversion output performs read operation.Assuming that a GTP conversion 4 road parallel signals of output, then will be based on mesh
Mark clock signal reads the parallel signal of caching from corresponding 4 cache modules.
In the present embodiment, read operation is performed to all parallel signals of caching based on the target clock signal recovered,
Deviation of each road parallel signal of single GTP outputs in transmission time can be effectively corrected, enhances the accurate of signal transmission
Property.
Include multiple GTP situation for FPGA, if recovering a target clock for each GTP in aforementioned process
Signal, the then parallel signal for changing output to each GTP respectively according to target clock signal corresponding to each GTP perform reading behaviour
Make.Explanation is needed exist for, target clock signal corresponding to different GTP may be different.Optionally, if in aforementioned process pin
All GTP are only recovered with a target clock signal, now according to the target clock signal to all GTP change output and
Row signal performs read operation, is able to ensure that the signal between different GTP is synchronous after this treatment.
Alternatively, in the present embodiment, in order that the bit wide for obtaining above-mentioned parallel signal meets FPGA processing requirement, may be used also
To comprise the following steps：
Bit wide conversion process is performed to all parallel signals of caching；
All parallel signals after bit width conversion is handled are read based on target clock signal.
In the present embodiment, VBO signals are converted to 20bit parallel signal, after being cached to it, by parallel signal
Bit wide be converted to 10bit from 20bit, be finally based on target clock signal read 10bit parallel signal.
The present embodiment, by the way that parallel signal will be respectively converted into per road VBO signals, recovered in the parallel signal of Bing Congmei roads
Clock signal all the way, multi-path parallel signal is cached respectively, so as to based on the multipath clock letter recovered from multi-path parallel signal
Clock signal all the way in number performs read operation to all parallel signals of caching.Due to being to be based on multichannel simultaneously in the present embodiment
The reading that clock signal all the way in the multipath clock signal recovered in row signal is carried out to all parallel signals of caching is grasped
Make, thus, it is possible to due to the difference in transmission time be present between solving each road parallel signal, caused by SOC and FPGA it
Between the transmission of VBO signals it is inaccurate the problem of, and then improve the stability of whole TV hardware system.
Fig. 2 is a kind of hardware system structure figure for laser television that one embodiment of the invention provides, as shown in Fig. 2 this is hard
Part system includes SOC and FPGA, and wherein FPGA includes GTP1, cache module and control parsing module Ctl1.Hardware system work
When making, SOC is by VBO signal outputs to GTP1, and GTP1 after VBO signals are received, gone here and there simultaneously by the VBO signals received to it
Conversion process, 4 road parallel signals of output cache module corresponding to are cached, and from 4 road parallel signals of GTP1 outputs
Recover clock signal all the way respectively, then determine that clock signal is believed as target clock all the way from the 4 tunnel clock signals recovered
Number.Preferably, the clock signal minimum with other road clock signal deviations is as target clock signal.Further, control solution
All parallel signals of caching are read in analysis module Ctl1 all cache modules according to corresponding to target clock signal from GTP1.Again
Further, control parsing module Ctl1 is additionally operable to all parallel signals of reading resolving to vision signal.
The specific executive mode and beneficial effect of the present embodiment are similar with Fig. 1 embodiments, repeat no more herein.
Fig. 3 is a kind of hardware system structure figure for laser television that further embodiment of this invention provides, as shown in figure 3,
On the basis of Fig. 2 embodiments, FPGA also includes cache module corresponding to GTP2, GTP2 and control parsing in the hardware system
Module Ctl2.
When hardware system works, 2 road VBO signals are exported and received to GTP1 and GTP2, GTP1 and GTP2 by SOC respectively
After VBO signals, serioparallel exchange processing is carried out to the VBO signals received, and each export 4 road parallel signals and cached corresponding to
Module is cached, and recovers a clock signal in the every road parallel signal exported from GTP1 and GTP2 respectively, then from
Determination of the clock signal as target clock signal, wherein target clock signal all the way is determined in the multipath clock signal recovered
Method is similar with Fig. 2 embodiments to be repeated no more herein.
Further, control and read in parsing module Ctl1 all cache modules according to corresponding to target clock signal from GTP1
Take the parallel signal of caching；Control parsing module Ctl2 all caching moulds according to corresponding to same target clock signal from GTP2
The parallel signal of caching is read in block.Yet further, parsing module Ctl1 and control parsing module Ctl2 are controlled respectively by it
The parallel signal of reading resolves to vision signal.
Those skilled in the art will be appreciated that the present embodiment is that the situation for including two GTP with FPGA is shown
Example explanation, when FPGA includes two or more GTP, it is similar with the situation for including two GTP to perform method for it, no longer superfluous herein
State.
The specific executive mode and beneficial effect of the present embodiment are similar with Fig. 1 embodiments, repeat no more herein.
Fig. 4 is a kind of hardware system structure figure for laser television that further embodiment of this invention provides, as shown in figure 4,
On the basis of Fig. 3 embodiments, FPGA also includes bit width conversion module, turns for performing bit wide to the parallel signal in cache module
Change processing.
Specifically, when hardware system works, SOC exports 2 road VBO signals to GTP1 and GTP2, GTP1 and GTP2 respectively
After VBO signals are received, serioparallel exchange processing is carried out to the VBO signals that receive, and each export 4 road parallel signals to pair
The cache module answered is cached, and recovers a clock signal from every road parallel signal of GTP1 outputs, then from extensive
Determine that clock signal is parallel from every road of GTP2 outputs as first object clock signal all the way in the multipath clock signal appeared again
A clock signal is recovered in signal, then determines that clock signal is as the second mesh all the way from the 4 tunnel clock signals recovered
Mark clock signal, the determination method of wherein first object clock signal and the second target clock signal it is similar with Fig. 2 embodiments
Here repeat no more.
Further, control parsing module Ctl1 according to first object clock signal from all cache modules corresponding to GTP1
The middle parallel signal for reading caching；Control parsing module Ctl2 according to the second target clock signal from all cachings corresponding to GTP2
The parallel signal of caching is read in module.Further, the parallel signal of caching is inputted to bit width conversion module respectively so that
Bit width conversion module carries out bit width conversion processing to it, so that the bit wide of parallel signal meets control parsing module Ctl1 and control
Parsing module Ctl2 processing requirement.
Optionally, in the present embodiment, FPGA (can also not show including monitoring modular, matching module and reseting module in Fig. 4
Go out).
Monitoring modular electrically connects with SOC and control parsing module respectively, the first data of the output signal for obtaining SOC
Parameter, and the second data parameters that monitoring and controlling parsing module parses after output signal is received.
Matching module is used to be matched first data parameters and second data parameters.
Reseting module is used to, when first data parameters and second data parameters mismatch, enter the GTP
Row reset processing.
The present embodiment, by the way that parallel signal will be respectively converted into per road VBO signals, recovered in the parallel signal of Bing Congmei roads
Clock signal all the way, multi-path parallel signal is cached respectively, so as to based on the multipath clock letter recovered from multi-path parallel signal
Clock signal all the way in number performs read operation to all parallel signals of caching.Due to being to be based on multichannel simultaneously in the present embodiment
The reading that clock signal all the way in the multipath clock signal recovered in row signal is carried out to all parallel signals of caching is grasped
Make, thus, it is possible to due to the difference in transmission time be present between solving each road parallel signal, caused by SOC and FPGA it
Between the transmission of VBO signals it is inaccurate the problem of, and then improve the stability of whole TV hardware system.
Fig. 5 is a kind of structural representation for FPGA that one embodiment of the invention provides, as shown in figure 3, the FPGA includes：
Memory, for storing computer program；
And processor, for performing the computer program, to perform the method for the various embodiments described above.
The FPGA that the present embodiment provides can be used in performing the technical scheme of above-described embodiment, its executive mode and beneficial effect
Fruit seemingly repeats no more herein.
A kind of laser television that the embodiment of the present invention also provides.The laser television includes what above-mentioned any embodiment provided
FPGA。
The embodiment of the present invention also provides a kind of non-transitorycomputer readable storage medium, the instruction in the storage medium
By FPGA computing device when so that FPGA processor is able to carry out following method：
Parallel signal will be respectively converted into per road VBO signals, clock signal all the way is recovered in the parallel signal of Bing Congmei roads；
Multi-path parallel signal is cached respectively；
Read operation is performed to all parallel signals of caching based on target clock signal；Wherein, the target clock letter
Number for the clock signal all the way in the multipath clock signal that is recovered from multi-path parallel signal.
The present embodiment, by the way that parallel signal will be respectively converted into per road VBO signals, recovered in the parallel signal of Bing Congmei roads
Clock signal all the way, multi-path parallel signal is cached respectively, so as to based on the multipath clock letter recovered from multi-path parallel signal
Clock signal all the way in number performs read operation to all parallel signals of caching.Due to being to be based on multichannel simultaneously in the present embodiment
The reading that clock signal all the way in the multipath clock signal recovered in row signal is carried out to all parallel signals of caching is grasped
Make, thus, it is possible to due to the difference in transmission time be present between solving each road parallel signal, caused by SOC and FPGA it
Between the transmission of VBO signals it is inaccurate the problem of, and then improve the stability of whole TV hardware system.
It is last it should be noted that one of ordinary skill in the art will appreciate that whole in above-described embodiment method or
Part flow, it is that by computer program the hardware of correlation can be instructed to complete, described program can be stored in a computer
In readable storage medium storing program for executing, the program is upon execution, it may include such as the flow of the embodiment of above-mentioned each method.Wherein, it is described to deposit
Storage media can be disk, CD, read-only memory (ROM) or random access memory (RAM) etc..
Each functional unit in the embodiment of the present invention can be integrated in a processing module or unit
Individually be physically present, can also two or more units be integrated in a module.Above-mentioned integrated module both can be with
Realized, can also be realized in the form of software function module in the form of hardware.If the integrated module is with software
The form of functional module realizes, and computer-readable is deposited as independent production marketing or in use, one can also be stored in
In storage media.Storage medium mentioned above can be read-only storage, disk or CD etc..
Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；Although with reference to foregoing each reality
Example is applied the present invention is described in detail, it will be understood by those within the art that：It still can be to foregoing each
Technical scheme described in embodiment is modified, and either carries out equivalent substitution to which part or all technical characteristic；And
These modifications are replaced, and the essence of appropriate technical solution is departed from the scope of various embodiments of the present invention technical scheme.
Claims (8)
- A kind of 1. processing method of VBO signals, it is characterised in that：Parallel signal will be respectively converted into per road VBO signals, clock signal all the way is recovered in the parallel signal of Bing Congmei roads；Multi-path parallel signal is cached respectively；Read operation is performed to all parallel signals of caching based on target clock signal；Wherein, the target clock signal is Clock signal all the way in the multipath clock signal recovered from multi-path parallel signal.
- 2. according to the method for claim 1, it is characterised in that the target clock signal with it is extensive from multi-path parallel signal The deviation for other road clock signals appeared again is minimum.
- 3. according to the method for claim 1, it is characterised in that it is described based on target clock signal to all parallel of caching Signal performs read operation, specifically includes：Bit wide conversion process is performed to all parallel signals of caching；All parallel signals after bit width conversion is handled are read based on target clock signal.
- A kind of 4. FPGA, it is characterised in that including：Memory, for storing computer program；And processor, for performing the computer program, the method any one of 1-3 is required with perform claim.
- 5. a kind of FPGA for being handled VBO signals, it is characterised in that including GTP modules, cache module and control Parsing module；The GTP modules are used to that parallel signal will to be respectively converted into per road VBO signals, and one is recovered in the parallel signal of Bing Congmei roads Road clock signal；The cache module is used to cache parallel signal；The control parsing module is used for all parallel signals that caching is read based on target clock signal；Wherein, the target clock signal is the letter of clock all the way in the multipath clock signal recovered from multi-path parallel signal Number.
- 6. FPGA according to claim 5, it is characterised in that it is described control parsing module be additionally operable to by reading it is all simultaneously Row signal resolution is vision signal.
- 7. FPGA according to claim 5, it is characterised in that the FPGA also includes bit width conversion module, for slow Parallel signal in storing module performs bit wide conversion process；The function of the control parsing module replaces with：For being read based on target clock signal after bit width conversion is handled All parallel signals.
- 8. a kind of laser television, it is characterised in that including the FPGA as any one of claim 5-7.
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| CN107483868B (en) | 2020-07-07 |
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