CN107481750B - Encoding and decoding method for reducing energy consumption of multilayer spin transfer torque magnetic memory - Google Patents

Abstract

The invention discloses an encoding and decoding method for reducing energy consumption of a multilayer spin transfer torque magnetic memory, and belongs to the technical field of data encoding and decoding. The invention includes encoding and decoding: when encoding occurs in data writing, encoding the cache line data to be written according to the existing cache line data, the flag bit data and the cache line data to be written in the memory bank to generate new cache line data and new flag bit data, and the method mainly comprises the following three steps: reading out data; coding the Hard bit; encoding the Soft bit; the decoding mainly occurs when reading data in a reading request, the data read from the memory bank in the decoding process comprises cache line data with a certain number of bits and flag bit data with a certain number of bits, the proportion of the cache line data and the flag bit data can be determined according to actual requirements, and the data obtained by decoding is the data of one cache line. The invention separately encodes Hard bit and Soft bit of MLC STT-RAM to reduce the number of required state transition HT and ST in the writing process, and can effectively reduce the writing energy consumption of MLC STT-RAM.

Description

Encoding and decoding method for reducing energy consumption of multilayer spin transfer torque magnetic memory

Technical Field

The invention belongs to the technical field of data encoding and decoding, and particularly relates to an encoding and decoding method for reducing energy consumption of a multilayer spin transfer torque magnetic memory.

Background

Spin-transfer torque magnetic memory (STT-RAM) is a nonvolatile memory in which information writing is performed by Spin current. It mainly consists of a gating transistor and a Magnetic Tunnel Junction (MTJ). The gating transistor is used to select the cell for reading and writing to the cell. The magnetic tunnel junction is used to store information. The magnetic tunnel junction is composed of three parts: free layer, insulating layer, reference layer. When a write current is applied to an STT-RAM memory cell, the write current flows through the MTJ and the write process is as shown in FIG. 1. When current flows through the free layer, the current is polarized to form spin polarized current, and the spin polarized current changes the direction of the magnetic field of the free layer to realize information writing. The magnetic field of the reference layer is strong and does not change with the change of the current direction. When a write current is applied from top to bottom, the magnetic moment of the free layer is aligned parallel to the magnetic moment of the reference layer, and the entire MTJ exhibits a low resistance state, typically representing a logic "0". When a write current is applied from bottom to top, the magnetic moment of the free layer is opposite to the magnetic moment of the reference layer, and the entire MTJ exhibits a high resistance state, typically representing a logic "1". STT-RAM has the characteristics of large capacity, low leakage power consumption and nonvolatility, and is likely to replace the traditional Static Random Access Memory (SRAM) technology and be used as the cache of the next generation processor.

Multi-level spin-transfer torque magnetic memory (MLC STT-RAM) refers to STT-RAM capable of storing a two-bit or more bit structure per memory cell. Multi-level cells (MLCs) store multiple bits in one cell and therefore have the advantage of greater capacity than single-level cells (SLCs). The structure of a typical MLC STT-RAM is shown in FIG. 2. MLC STT-RAM is also comprised of access transistors and MTJs. In contrast, in the MLC structure, the free layer of the MTJ has two regions, namely a Hard region (Hard Domain) and a Soft region (Soft Domain). These two regions are used to store two bits of data, respectively. Typically, Hard Domain stores the upper of two bits, which are also called Hard bits (Hard bits). Soft Domain stores the lower of two bits, also called Soft bits (Soft bits).

The writing energy consumption of the MLC STT-RAM is very high and can even reach 10 times of that of the SRAM. When the MLCTT-RAM is applied to the actual processor cache, the advantage of low leakage power consumption can be offset by the characteristic of high writing power consumption. Therefore, reducing the write power consumption of MLC STT-RAM is a very critical issue.

The problem of write disturbance exists in the writing process of the MLC STT-RAM. As the area of the Hard Domain corresponding to the Hard bit is larger than that of the Soft Domain for storing the Soft bit, and the magnetism of the Hard Domain is stronger, when the Hard bit is written, a larger write current needs to be applied, and the write current is enough to change the Soft Domain, so that the Hard bit and the Soft bit are written simultaneously, and the phenomenon is called the writing interference of the MLC STT-RAM. While the write current required for the Soft bit is not sufficient to change the Hard Domain, writing the Soft bit does not disturb the Hard bit. Because of the problem of write disturb between two bits of MLC STT-RAM, its writing process is complicated, and its state transition is shown in FIG. 3.

The state transitions that can be experienced in MLC STT-RAM write operations can be divided into four categories:

zt (zero transition): the MTJ state is unchanged. The value to be written is the same as the value already stored, say 01, and the MLC would have stored 01.

ST (Soft transition): only the Soft bit changes, say 00 to 01, 10 to 11.

HT (hard transition): the Hard bit changes and the Soft bit is written with the Hard bit, e.g., 00 to 11, 01 to 11, 10 to 00, 11 to 00.

TT (two Step transition): two-step transmission, state transition is divided into two steps, such as from 00 to 10, requiring one HT, first from 00 to 11, and then requiring one ST, from 11 to 10.

This writing method based on state transition is obviously different from other MLC nonvolatile memories, such as Phase Change Memory (PCM). The programming scheme for MLC PCM is based on Program-and-Verify. The Program-and-Verify approach first applies a Set or Reset pulse to the cell, and then ensures that the resistance reaches the specified range through multiple iterations of small pulses and reads. This difference in programming makes some encoding schemes that reduce the PCM write power consumption of MLCs unsuitable for the STT-RAM of MLCs.

Existing methods for reducing the write power consumption of MLC STT-RAM can be divided into two categories. One is to form two cache lines of different characteristics by separating two bits of the MLC. A cache line composed of Soft bits has the characteristic of reading slowly and writing quickly, while a cache line composed of Hard bits has the characteristic of reading quickly and writing slowly. Mapping frequently read and written data to Soft bit cache lines and Hard bit cache lines respectively can improve performance and reduce energy consumption. However, in this way, the cache line for writing Hard bit will overwrite the cache line for writing Soft bit, so the cache line for writing Hard bit needs to be rewritten after the cache line for writing Hard bit is completed. The rewriting causes unnecessary overhead of power consumption. The second type is to change the mapping of logical values to resistance values. This approach is based on the property that the write energy consumption of an MLC is very dependent on the value to be written to the cell. This feature is not present in the STT-RAM of MLCs, however, and therefore this approach is not applicable to the STT-RAM of MLCs.

Disclosure of Invention

Aiming at the defects or the improvement requirements of the prior art, the invention provides a coding and decoding method for reducing the energy consumption of a multilayer spin transfer torque magnetic memory, which aims to separately code Hard bit and Soft bit of an MLC STT-RAM, reduce the number of HT by respectively coding the Hard bit and reduce the number of ST by respectively coding the Soft bit, thereby solving the technical problem of high writing energy consumption caused by applying the multilayer spin transfer torque magnetic memory to a system.

To achieve the above object, according to one aspect of the present invention, there is provided a method for encoding and decoding a multilayer spin transfer torque magnetic memory, the method comprising the steps of:

(1) reading old cache line data D and old flag bit T according to the address of the cache line data to be written;

(2) coding the Hard bit, comprising the following sub-steps:

(21) setting cache line data to be written as N, forming all Hard bits of the N into NH, and forming all Soft bits of the N into NS; initializing the digit number of the flag bit to be written to be equal to the digit number of T, wherein the flag bit to be written is all 0, all Hard bits of the flag bit to be written form THN, and all Soft bits of the flag bit to be written form TSN; forming DH by all Hard bits of the D and forming DS by all Soft bits; forming all Hard bits of the T into TH, and forming all Soft bits into TS;

(22) carrying out bitwise XOR on NH and DH to obtain NHXOR, and carrying out bitwise XOR on TH and 0 with the same number of bits to obtain THXOR;

(23) using NHXOR and TH as the input of coding, and coding to obtain the new Hard bit to be written into the zone bit, namely THN ', and the new Hard bit to be written into the cache line data, namely NH';

(3) encoding the Soft bit, comprising the following substeps:

(31) taking out the first bits of NH' and NS to form binary number b of two bits₁b₀The first bit of DH and DS is fetched to form a binary number a of two bits₁a₀，a₁a₀And b₁b₀Performing bit operation:

obtaining a first bit of the new data DS ', and sequentially executing the same operation on each bit of data after the first bit of the NH ', the NS, the DH and the DS to obtain the new data DS ';

(32) taking out the first bits of THN' and TSN to form binary number b of two bits₁b₀The first bit of TH and TS is taken out to form binary number a of two bits₁a₀，a₁a₀And b₁b₀Performing bit operation:

obtaining a first bit of the new data TS ', and sequentially executing the same operation on each bit of data after the first bit of the THN ', the TSN, the TH and the TS to obtain new data TS ';

(33) and (3) taking DS 'and TS' as the input of coding, and coding to obtain the new Soft bit to be written into the zone bit: TSN', the Soft bit of the new data to be written into the cache line: NS';

(4) and forming encoded buffer line data { NH ', NS' }, and encoded flag bits { THN ', TSN' }.

Further, the decoding specifically includes the steps of:

s1, reading the cache line data D and the flag bit T according to the decoding address;

s2, all Hard bits of D form data DH, all Soft bits of D form data DS, all Hard bits of T form data TH, and all Soft bits of T form data TH;

s3 decoding DH and TH to obtain data DH before coding₀Decoding the DS and TS to obtain the data DS before encoding₀，DH₀And DS₀Respectively cache line data D₀Hard bit and Soft bit of (D), for DH₀And DS₀Combining to obtain decoded cache line data { DH₀，DS₀}。

Further, the decoding method of step S3 is the inverse process of the encoding method in step (23) and step (33).

Further, the encoding in the step (23) and the step (33) is specifically FNW encoding, and the decoding in the step S3 is specifically FNW decoding.

Further, the FNW encoding process specifically includes:

initializing a flag bit to be written to be 0, wherein the bit number and the bit number of the old flag bit are both N bits; combining the Nth K bit data to be written into the NxK bit cache line data with the Nth old mark bit to form K +1 bit data; counting the number of 0, if the number of 0 is more than (K +1)/2, setting the Nth position of the mark to be written as 0, otherwise, setting the Nth position of the mark to be written as 1; and sequentially executing the processes on all the cache line data and each bit of zone bit to be written.

Further, the FNW decoding process specifically includes:

reading NxK bits and N bits of old zone bits of old cache line data, wherein Nth K bit data of the cache line corresponds to the Nth zone bit, if the zone bit is 0, the corresponding K bit data does not execute any operation, otherwise, the data of the K bit is executed with negation operation; the above process is performed on all the data in turn.

Generally, compared with the prior art, the technical scheme of the invention has the following technical characteristics and beneficial effects:

(1) according to the technical scheme, Hard bits and Soft bits of the MLC STT-RAM are separately coded, the number of HT is reduced by coding the Hard bits respectively, the number of ST is reduced by coding the Soft bits respectively, and redundant write operation ST and HT are eliminated, so that the write energy consumption of the MLC STT-RAM is reduced;

(2) the invention applies FNW codec method to STT-RAM of MLC, the purpose of traditional application FNW codec method is to reduce bit flipping, the purpose of invention using FNW codec is to reduce state transition, namely number of ST and HT; in addition, the encoding and decoding method which is widely applied to SLC and reduces bit flipping can be extended to the STT-RAM of MLC through the method of the patent, so that the patent provides more optional methods for reducing the STT-RAM of MLC;

(3) the coding and decoding method in the technical scheme of the invention can be realized only by a small amount of bit operations, and the bit operations generate very small delay, so that the coding and decoding method has very little influence on the delay of the read-write operation, and the influence on the system performance can be ignored while the write energy consumption is reduced.

Drawings

FIG. 1 shows the structure and reading and writing of SLC STT-RAM;

FIG. 2 is a block diagram of the MLC STT-RAM;

FIG. 3 is a write process for MLC STT-RAM;

FIG. 4 is a schematic diagram of the encoding and decoding of MLC STT-RAM cache using the encoding and decoding method of the present invention;

FIG. 5 is a diagram illustrating an exemplary embodiment of a coding/decoding method according to the present invention;

FIG. 6 is a flow chart of the FNW encoding process;

fig. 7 is a flow chart of the FNW decoding process.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

As shown in FIG. 4, when a read request is received by a cache formed by MLC STT-RAM, the cache line data is decoded before being output to the read buffer. The inputs to the decoding process are the buffer line data and the flag bit data. And in the decoding stage, Hard bit and Soft bit of the cache line data are distinguished and treated, and the inversion or non-inversion is selected according to the Hard bit and Soft bit of the zone bit respectively. And after the decoding is finished, obtaining the data of one cache line and outputting the data to the read buffer.

When a cache formed by an MLC STT-RAM receives a write request, old cache line data and a flag bit need to be read from the cache according to the address of the write request. And then, encoding the cache line data, the old cache line data and the flag bit contained in the write request to obtain the encoded cache line data and the encoded flag bit. And in the encoding stage, the old cache line data and the Hard bit to be written into the cache line data are encoded together, and then the old cache line data and the Soft bit to be written into the cache line are encoded together.

Fig. 5 is an encoding embodiment. Assume that the cache line data is 8 bits and a flag bit of 2 bits is allocated.

The old 8-bit cache line data D and the old 2-bit flag bit data T are read out first according to the address of the data to be written. The flag bit data to be written is initialized to all 0 s.

The first step is to write the cache line data N and the flag bit data according to the old cache line data and the flag bit data, and encode the Hard bit. Hard bits of old cache line data are organized together as DH ═ 1,0, and Hard bits to be written into cache lines are organized together as NH ═ 0,1,0, 0. Bitwise xoring DH and NH yields NHXOR {1,1,1,0 }. The Hard bit of T is TH ═ 0}, and TH is xored with 0 of 1 bit to obtain THXOR ═ 0 }. The NHXOR and TH are used as FNW encoding inputs, and the Hard bit of the new flag bit to be written, that is, THN '═ {1}, is obtained through encoding, and the Hard bit of the new data to be written, that is, NH' ═ {1,0,1,1}, is obtained.

The second step encodes the Soft bit. Taking out NH' and the first bit of Soft bit (NS) of data to be written to form a binary number b of two bits₁b₀The first bit of DH and DS is taken out to form a binary number a of two bits 1,1₁a₀＝{1,0}，a₁a₀And b₁b₀Performing bit operation:

the first bit 1 of the new data DS ' is obtained, and the same operations as above are performed on each bit of data after the first bits of NH ', NS, DH, and DS in sequence, so that the new data DS ' is {1,1,0,0 }.

Taking out the first bits of THN' and TSN to form binary number b of two bits₁b₀Taking out the first bit of TH and TS to form binary digit a of two bits₁a₀＝{0,0}，a₁a₀And b₁b₀Performing bit operation:

the first bit 1 of the new data TS ' is obtained, and the same operations as above are sequentially performed on each bit of data after the first bits of the THN ', TSN, TH, and TS, so that the new data TS ' is {1 }. And taking DS 'and TS' as the input of FNW codes, and obtaining the Soft bit of a new flag bit to be written by the codes: TSN ═ {1}, Soft bit of new data to be written: NS' ═ {0,1,0,0 }. After encoding, the data to be written is { NH ', NS' } {1,0,0,1,1,0,1,0}, and the flag bit to be written after encoding is { THN ', TSN' } {1,1 }.

The FNW encoding process in the first step is that the total number of 1's in NHXOR and TH is 3, which is greater than (4+1)/2, so that Hard bit of the new flag bit to be written is set to 1, i.e., THN ═ 1 }. And simultaneously, all the Hard bits of the data to be written are turned over to obtain the coded Hard bits of the data to be written, namely NH' ═ 1,0,1,1 }. The FNW encoding process in the second step is similar to the first step.

As shown in fig. 6, the FNW encoding process is:

initializing a flag bit to be written to be 0, wherein the bit number and the bit number of the old flag bit are both N bits; combining the Nth K bit data to be written into the NxK bit data with the Nth old mark bit to form K +1 bit data; counting the number of 0, if the number of 0 is greater than (K +1)/2, setting the Nth position of the mark to be written as 1, otherwise, setting the Nth position of the mark to be written as 0; the above process is performed for all data and each bit of flag bits to be written in sequence.

As shown in fig. 7, the FNW decoding process is:

reading NxK bits of old cache line data and N bits of old flag bits, wherein the Nth K bit data corresponds to the Nth flag bit, if the flag bit is 0, the corresponding K bit data does not execute any operation, otherwise, the data of the K bit is executed with negation operation; the above process is performed on all the data in turn.

It will be appreciated by those skilled in the art that the foregoing is only a preferred embodiment of the invention, and is not intended to limit the invention, such that various modifications, equivalents and improvements may be made without departing from the spirit and scope of the invention.

Claims (6)

1. A coding and decoding method for reducing energy consumption of a multilayer spin transfer torque magnetic memory is characterized in that the coding specifically comprises the following steps:

(1) reading old cache line data D and old flag bit T according to the address of the cache line data to be written;

(2) coding the Hard bit, comprising the following sub-steps:

(21) setting cache line data to be written as N, forming all Hard bits of the N into NH, and forming all Soft bits of the N into NS; initializing the digit number of the flag bit to be written to be equal to the digit number of T, wherein the flag bit to be written is all 0, all Hard bits of the flag bit to be written form THN, and all Soft bits of the flag bit to be written form TSN; forming DH by all Hard bits of the D and forming DS by all Soft bits; forming all Hard bits of the T into TH, and forming all Soft bits into TS;

(22) carrying out bitwise XOR on NH and DH to obtain NHXOR, and carrying out bitwise XOR on TH and 0 with the same number of bits to obtain THXOR;

(23) using NHXOR and TH as the input of coding, and coding to obtain the new Hard bit to be written into the zone bit, namely THN ', and the new Hard bit to be written into the cache line data, namely NH';

(3) encoding the Soft bit, comprising the following substeps:

(31) taking out the first bits of NH' and NS to form binary number b of two bits₁b₀The first bit of DH and DS is fetched to form a binary number a of two bits₁a₀，a₁a₀And b₁b₀Performing bit operation:

obtaining a first bit of the new data DS ', and sequentially executing the same operation on each bit of data after the first bit of the NH ', the NS, the DH and the DS to obtain the new data DS ';

(32) taking out the first bits of THN' and TSN to form binary number b of two bits₁b₀The first bit of TH and TS is taken out to form binary number a of two bits₁a₀，a₁a₀And b₁b₀Performing bit operation:

obtaining a first bit of the new data TS ', and sequentially executing the same operation on each bit of data after the first bit of the THN ', the TSN, the TH and the TS to obtain new data TS ';

(33) and (3) taking DS 'and TS' as the input of coding, and coding to obtain the new Soft bit to be written into the zone bit: TSN', the Soft bit of the new data to be written into the cache line: NS';

(4) and forming encoded buffer line data { NH ', NS' }, and encoded flag bits { THN ', TSN' }.

2. The encoding and decoding method for reducing the energy consumption of the multilayer spin-transfer torque magnetic memory according to claim 1, wherein the decoding specifically comprises the following steps:

s1, reading the cache line data D and the flag bit T according to the decoding address;

s2, all Hard bits of D form data DH, all Soft bits of D form data DS, all Hard bits of T form data TH, and all Soft bits of T form data TH;

s3 decoding DH and TH to obtain data DH before coding₀Decoding the DS and TS to obtain the data DS before encoding₀，DH₀And DS₀Respectively cache line data D₀Hard bit and Soft bit of (D), for DH₀And DS₀Combining to obtain decoded cache line data { DH₀，DS₀}。

3. The encoding and decoding method for reducing the power consumption of the multi-layer spin-transfer torque magnetic memory according to claim 2, wherein the decoding method of step S3 is the inverse of the encoding method of step (23) and step (33).

4. The encoding and decoding method for reducing the energy consumption of the multi-layer spin-transfer torque magnetic memory as claimed in claim 2, wherein the encoding in the steps (23) and (33) is specifically FNW encoding, and the decoding in the step S3 is specifically FNW decoding.

5. The encoding and decoding method for reducing the energy consumption of the multilayer spin-transfer torque magnetic memory according to claim 4, wherein the FNW encoding process is specifically as follows:

initializing a flag bit to be written to be 0, wherein the bit number and the bit number of the old flag bit are both N bits; combining the Nth K bit data to be written into the NxK bit cache line data with the Nth old mark bit to form K +1 bit data; counting the number of 0, if the number of 0 is more than (K +1)/2, setting the Nth position of the mark to be written as 0, otherwise, setting the Nth position of the mark to be written as 1; and sequentially executing the processes on all the cache line data and each bit of zone bit to be written.

6. The encoding and decoding method for reducing the energy consumption of the multilayer spin-transfer torque magnetic memory according to claim 4, wherein the FNW decoding process is specifically as follows:

reading NxK bits and N bits of old zone bits of old cache line data, wherein Nth K bit data of the cache line corresponds to the Nth zone bit, if the zone bit is 0, the corresponding K bit data does not execute any operation, otherwise, the data of the K bit is executed with negation operation; the above process is performed on all the data in turn.

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