CN107481750A - A kind of decoding method for reducing multilayer spin-transfer torque magnetic memory energy consumption - Google Patents
A kind of decoding method for reducing multilayer spin-transfer torque magnetic memory energy consumption Download PDFInfo
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Abstract
The invention discloses the decoding method for reducing multilayer spin-transfer torque magnetic memory energy consumption, belong to data encoding and decoding technique field.The present invention includes coding and decoding：Coding occurs when writing data, needed during coding according to existing cache line data, flag bit data and the cache line data that will be write in memory bank, new cache line data and new flag bit data are generated to the cache line data coding that will be write, mainly include three steps：Read data；Hard bit are encoded；Soft bit are encoded；When decoding occurs mainly in read request reading data, the flag bit data of cache line data and certain digit of the packet read in decoding process from memory bank containing certain digit, their ratio can determine that the data for decoding to obtain are the data of a cache lines according to the actual requirements.MLC STT RAM Hard bit and Soft bit is encoded separately status change HT and ST required during reduction is write quantity by the present invention, and can effectively reduce MLC STT RAM writes energy consumption.
Description
Technical field
The invention belongs to data encoding and decoding technique field, reduces multilayer spin-transfer torque magnetic more particularly, to one kind and deposits
The decoding method of reservoir energy consumption.
Background technology
Spin-transfer torque magnetic memory (STT-RAM, Spin-transfer torque magnetic random
Access memory) it is a kind of nonvolatile storage that information write-in is realized by spinning current.It is mainly brilliant by a gating
Body pipe and magnetic tunnel-junction (MTJ, a Magnetic Tunnel Junction) composition.Gating transistor is used for choosing this list
Member, so as to which this unit is read and write.Magnetic tunnel-junction is used for storage information.Magnetic tunnel-junction is made up of three parts：Free layer,
Insulating barrier, reference layer.When applying write current to a STT-RAM memory cell, this write current can flow through MTJ, write process
As shown in Figure 1.When electric current flows through free layer, electric current can be polarized to form spin polarized current, and spin polarized current can change certainly
By the magnetic direction of layer, the write-in of information is realized.The magnetic field of reference layer is very strong, will not change with the change of the sense of current.
When applying a write current from the top down, the magnetic moment direction of free layer can be parallel with the magnetic moment direction of reference layer in the same direction, this
When whole MTJ low-resistance state is presented, be generally used to represent logical value " 0 ".When applying a write current from the bottom up,
The magnetic moment direction of free layer can be parallel with the magnetic moment direction of reference layer reverse, and now high-resistance state is presented in whole MTJ, typically
For representing logical value " 1 ".STT-RAM has Large Copacity, low drain electrical power consumed and non-volatile characteristic, it is likely that substitutes traditional
Static RAM (SRAM, Static Random Access Memory) technology, it is slow as processor of future generation
Deposit.
Multilayer spin-transfer torque magnetic memory (MLC STT-RAM) refers to that each memory cell can store two or more
The STT-RAM of more bit architectures.Compared to single layer cell (SLC), multilevel-cell (MLC) stores multidigit in a unit, therefore has
The advantage of more Large Copacity.Typical MLC STT-RAM structure is as shown in Figure 2.MLC STT-RAM are equally by access transistor
Formed with MTJ.Unlike, in MLC structure, MTJ free layer has two regions, i.e., hard area domain (Hard Domain) and
Soft zone domain (Soft Domain).The two regions are respectively intended to the data of storage two.General Hard Domain store two
In a high position, while this position is also called hard position (Hard bit).Soft Domain store the low level in two, and this position is also referred to as
Soft bit (Soft bit).
MLC STT-RAM to write energy consumption very high, it might even be possible to reach 10 times of SRAM.MLCSTT-RAM is applied to reality
When in processor cache, its characteristic for writing high energy consumption can offset the advantage of low drain electrical power consumed.Therefore reduce MLC STT-RAM's
Write the problem of energy consumption is one very crucial.
The problem of writing interference during the writing of MLC STT-RAM be present.Due to Hard Domain phases corresponding to Hard bit
Soft Domain areas than storing Soft bit are bigger, magnetic is stronger, need to apply when row write is entered to Hard bit
Larger write current, this write current are enough to change Soft Domain, so as to cause Hard bit and Soft bit quilts simultaneously
Write, what this phenomenon was referred to as MLC STT-RAM writes interference.And the write current that Soft bit need is not enough to change Hard
Domain, Soft bit are write without interference with Hard bit.Because the problem of writing interference between two of MLC STT-RAM be present,
It writes that process is more complicated, and its status change is as shown in Figure 3.
The status change that may be undergone in MLC STT-RAM write operations can be divided into four kinds：
ZT(Zero Transition)：MTJ states are unchanged.The value to be write as stored value, such as
Write that 01, MLC stored originally is exactly 01.
ST(Soft Transition)：Only Soft bit change, for example 00 is changed into 01,10 and is changed into 11.
HT(Hard Transition)：Hard bit change, at the same Soft bit can with writing for Hard bit and
Also write, for example 00 is changed into 11,01 and is changed into 11,10 and is changed into 00,11 being changed into 00.
TT(Two Step Transition)：Two steps are transmitted, and status change is divided into two steps, for example, from 00 be changed into 10, it is necessary to
HT, is changed into 11 from 00 first, then also needs to a ST, is changed into 10 from 11.
It is this based on the writing mode of status change with other MLC nonvolatile storages, such as phase transition storage
(PCM, Phase Change Memory) has obvious different.MLC PCM programming mode is to be based on Program-and-
Verify.Program-and-Verify mode applies a Set or Reset pulse to unit first, then passes through
The small pulse and reading of multiple iteration, to ensure that resistance has reached defined scope.The difference of so programming mode causes
The coded system that reduction MLC PCM writes energy consumption does not apply to MLC STT-RAM.
The method that existing reduction MLC STT-RAM write energy consumption can be divided into two classes.One kind is by by two points of MLC
Open, separately constitute the cache lines of two different qualities.The cache lines being made up of Soft bit, which have, to be read to write fast characteristic slowly, and
The cache lines of Hard bit compositions, which have, to be read to write slow characteristic soon.The frequent data read and frequently write are respectively mapped to by Soft
Bit cache lines and Hard bit cache lines can reduce energy consumption with improving performance.But in this mode, write Hard bit
Cache lines can cover the cache lines for writing Softbit, therefore write Hard bit cache lines complete after need to Soft bit
Cache lines rewrite.Rewriting can cause unnecessary energy consumption expense.Second class is the mapping relations for changing logical value to resistance.This
Kind of method is the characteristic based on " MLC write energy consumption very related to the value for being written to unit ".But this characteristic is in MLC
STT-RAM in be not present, therefore this method is not suitable for MLC STT-RAM.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the invention provides one kind to reduce multilayer spin-transfer torque magnetic
The decoding method of memory energy consumption, its object is to which MLC STT-RAM Hard bit and Soft bit is encoded separately, lead to
Cross and Hard bit are encoded respectively to reduce HT quantity, Soft bit are encoded to reduce ST quantity, thus solved respectively
Multilayer spin-transfer torque magnetic memory applications cause the high technical problem for writing energy consumption in system.
To achieve the above object, according to one aspect of the present invention, there is provided one kind reduces multilayer spin-transfer torque magnetic and deposited
The decoding method of reservoir energy consumption, the coding specifically include following steps：
(1) old cache line data D and old flag bit T is read according to the address of cache line data to be written；
(2) Hard bit are encoded, including following sub-step：
(21) cache line data being written into is set to N, N all Hard bit is formed into NH, by N all Soft
Bit forms NS；The digit for initializing flag bit to be written is equal to T digit, and flag bit to be written is full 0, flag bit to be written
All Hard bit composition THN, flag bit to be written all Soft bit composition TSN；D all Hard bit are formed
DH, all Soft bit form DS；T all Hard bit are formed into TH, all Soft bit form TS；
(22) NH and DH step-by-step XORs are obtained into NHXOR, TH obtains THXOR with 0 XOR of identical digit；
(23) input using NHXOR and TH as coding, coding obtain the Hard bit of new flag bit to be written, i.e.,
THN ', the Hard bit, i.e. NH ' of new cache line data to be written；
(3) Soft bit are encoded, including following sub-step：
(31) by NH ' and NS first taking-up, the binary number b of composition two1b0, first of DH and DS is taken out,
The binary number a of composition two1a0, a1a0With b1b0Perform bit arithmetic：
Obtain first of new data DS ', successively to after NH ', NS, DH and DS first each data perform more than
Identical operates, and obtains new data DS '；
(32) by THN ' and TSN first taking-up, the binary number b of composition two1b0, first of TH and TS is taken
Go out, the binary number a of composition two1a0, a1a0With b1b0Perform bit arithmetic：
Obtain first of new data TS ', successively to after THN ', TSN, TH and TS first each data perform with
Upper identical operation, obtains new data TS '；
(33) using DS ' and TS ' as the input of coding, encode and obtain the Soft bit of new flag bit to be written：TSN ',
The Soft bit of new cache line data to be written：NS’；
(4) cache line data { NH ', NS ' } after composition coding, flag bit after coding THN ', TSN ' }.
Further, the decoding specifically includes following steps：
S1 reads cache line data D and flag bit T according to decoding address；
S2 is by D all Hard bit composition data DH, by D all Soft bit composition data DS, by all of T
Hard bit composition data TH, by T all Soft bit composition datas TH；
S3 decodes the data DH before being encoded to DH and TH0, the data DS before being encoded is decoded to DS and TS0,
DH0And DS0Respectively cache line data D0Hard bit and Soft bit, to DH0And DS0It is combined, obtains decoded
Cache line data { DH0, DS0}。
Further, the coding/decoding method of the step S3 is the inverse process of coding method in step (23) and step (33).
Further, the coding in the step (23) and step (33) is specially that FNW is encoded, the decoding tool in step S3
Body decodes for FNW.
Further, the FNW cataloged procedures are specially：
The flag bit being written into is initialized as 0, and the digit of digit and old flag bit is all N positions；It is written into N × K
N-th K position data in the cache line data of position are combined with the old flag bit in N positions, the data of composition K+1 positions；Statistics wherein 0
Number, if 0 number is more than (K+1)/2, the nth position for the mark being written into is 0, the mark being otherwise written into
Nth position is 1；The flag bit to be written to all cache line datas and every performs above procedure successively.
Further, the FNW decoding process is specially：
Read old cache line data N × K positions and old flag bit N positions, the corresponding N positions of n-th K positions data of cache lines
Flag bit, if the flag bit is 0, the data of corresponding K positions do not perform any operation, and the otherwise data execution to K positions negates
Operation；Above procedure is performed to all data successively.
In general, by the contemplated above technical scheme of the present invention compared with prior art, have following technology special
Sign and beneficial effect：
(1) MLC STT-RAM Hard bit and Soft bit is encoded separately by technical solution of the present invention, by right respectively
Hard bit codings reduce HT quantity, Soft bit are encoded respectively to reduce ST quantity, the write operation ST of redundancy and
HT is eliminated, therefore MLC STT-RAM energy consumption of writing reduces；
(2) FNW decoding methods are applied to MLC STT-RAM by the present invention, and tradition applies the mesh of FNW decoding methods
Be to reduce bit flipping, the present invention is to reduce the quantity of status change, i.e. ST and HT using the purposes of FNW encoding and decoding；This
Outside, being widely used in reducing the decoding method of bit flipping above SLC can be expanded to MLC's by the method for this patent
STT-RAM, therefore this patent provides more optional methods to reduce MLC STT-RAM；
(3) decoding method in technical solution of the present invention only needs a small amount of bit arithmetic to can be achieved, these bit arithmetics
The delay of very little is produced, thus the encoding and decoding of the present invention are very little to the delayed impact of read-write operation, and energy consumption is write reducing
Simultaneously systematic function is influenceed also to can be neglected.
Brief description of the drawings
Structure and the read-write that Fig. 1 is SLC STT-RAM；
Fig. 2 is MLC STT-RAM structure chart；
Fig. 3 writes process for MLC STT-RAM's；
Fig. 4 is the encoding and decoding schematic diagram cached using the MLC STT-RAM of decoding method of the present invention；
Fig. 5 is the specific implementation example of decoding method of the present invention；
Fig. 6 is FNW cataloged procedure flow charts；
Fig. 7 is FNW decoding process flow charts.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below that
Conflict can is not formed between this to be mutually combined.
As shown in figure 4, when the caching being made up of MLC STT-RAM receives read request, cache line data is being output to reading
Decoding can be passed through before buffering.The input of decoding process is cache line data and flag bit data.Decoding stage, cache line data
Hard bit and Soft bit be distinguished and treat, respectively according to Hard bit and the Soft bit of flag bit come select upset or
Person does not overturn.After decoding terminates, obtain the data of a cache lines and be output in reading buffering.
When the caching being made up of MLC STT-RAM receives write request, it is necessary to be read according to the address of write request from caching
Take out old cache line data and flag bit.Then the cache line data included to write request, old cache line data, flag bit
Encoded to obtain and encode later cache line data and flag bit.Coding stage, old cache line data and caching to be written
The Hard bit of row data are encoded together, and then old cache line data and the Soft bit of cache lines to be written are encoded together.
Fig. 5 is encoding embodiments.Assuming that cache line data is 8, and it is assigned with the flag bit of 2.
8 old cache line data D and 2 old bit flag position data T are read according to the address of data to be written first.Treat
It is full 0 to write flag bit data initialization.
The first step is according to old cache line data and flag bit data, and cache line data N to be written and flag bit data are right
Hard bit are encoded.The Hard bit tissues of old cache line data are to being DH={ 1,0,1,0 } together, caching to be written
It is together NH={ 0,1,0,0 } that capable Hard bit tissues, which arrive,.NHXOR={ 1,1,1,0 } is obtained to DH and NH step-by-step XORs.T
Hard bit be TH={ 0 }, 0 XOR of TH and 1 obtains THXOR={ 0 }.Encoded using NHXOR and TH as FNW defeated
Enter, coding obtains the Hard bit of new flag bit to be written, i.e. THN '={ 1 }, obtains the Hard of new data to be written
Bit, i.e. NH '={ 1,0,1,1 }.
Second step encodes to Soft bit.First of NH ' and the Soft bit (NS) of data to be written is taken out,
The binary number b of composition two1b0={ 1,1 }, by DH and DS first taking-up, the binary number a of composition two1a0=1,
0 }, a1a0With b1b0Perform bit arithmetic：
Obtain first 1 of new data DS ', successively to after NH ', NS, DH and DS first each data perform with
Upper identical operation, obtains new data DS '={ 1,1,0,0 }.
By THN ' and TSN first taking-up, the binary number b of composition two1b0={ 1,0 }, by first of TH and TS
Take out, the binary number a of composition two1a0={ 0,0 }, a1a0With b1b0Perform bit arithmetic：
First 1 of new data TS ' is obtained, each data after THN ', TSN, TH and TS first are performed successively
Above identical operates, and obtains new data TS '={ 1 }.Using DS ' and TS ' as the input of FNW codings, encode and obtain new treat
Write the Soft bit of flag bit：TSN '={ 1 }, the Soft bit of new data to be written：NS '={ 0,1,0,0 }.Encode it
Data to be written afterwards are { NH ', NS ' }={ 1,0,0,1,1,0,1,0 }, and flag bit to be written is { THN ', TSN ' } after coding
={ 1,1 }.
FNW cataloged procedures in the first step are that 1 sum is 3 in input NHXOR and TH, more than (4+1)/2, therefore will
The Hard bit of new flag bit to be written are set to 1, i.e. THN '={ 1 }.The Hard bit of data to be written are all overturn simultaneously,
Obtain the Hard bit of data to be written after encoding, i.e. NH '={ 1,0,1,1 }.FNW cataloged procedures and first in second step
Walk similar.
As shown in fig. 6, FNW cataloged procedures are：
The flag bit being written into is initialized as 0, and the digit of digit and old flag bit is all N positions；It is written into N × K
N-th K position data in the data of position are combined with the old flag bit in N positions, the data of composition K+1 positions；Of statistics wherein 0
Number, if 0 number is more than (K+1)/2, the nth position for the mark being written into is 1, the N for the mark being otherwise written into
Position is 0；The flag bit to be written to all data and every performs above procedure successively.
As shown in fig. 7, FNW decoding process is：
Old cache line data N × K positions and old flag bit N positions are read, n-th K positions data correspond to N bit flags position,
If the flag bit is 0, the data of corresponding K positions do not perform any operation, otherwise perform inversion operation to the data of K positions；According to
It is secondary that above procedure is performed to all data.
Above content as it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention,
It is not intended to limit the invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc.,
It should be included in the scope of the protection.
Claims (6)
1. a kind of decoding method for reducing multilayer spin-transfer torque magnetic memory energy consumption, it is characterised in that the coding is specific
Comprise the following steps：
(1) old cache line data D and old flag bit T is read according to the address of cache line data to be written；
(2) Hard bit are encoded, including following sub-step：
(21) cache line data being written into is set to N, N all Hard bit is formed into NH, by N all Soft bit groups
Into NS；The digit for initializing flag bit to be written is equal to T digit, and flag bit to be written is full 0, and flag bit to be written owns
Hard bit form THN, all Soft bit compositions TSN of flag bit to be written；D all Hard bit are formed into DH, institute
DS is formed by Soft bit；T all Hard bit are formed into TH, all Soft bit form TS；
(22) NH and DH step-by-step XORs are obtained into NHXOR, TH obtains THXOR with 0 XOR of identical digit；
(23) input using NHXOR and TH as coding, coding obtain the Hard bit of new flag bit to be written, i.e. THN ',
The Hard bit, i.e. NH ' of new cache line data to be written；
(3) Soft bit are encoded, including following sub-step：
(31) by NH ' and NS first taking-up, the binary number b of composition two1b0, by DH and DS first taking-up, composition
The binary number a of two1a0, a1a0With b1b0Perform bit arithmetic：
First of new data DS ' is obtained, each data after NH ', NS, DH and DS first are performed successively identical above
Operation, obtain new data DS '；
(32) by THN ' and TSN first taking-up, the binary number b of composition two1b0, by TH and TS first taking-up, group
Into the binary number a of two1a0, a1a0With b1b0Perform bit arithmetic：
First of new data TS ' is obtained, above phase is performed to each data after THN ', TSN, TH and TS first successively
Same operation, obtains new data TS '；
(33) using DS ' and TS ' as the input of coding, encode and obtain the Soft bit of new flag bit to be written：TSN ', new
The Soft bit of cache line data to be written：NS’；
(4) cache line data { NH ', NS ' } after composition coding, flag bit after coding THN ', TSN ' }.
2. a kind of decoding method for reducing multilayer spin-transfer torque magnetic memory energy consumption according to claim 1, it is special
Sign is that the decoding specifically includes following steps：
S1 reads cache line data D and flag bit T according to decoding address；
S2 is by D all Hard bit composition data DH, by D all Soft bit composition data DS, by T all Hard
Bit composition data TH, by T all Soft bit composition datas TH；
S3 decodes the data DH before being encoded to DH and TH0, the data DS before being encoded is decoded to DS and TS0, DH0
And DS0Respectively cache line data D0Hard bit and Soft bit, to DH0And DS0It is combined, obtains decoded slow
Deposit row data { DH0, DS0}。
3. according to a kind of decoding method of reduction multilayer spin-transfer torque magnetic memory energy consumption described in claim 1 or 2,
Characterized in that, the coding/decoding method of the step S3 is the inverse process of coding method in step (23) and step (33).
4. according to a kind of decoding method of reduction multilayer spin-transfer torque magnetic memory energy consumption described in claim 1 or 2,
Characterized in that, the coding in the step (23) and step (33) is specially FNW codings, the decoding in step S3 is specially
FNW is decoded.
5. a kind of decoding method for reducing multilayer spin-transfer torque magnetic memory energy consumption according to claim 4, it is special
Sign is that the FNW cataloged procedures are specially：
The flag bit being written into is initialized as 0, and the digit of digit and old flag bit is all N positions；N × K positions are written into delay
The n-th K position data deposited in row data are combined with the old flag bit in N positions, the data of composition K+1 positions；Of statistics wherein 0
Number, if 0 number is more than (K+1)/2, the nth position for the mark being written into is 0, the N for the mark being otherwise written into
Position is 1；The flag bit to be written to all cache line datas and every performs above procedure successively.
6. a kind of decoding method for reducing multilayer spin-transfer torque magnetic memory energy consumption according to claim 4, it is special
Sign is that the FNW decoding process is specially：
Read old cache line data N × K positions and old flag bit N positions, the corresponding N bit flags of n-th K positions data of cache lines
Position, if the flag bit is 0, the data of corresponding K positions do not perform any operation, otherwise perform inversion operation to the data of K positions；
Above procedure is performed to all data successively.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109036491A (en) * | 2017-06-09 | 2018-12-18 | 台湾积体电路制造股份有限公司 | The detection method and detection system and storage system of address decoding error |
| CN109036491B (en) * | 2017-06-09 | 2021-05-11 | 台湾积体电路制造股份有限公司 | Method and system for detecting address decoding error and memory system |
| CN110007855A (en) * | 2019-02-28 | 2019-07-12 | 华中科技大学 | A kind of the 3D stacking NVM internal storage data compression method and system of hardware supported |
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