WO2018192488A1

WO2018192488A1 - Data processing method and apparatus for nand flash memory device

Info

Publication number: WO2018192488A1
Application number: PCT/CN2018/083355
Authority: WO
Inventors: 王凤海; 杨骥; 张建涛; 夏杰旭; 王嵩
Original assignee: 北京紫光得瑞科技有限公司
Priority date: 2017-04-17
Filing date: 2018-04-17
Publication date: 2018-10-25
Also published as: CN107102820A; CN107102820B

Abstract

Disclosed are a data processing method and apparatus for an NAND flash memory device, wherein the method comprises: when a data write-in request command sent by a host is received, determining a page, corresponding to block data to be processed, in a storage unit to be operated of the NAND flash memory device (S11); according to the type of page and a data characteristic of the block data to be processed, carrying out, according to a pre-set rule, a complementary operation for the block data to be processed, and identifying a data processing mode for a metadata area of the corresponding page of the storage unit to be operated (S12); and encoding the processed block data to be processed, and writing the encoded data into the storage unit to be operated (S13). According to the data processing method and apparatus for the NAND flash memory device, the data error occurrence probability of the NAND flash memory device can be effectively reduced, and the overall performance of the NAND flash memory device is improved.

Description

Data processing method and device for NAND flash memory device

Technical field

The present invention relates to the field of data storage technologies, and in particular, to a data processing method and apparatus for a NAND flash memory device.

Background technique

Compared with traditional mechanical hard drives, SSDs have a qualitative leap in access speed. The MLC NAND flash memory device can greatly increase the storage density of the memory and reduce the storage cost by applying the MLC NAND flash memory to the solid state hard disk. MLC NAND refers to NAND flash memory of Multi-Level Cell. If a memory cell of NAND flash memory only stores one bit of data, it is called SLC (Single-Level Cell) NAND flash memory. If it can store 2 bits of data, it is called CMOS flash memory of multi-level cell (MLC), if it can store 3 One bit of data, called a three-level cell (TLC) NAND flash. However, since multi-bit data is stored in one memory unit of the MLC NAND flash memory device, the probability of data error is greatly increased. In particular, as the process size is reduced to less than 20 nm, the amount of charge stored in the floating gate layer is reduced, and the thickness of the oxide layer is smaller, the charge stored in the floating gate layer is more likely to escape, resulting in data retention errors. The probability is greatly improved.

At present, the methods for reducing data errors of MLC NAND flash memory devices in the prior art mainly include the following:

Use error correction techniques such as BCH/LDPC. They are general-purpose data error correction techniques that do not require knowledge of the principles and mechanisms of error generation and can be used for data errors in any scenario. This method requires some redundancy bits to encode the original data. If the number of errors in the flash memory is more, the more redundant bits are needed, and these redundant bits need to occupy the storage space of the flash memory, so the data that the user can store is reduced. There are two main types of data error in NAND flash: one is data interference error and the other is data retention error. In today's process sizes, the probability of data retention errors is much greater than data interference errors. Therefore, BCH/LDPC is a general-purpose data error correction technique that cannot exploit the difference in probability to reduce the probability of errors.

Asymmetric coding technology. This technique reduces data retention errors by changing the input data pattern and reducing the probability of data with higher threshold voltages. This method has a good effect on data retention errors, but it is ineffective for data interference errors and may even increase data interference errors. The scheme adds a flag for every 16 bits of data to identify whether the 16 bits are 0 or more. The flag also needs to be stored in the NAND flash, so the space cost of this encoding is 6.25%. If asymmetric coding is used alone, the space cost is not too great for SSDs. However, since this coding algorithm only targets data reservation errors and is ineffective for interference errors, it is necessary to use the common BCH/LDPC error correction technique at the same time, so that the space cost of the asymmetric coding algorithm is 6.3%, which is extra for the BCH/LDPC redundancy code. The added cost is hard to accept.

Therefore, how to provide a data processing method capable of effectively reducing the probability of occurrence of data errors in a NAND flash memory device is a technical problem to be solved at present.

Summary of the invention

The invention provides a data processing method and device for a NAND flash memory device, which can effectively reduce the probability of data error occurrence of the NAND flash memory device and improve the overall performance of the NAND flash memory device.

In order to solve the above technical problem, the present invention adopts the following technical solutions:

One aspect of the present invention provides a data processing method for a NAND flash memory device, the method comprising:

Receiving a data write request command sent by the host, determining that the to-be-processed block data is in a corresponding Page page in the to-be-operated storage unit of the NAND flash memory device;

Determining the to-be-processed block data according to a preset rule according to a type of the page page and a data feature of the to-be-processed block data, and performing data processing on the metadata area corresponding to the Page page of the to-be-operated storage unit Identification

The processed block data to be processed is encoded, and the encoded coded data is written into the to-be-operated memory unit.

Optionally, the method further includes:

A corresponding metadata area is set in advance for each of the NAND flash memory devices, and the metadata area is used to identify a data processing manner corresponding to data written to different Page pages of the storage unit.

Optionally, the inversion operation is performed on the to-be-processed block data according to a type of the page page and the data feature of the to-be-processed block data, and the metadata of the page page corresponding to the to-be-operated storage unit is The identification of the data processing mode of the area, including:

When the Page page is a lower page, determining whether the number of 0s in the to-be-processed block data is greater than 1; if yes, inverting data corresponding to each bit in the to-be-processed block data The operation is performed, and the data processing mode identifier corresponding to the inverse operation is written in the metadata area corresponding to the Page page of the to-be-operated storage unit; otherwise, the encoding operation is performed on the to-be-processed block data.

When the Page page is an upper page page, determining whether the number of 1 in the to-be-processed block data is greater than 0; if yes, inverting data corresponding to each bit in the to-be-processed block data The operation is performed, and the data processing mode identifier corresponding to the inverse operation is written in the metadata area corresponding to the Page page of the to-be-operated storage unit; otherwise, the encoding operation is performed on the to-be-processed block data.

Optionally, after the encoded encoded data is written into the to-be-operated storage unit, the method further includes:

When receiving the data read request command sent by the host, reading the target data from the Page page of the storage unit to be operated, and decoding the target data;

Obtaining the identification information in the metadata area corresponding to the Page page of the target data;

Determining whether the identification information is a data processing mode identifier corresponding to the inverse operation, and if so, inverting the data corresponding to each bit in the decoded block data, and transmitting the obtained block data to the host, Otherwise, the decoded block data is directly transmitted to the host.

In still another aspect of the present invention, a data processing apparatus for a NAND flash memory device is provided, the apparatus comprising:

a determining module, configured to: when receiving a data write request command sent by the host, determine that the to-be-processed block data is in a corresponding Page page in the to-be-operated storage unit of the NAND flash memory device;

a data processing module, configured to perform an inverse operation on the to-be-processed block data according to a type of a Page page and a data feature of the to-be-processed block data, and to perform metadata of the Page page corresponding to the to-be-operated storage unit The area identifies the data processing method;

The command execution module is configured to encode the to-be-processed block data processed by the data processing module, and write the encoded coded data into the to-be-operated storage unit.

Optionally, the device further includes:

And a configuration module, configured to pre-set a corresponding metadata area for each storage unit in the NAND flash memory device, where the metadata area is used to identify a data processing manner corresponding to data written to different Page pages of the storage unit.

Optionally, the data processing module is configured to determine, when the Page page is a lower page page, whether the number of 0s in the to-be-processed block data is greater than 1, and if yes, the to-be-processed block The data corresponding to each bit in the data is subjected to a negation operation, and the data processing mode identifier corresponding to the inverse operation is written into the metadata area of the Page page corresponding to the to-be-operated storage unit;

The command execution module is further configured to directly perform an encoding operation on the to-be-processed block data when the number of 0s in the to-be-processed block data is less than or equal to 1.

Optionally, the data processing module is configured to determine, when the Page page is an upper page page, whether the number of 1 in the to-be-processed block data is greater than 0, and if yes, the to-be-processed block The data corresponding to each bit in the data is subjected to a negation operation, and the data processing mode identifier corresponding to the inverse operation is written into the metadata area of the Page page corresponding to the to-be-operated storage unit;

The command execution module is further configured to directly perform an encoding operation on the to-be-processed block data when the number of 1 in the to-be-processed block data is less than or equal to 0.

Optionally, the command execution module is further configured to: after the encoded encoded data is written into the to-be-operated storage unit, when receiving the data read request command sent by the host, from the to-be-operated storage unit Reading the target data in the Page page, and decoding the target data;

The device also includes:

An obtaining module, configured to acquire identifier information in a metadata area corresponding to the Page page of the target data;

Correspondingly, the determining module is further configured to determine whether the identifier information is a data processing mode identifier corresponding to the inverse operation;

The data processing module is further configured to: when the determination result of the determining module is that the identifier information is a data processing mode identifier corresponding to the negation operation, perform data corresponding to each bit in the decoded block data Reverse the operation and transfer the obtained block data to the host. Otherwise, the decoded block data is directly transmitted to the host.

Compared with the prior art, the main advantages of the technical solution of the present invention are as follows:

The data processing method and device of the NAND flash memory device provided by the embodiment of the present invention, when receiving the data write request command sent by the host, according to the type of the corresponding Page page in the storage unit to be operated and the data characteristics of the block data to be processed, according to the data characteristics of the block data to be processed The preset rule performs a negation operation on the processing block data, and stores a small amount of information in the metadata area in the storage unit of the NAND flash memory device to identify a data processing manner corresponding to the stored data in the corresponding page page of the storage unit, and then uses the information to Reducing data retention errors can effectively reduce the probability of data errors in NAND flash devices and improve the overall performance of NAND flash devices.

Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.

The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments.

DRAWINGS

Various other advantages and benefits will become apparent to those skilled in the art from a The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting. Throughout the drawings, the same reference numerals are used to refer to the same parts. In the drawing:

1 is a schematic structural view of a NAND memory cell;

2 is a schematic diagram showing threshold voltage distribution of memory cells in an MLC NAND flash memory device;

3 is a schematic diagram of a threshold voltage shift of a memory cell in an MLC NAND flash memory device due to a data retention error;

4 is a flowchart of a data processing method of a NAND flash memory device according to an embodiment of the present invention;

FIG. 5 is a flowchart of a specific process for a 4K byte write operation process;

6 is a flowchart of a specific process for a 4K byte read operation process;

FIG. 7 is a schematic structural diagram of a data processing apparatus of a NAND flash memory device according to an embodiment of the present invention; FIG.

FIG. 8 is a schematic structural diagram of a data processing apparatus of a NAND flash memory device according to another embodiment of the present invention.

detailed description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the embodiments of the present invention have been shown in the drawings, the embodiments Rather, these embodiments are provided so that this disclosure will be more fully understood and the scope of the disclosure will be fully disclosed.

Those skilled in the art will appreciate that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs, unless otherwise defined. It should also be understood that terms such as those defined in a general dictionary should be understood to have meaning consistent with the meaning in the context of the prior art, and will not be idealized or overly formal unless specifically defined. To explain.

NAND flash memory devices are high-performance, low-power, non-volatile memories that are becoming more widely used in today's storage industry, especially for SSDs. The process of NAND flash has been getting smaller and smaller. FIG. 1 is a schematic structural diagram of a NAND memory cell. Referring to FIG. 1, each NAND memory cell is developed from an SLC having only one bit of data to a current MLC/TLC. The benefits of these developments are obvious, the number of storage units on the same area is increasing, and costs are continually decreasing. However, the accompanying challenge is that the distance between the various memory cells is getting smaller and smaller, the oxide layer is getting thinner, and the interference of the electrical signals of adjacent memory cells is getting stronger and stronger, so data errors are increasing.

2 is a schematic diagram of threshold voltage distribution of memory cells in an MLC NAND flash device. Referring to FIG. 2, for MLCNAND flash memory, one memory cell stores 2-bit data, one bit belongs to the lower page and the other bit belongs to the upper page. The memory cell is programmed to four different threshold voltages based on this 2-bit data. In Figure 2, when the stored data is 11 (data state data state is 0), the threshold voltage of the memory cell conforms to the leftmost Gaussian distribution; when the stored data is 01 (data state is 1, upper page is 0, lower page is 1), the threshold voltage of the memory cell conforms to the Gaussian distribution on the left side; when the stored data is 00 (data state is 2), the threshold voltage of the memory cell conforms to the Gaussian distribution on the right side; when the data is stored as 10 (data state is 3. When the upper page is 1, and the lower page is 0), the threshold voltage of the memory cell conforms to the rightmost Gaussian distribution.

When a memory cell is programmed, as time passes, the stored charge may escape, causing a data retention error. This type of error can cause the threshold voltage of this memory cell to decrease, as shown in Figure 3. It can be seen that the heat balance voltage of one memory cell is around 0V, so the higher the threshold voltage, the more likely the charge to escape, resulting in data retention errors. Statistics also found that for data retention errors, the upper page has more errors from 1 to 0, while the lower page has more errors from 0 to 1.

To this end, the embodiment of the present invention provides a data processing method for reducing data retention errors by reducing the probability of data 10 and 00, so as not to add excessive redundancy bits and occupy excessive storage space. Effectively reduce the probability of data errors in NAND flash devices and improve the overall performance of NAND flash devices.

4 is a flow chart schematically showing a data processing method of a NAND flash memory device in accordance with an embodiment of the present invention. Referring to FIG. 4, the data processing method of the NAND flash memory device of the embodiment of the present invention specifically includes the following steps:

S11. When receiving a data write request command sent by the host, determining that the to-be-processed block data is in a corresponding Page page in the to-be-operated storage unit of the NAND flash memory device.

S12. Perform inverse operation on the to-be-processed block data according to a preset rule according to a type of the Page page and a data feature of the to-be-processed block data, and perform data processing in the metadata area corresponding to the Page page of the to-be-operated storage unit. The way the logo is.

S13. Encode the processed block data to be processed, and write the encoded coded data into the to-be-operated storage unit.

The data processing method of the NAND flash memory device provided by the embodiment of the present invention, according to the data write request command sent by the host, according to the type of the corresponding Page page in the storage unit to be operated and the data feature of the block data to be processed, according to the preset The rule performs the negation operation on the processing block data, and stores a small amount of information in the metadata area in the storage unit of the NAND flash memory device to identify the data processing mode corresponding to the stored data in the corresponding page page of the storage unit, and then uses the information to reduce the data. Retaining errors can effectively reduce the probability of data errors in NAND flash devices and improve the overall performance of NAND flash devices.

Further, the method further includes the step of setting a corresponding metadata area for each of the NAND flash memory devices in advance. The metadata area is used to identify a data processing manner corresponding to data written to different Page pages of the storage unit.

In the embodiment of the present invention, the step S12 may further include the following two situations, as follows:

When the Page page is not a lower page page, that is, when the Page page is an upper page page, it is determined whether the number of 1 in the to-be-processed block data is greater than 0; if yes, the to-be-processed The data corresponding to each bit in the block data is subjected to a negation operation, and the data processing mode identifier corresponding to the inverse operation is written in the metadata area corresponding to the Page page of the to-be-operated storage unit; otherwise, the The block data is processed for encoding operations.

The technical solution of the present invention will be explained below by taking an MLC NAND flash memory device as an example.

When MLC NAND flash is applied to a solid state drive, it is accessed as a block device. The size of a block is mostly 512 bytes or 4K bytes. In the embodiment of the present invention, 4K bytes is taken as an example. When the host writes 4K bytes of data, the SSD master will encode according to the adopted BCH/LDPC technology, and for each 4K bytes of data, the master will add a few bytes of metadata for Management information for storing data. The data method proposed by the embodiment of the present invention utilizes the storage area of the metadata to reduce the data retention error of the NAND flash memory.

For SSDs, the reliability of the data is the most important. According to the barrel theory, problems with the reliability of data often occur in the worst case. In particular, the capacity of SSDs is getting larger and larger, and small-probability events will become unnegligible as statistical samples increase. For example, for data retention errors, if the data stored in NAND is 10 (data state is 3, upper page is 1, lower page is 0), then many data retention errors may occur, possibly exceeding BCH. The error correction capability of technologies such as /LDPC causes irreversible errors and affects the reliability of data. Therefore, the data processing method proposed by the embodiment of the present invention is to prevent the occurrence of such an extreme situation. At the same time, in order to reduce redundant bits occupying too much storage space, for one piece (512 bytes or 4 Kbytes) of data, the embodiment of the present invention stores only a small number of bits in the metadata area to identify the data processing mode. Referring to FIG. 5, FIG. 5 is a specific processing flowchart of a 4K byte write operation process, which specifically includes: when receiving a data write request command sent by a host, differentiating the metadata storage area for identifying the write storage unit The identification information of the data processing mode corresponding to the data of the page page may be set to 0 in one specific embodiment. For the block data of the lower page in the storage unit to be operated, if the number of 0s in the original data is greater than one, the entire block of data is inverted, that is, the inverse operation is performed, and 1 is stored in the metadata area to indicate the The data of the Page page corresponding to the storage unit is the data after the data is inverted, so that the original data is obtained by performing the corresponding inversion operation when the data is subsequently read. If the number of 0s in the original data is less than or equal to 1, the entire block of data is not inverted, and 0 is stored in the metadata area to indicate that the data of the Page page corresponding to the storage unit is data that has not undergone data inversion processing. The subsequent can be directly read and sent to the host. Then, the inverted data is encoded by the BCH/LDPC error correction technique and sent to the storage unit. For the block data of the upper page in the storage unit to be operated, if the number of 1s in the original data is greater than 0, the entire block of data is inverted, and 1 is stored in the metadata area. If the number of 1s in the original data is less than or equal to 0, the entire block of data is not inverted and 0 is stored in the metadata area.

In the embodiment of the present invention, after the encoded encoded data is written into the to-be-operated storage unit, the method further includes the following steps:

In a specific embodiment, referring to FIG. 6, FIG. 6 is a specific processing flowchart for a 4K byte read operation process, which specifically includes: when receiving a data read request command sent by a host, from a storage unit to be operated The page reads the data, and decodes the read data through the BCH/LDPC error correction technology, and then obtains the identification information in the metadata area of the Page page storing the data. If the identification information of the metadata area is 1, The data of the Page page is data after data inversion. Therefore, the data corresponding to each bit in the decoded block data is inversely operated, and the obtained block data is transmitted to the host, otherwise The decoded block data is transmitted to the host.

The data processing method of the NAND flash memory device provided by the embodiment of the present invention combines a common BCH/LDPC error correction technology to store a small amount of information in a metadata area of a block device using NAND FLASH as a storage medium to identify a data mode. This information reduces data retention errors and effectively reduces the probability of data errors in NAND flash devices.

The technical solution provided by the embodiments of the present invention is not limited to the MLC NAND flash memory device, and is also applicable to the TLC and SLC NAND flash memory devices. For the data processing method embodiments of the TLC and SLC NAND flash memory devices, due to the MLC NAND flash memory device The data processing method embodiments are basically similar, so the description is not described too much. For related details, refer to the description of the embodiment of the data processing method of the MLC NAND flash memory device.

In addition, the technical solution provided by the embodiment of the present invention is not limited to the SSD application. For other block devices that use the NAND FLASH as the storage medium, the data processing of the NAND flash memory device provided by the embodiment of the present invention can be applied as long as the metadata area exists. The method is to effectively reduce the probability of data error occurrence of the NAND flash device.

For the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should understand that the embodiments of the present invention are not limited by the described action sequence, because the embodiment according to the present invention Some steps can be performed in other orders or at the same time. In the following, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

FIG. 7 is a schematic block diagram showing the structure of a data processing apparatus of a NAND flash memory device according to an embodiment of the present invention. The data processing apparatus of the NAND flash memory device of the embodiment of the present invention may be disposed in a main controller of the NAND flash memory device or implemented by a main controller. Referring to FIG. 7, the data processing apparatus of the NAND flash memory device of the embodiment of the present invention specifically includes a determining module 701, a data processing module 702, and a command execution module 703, wherein: the determining module 701 is configured to receive data sent by the host. When the request command is written, it is determined that the to-be-processed block data is in the corresponding Page page in the to-be-operated storage unit of the NAND flash memory device; the data processing module 702 is configured to use, according to the type of the Page page and the data characteristics of the to-be-processed block data, Performing a negation operation on the to-be-processed block data according to a preset rule, and performing data processing mode identification on a metadata area corresponding to the Page page of the to-be-operated storage unit; the command execution module 703 is configured to The to-be-processed block data processed by the data processing module 702 is encoded, and the encoded encoded data is written into the to-be-operated storage unit.

The data processing apparatus of the NAND flash memory device provided by the embodiment of the present invention, according to the data write request command sent by the host, according to the type of the corresponding Page page in the storage unit to be operated and the data characteristics of the to-be-processed block data, according to the pre-pre The rule is to perform the negation operation on the processing block data, and store a small amount of information in the metadata area in the storage unit of the NAND flash memory device to identify the data processing mode corresponding to the stored data in the corresponding page page of the storage unit, and then use the information to reduce Data retention errors can effectively reduce the probability of data errors in NAND flash devices and improve the overall performance of NAND flash devices.

In an optional embodiment of the present invention, the data processing apparatus of the NAND flash memory device further includes a configuration module not shown in the drawing, the configuration module for pre-empting each of the NAND flash memory devices A storage unit sets a corresponding metadata area, and the metadata area is used to identify a data processing manner corresponding to data written to different Page pages of the storage unit.

In the embodiment of the present invention, the data processing module 702 is specifically configured to determine, when the Page page is a lower page page, whether the number of 0s in the to-be-processed block data is greater than 1, and if yes, The data corresponding to each bit in the to-be-processed block data is inversely operated, and the data processing mode identifier corresponding to the inverse operation is written into the metadata area of the Page page corresponding to the to-be-operated storage unit;

The command execution module 703 is further configured to directly perform an encoding operation on the to-be-processed block data when the number of 0s in the to-be-processed block data is less than or equal to 1.

In the embodiment of the present invention, the data processing module 702 is specifically configured to determine, when the Page page is an upper page page, whether the number of 1 in the to-be-processed block data is greater than 0, and if yes, The data corresponding to each bit in the to-be-processed block data is inversely operated, and the data processing mode identifier corresponding to the inverse operation is written into the metadata area of the Page page corresponding to the to-be-operated storage unit;

The command execution module 703 is further configured to directly perform an encoding operation on the to-be-processed block data when the number of 1 in the to-be-processed block data is less than or equal to 0.

In an optional embodiment of the present invention, the command execution module 703 is further configured to: after the encoded encoded data is written into the to-be-operated storage unit, receive a data read request sent by the host At the time of the command, the target data is read from the Page page of the storage unit to be operated, and the target data is decoded.

Correspondingly, referring to FIG. 8 , the apparatus further includes an obtaining module 704, where the acquiring module 704 is configured to acquire identifier information in a metadata area corresponding to the Page page of the target data;

Further, the determining module 701 is further configured to determine whether the identifier information is a data processing mode identifier corresponding to the inverse operation;

The data processing module 702 is further configured to: when the determination result of the determining module 701 is that the identifier information is a data processing mode identifier corresponding to the negation operation, corresponding to each bit in the decoded block data The data is negated and the obtained block data is transmitted to the host. Otherwise, the decoded block data is directly transmitted to the host.

For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

The data processing method and device of the NAND flash memory device provided by the embodiment of the present invention, when receiving the data write request command sent by the host, according to the type of the corresponding Page page in the storage unit to be operated and the data characteristics of the block data to be processed, according to The preset rule performs a negation operation on the processing block data, and stores a small amount of information in the metadata area in the storage unit of the NAND flash memory device to identify a data processing manner corresponding to the stored data in the corresponding page page of the storage unit, and then uses the information to Reducing data retention errors can effectively reduce the probability of data errors in NAND flash devices and improve the overall performance of NAND flash devices.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

A data processing method for a NAND flash memory device, comprising:

Receiving a data write request command sent by the host, determining that the to-be-processed block data is in a corresponding Page page in the to-be-operated storage unit of the NAND flash memory device;

Determining the to-be-processed block data according to a preset rule according to a type of the page page and a data feature of the to-be-processed block data, and performing data processing on the metadata area corresponding to the Page page of the to-be-operated storage unit Identification

The processed block data to be processed is encoded, and the encoded coded data is written into the to-be-operated memory unit.
The method of claim 1 further comprising:

A corresponding metadata area is set in advance for each of the NAND flash memory devices, and the metadata area is used to identify a data processing manner corresponding to data written to different Page pages of the storage unit.
The method according to claim 1 or 2, wherein the inverse of the to-be-processed block data is performed according to a preset rule according to a type of the Page page and a data feature of the to-be-processed block data, and Declaring the identifier of the data processing mode corresponding to the metadata area of the Page page corresponding to the operation storage unit, including:

When the Page page is a lower page, determining whether the number of 0s in the to-be-processed block data is greater than 1; if yes, inverting data corresponding to each bit in the to-be-processed block data The operation is performed, and the data processing mode identifier corresponding to the inverse operation is written in the metadata area corresponding to the Page page of the to-be-operated storage unit; otherwise, the encoding operation is performed on the to-be-processed block data.
The method according to claim 1 or 2, wherein the inverse of the to-be-processed block data is performed according to a preset rule according to a type of the Page page and a data feature of the to-be-processed block data, and Declaring the identifier of the data processing mode corresponding to the metadata area of the Page page corresponding to the operation storage unit, including:

When the Page page is an upper page page, determining whether the number of 1 in the to-be-processed block data is greater than 0; if yes, inverting data corresponding to each bit in the to-be-processed block data The operation is performed, and the data processing mode identifier corresponding to the inverse operation is written in the metadata area corresponding to the Page page of the to-be-operated storage unit; otherwise, the encoding operation is performed on the to-be-processed block data.
The method according to claim 1, wherein after the encoded encoded data is written into the to-be-operated storage unit, the method further comprises:

When receiving the data read request command sent by the host, reading the target data from the Page page of the storage unit to be operated, and decoding the target data;

Obtaining the identification information in the metadata area corresponding to the Page page of the target data;

Determining whether the identification information is a data processing mode identifier corresponding to the inverse operation, and if so, inverting the data corresponding to each bit in the decoded block data, and transmitting the obtained block data to the host, Otherwise, the decoded block data is directly transmitted to the host.
A data processing device for a NAND flash memory device, comprising:

a determining module, configured to: when receiving a data write request command sent by the host, determine that the to-be-processed block data is in a corresponding Page page in the to-be-operated storage unit of the NAND flash memory device;

a data processing module, configured to perform an inverse operation on the to-be-processed block data according to a type of a Page page and a data feature of the to-be-processed block data, and to perform metadata of the Page page corresponding to the to-be-operated storage unit The area identifies the data processing method;

The command execution module is configured to encode the to-be-processed block data processed by the data processing module, and write the encoded coded data into the to-be-operated storage unit.
The device according to claim 6, wherein the device further comprises:

And a configuration module, configured to pre-set a corresponding metadata area for each storage unit in the NAND flash memory device, where the metadata area is used to identify a data processing manner corresponding to data written to different Page pages of the storage unit.
The device according to claim 6 or 7, wherein the data processing module is configured to determine whether the number of 0s in the to-be-processed block data is greater than 1 when the Page page is a lower page page. The quantity, if yes, inverts the data corresponding to each bit of the to-be-processed block data, and writes the data processing mode identifier corresponding to the inverse operation to the element corresponding to the Page page of the to-be-operated storage unit Data area

The command execution module is further configured to directly perform an encoding operation on the to-be-processed block data when the number of 0s in the to-be-processed block data is less than or equal to 1.
The device according to claim 6 or 7, wherein the data processing module is configured to determine whether the number of 1 in the to-be-processed block data is greater than 0 when the Page page is an upper page page. The quantity, if yes, inverts the data corresponding to each bit of the to-be-processed block data, and writes the data processing mode identifier corresponding to the inverse operation to the element corresponding to the Page page of the to-be-operated storage unit Data area

The command execution module is further configured to directly perform an encoding operation on the to-be-processed block data when the number of 1 in the to-be-processed block data is less than or equal to 0.
The device according to claim 6, wherein the command execution module is further configured to: after the encoded encoded data is written into the to-be-operated storage unit, receive data read by the host When the command is requested, the target data is read from the Page page of the storage unit to be operated, and the target data is decoded;

The device also includes:

An obtaining module, configured to acquire identifier information in a metadata area corresponding to the Page page of the target data;

Correspondingly, the determining module is further configured to determine whether the identifier information is a data processing mode identifier corresponding to the inverse operation;

The data processing module is further configured to: when the determination result of the determining module is that the identifier information is a data processing mode identifier corresponding to the negation operation, perform data corresponding to each bit in the decoded block data Reverse the operation and transfer the obtained block data to the host. Otherwise, the decoded block data is directly transmitted to the host.