CN107465341B - Control method and control circuit of DCMBoost power factor correction converter - Google Patents
Control method and control circuit of DCMBoost power factor correction converter Download PDFInfo
- Publication number
- CN107465341B CN107465341B CN201710803670.0A CN201710803670A CN107465341B CN 107465341 B CN107465341 B CN 107465341B CN 201710803670 A CN201710803670 A CN 201710803670A CN 107465341 B CN107465341 B CN 107465341B
- Authority
- CN
- China
- Prior art keywords
- power factor
- input voltage
- factor correction
- voltage
- correction converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000003321 amplification Effects 0.000 claims abstract description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 8
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000001939 inductive effect Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a control method and a control circuit of a DCM Boost power factor correction converter. The control method comprises the following steps: detecting output voltage V of DCM Boost power factor correction converter o With a reference voltage V ref Error amplification is carried out to obtain an error amplification signal V EA (ii) a By a proportionality coefficient k i Obtain a control signal V con_i Control signal V con_i Respectively compared with sawtooth wave to generate control pulse P i (ii) a Detecting the input voltage v after rectification of the DCM Boost power factor correction converter at the beginning of each switching period rec And is bounded by an input voltage V i After the comparison, P is selected i The active control pulse is used for controlling the conduction of a switching tube of the DCM Boost power factor correction converter. The control circuit comprises an input voltage judger, a control pulse generator and a control pulse selector. The invention can improve the power factor of the traditional DCM Boost power factor correction converter, and can obtain the power factor close to 1 in the input voltage range of 90V-264V AC.
Description
Technical Field
The invention relates to a DCM Boost power factor correction converter, in particular to a control method and a control circuit of the DCM Boost power factor correction converter.
Background
The power factor correction converter can reduce harmonic pollution of the power electronic device to a public power grid, and has the advantages of high power factor, small size, low cost and the like. Boost power factor correction converters operating in discontinuous mode (DCM) of inductive current are widely used with the advantages of simple control, no diode reverse recovery loss, etc. The conduction duty ratio of a switch tube of the fixed duty ratio control DCM Boost power factor correction converter is fixed, input current distortion exists, the input current distortion is more serious along with the improvement of input voltage, the input power factor is reduced, and the fixed duty ratio control DCM Boost power factor correction converter cannot meet the requirements on occasions with high requirements on power factors and input current harmonics.
Disclosure of Invention
The invention aims to provide a DCM Boost power factor corrector control method and a DCM Boost power factor corrector control circuit with high power factor.
The technical scheme of the control method for realizing the aim of the invention is as follows:
a control method of a DCM Boost power factor correction converter comprises the following steps:
detecting output voltage V of DCM Boost power factor correction converter o With a reference voltage V ref Error amplification is carried out to obtain an error amplification signal V EA ；
By a proportionality coefficient k i Obtain a control signal V con_i I.e. V con_i ＝k i V EA (ii) a The proportionality coefficient
Wherein V m_max At the peak of the maximum input voltage, M i I =0,1,2, \ 8230;, n;
will control the signal V con_i Respectively compared with sawtooth wave to generate control pulse P i ；
Detecting the input voltage v after rectification of the DCM Boost power factor correction converter at the beginning of each switching period rec And is bounded by the input voltage i And (3) comparison: when V is i ≤v rec ＜V i+1 When selecting P i As an active control pulse; when v is rec ≥V n When selecting P n As an active control pulse; the input voltage boundary V i ＝M i V m_max And the effective control pulse is used for controlling the conduction of a switching tube of the DCM Boost power factor correction converter.
Further technical solution, the electricityCoefficient of pressure boundary
The technical scheme of the control circuit for realizing the purpose of the invention is as follows:
a control circuit of a DCM Boost power factor correction converter comprises an input voltage judger, a control pulse generator and a control pulse selector;
the input voltage judger comprises a first comparator B 10 ，B 11 ，…，B 1n And D flip-flop D 1 ，D 2 ，…，D n (ii) a First comparator B 10 Is used for connecting a switching period detection signal V PC The negative input end is used for connecting a sawtooth wave v saw The output end is connected to a D flip-flop D 1 ，D 2 ，…，D n The CLK terminal of (1); first comparator B 11 ，…，B 1n Respectively for connecting to an input voltage boundary V i I =1,2, \ 8230, n, negative input ends are respectively used for connecting input voltage v after rectification of DCM Boost power factor correction converter rec The output ends are respectively correspondingly connected to the D flip-flops D 1 ，D 2 ，…，D n The D terminal of (1);
the control pulse generator comprises an error amplifier and a voltage division network K 0 ，K 1 ，…，K n And a second comparator B 20 ，B 21 ，…，B 2n (ii) a The negative input end of the error amplifier is used for being connected with the output voltage V of the DCM Boost power factor correction converter o The positive input end is used for connecting a reference voltage V ref The output end of the voltage divider is connected to the voltage dividing network K 0 ，K 1 ，…，K n An input terminal of (1); voltage divider network K 0 ，K 1 ，…，K n Are respectively correspondingly connected to the second comparator B 20 ，B 21 ，…，B 2n The positive input end of (a); second comparator B 20 ，B 21 ，…，B 2n Is used for connecting a sawtooth wave v saw (ii) a The voltage dividing network K 0 ，K 1 ，…，K n Respectively is k 0 ，k 1 ，…k n ；
The control pulse selector comprises an AND gate Y 0 ，Y 1 ，…，Y n And or gate; and gate Y 1 Are respectively connected to a D flip-flop D 1 QN terminal, D flip-flop D 2 And a second comparator B 21 An output terminal of (a); and gate Y 2 Are respectively connected to a D flip-flop D 2 QN terminal, D flip-flop D 3 And a second comparator B 22 An output terminal of (a); and gate Y 3 ，…，Y n-1 The connection relation between the D trigger and the second comparator is analogized in the same way; and gate Y 0 Are respectively connected to a D flip-flop D 1 And a second comparator B 20 An output terminal of (a); and gate Y n Are respectively connected to the D flip-flops D n QN terminal and second comparator B 2n An output terminal of (a); AND gate Y 0 ，Y 1 ，…，Y n The output ends of the or gates are respectively connected to the input ends of the or gates, and the output ends of the or gates are used for being connected with a switching tube of the DCM Boost power factor correction converter.
The invention has the beneficial effects that: therefore, the DCM Boost power factor corrector can obtain a power factor approximate to 1 in the whole 90-264V AC input voltage range.
Drawings
FIG. 1 is a block diagram of a DCM Boost PFC converter system of the present invention;
FIG. 2 is a flow chart of a control method of the DCM Boost PFC converter of the present invention;
fig. 3 is a circuit diagram of the input voltage determiner (100), including comparators (101, 102, 103, 104, 105), D flip-flops (106, 107, 108, 109); d flip-flop D i Has an output of V at the Q terminal Qi The QN terminal output is V NQi ；
Fig. 4 is a circuit diagram of a control pulse generator (200) including an error amplifier (201), a voltage divider network (202), and a comparator (203);
fig. 5 is a circuit diagram of a control pulse selector (300) including and gates (301, 302, 303), or gate (304), and a driving circuit (305);
FIG. 6 is key waveforms of the present invention including (a) input voltage boundary, (b) control pulse type, (c) inductor current waveform, and (d) switching tube drive waveform;
FIG. 7 is a design method of input voltage boundary coefficients;
FIG. 8 is an input voltage versus input current waveform for different input voltage conditions, including (a) an input voltage waveform and (b) an input current waveform;
FIG. 9 is a PF comparison of constant duty cycle control and DCM Boost power factor correction converter of the present invention;
FIG. 10 is a comparison of the THD of the fixed duty cycle control and DCM Boost power factor correction converter of the present invention;
FIG. 11 is V in When the voltage is not less than 110V, the input voltage, the input current and the inductive current simulation waveform of the DCM Boost power factor correction converter are controlled by a fixed duty ratio;
FIG. 12 is V in When the voltage is not less than 264V, the input voltage, the input current and the inductive current simulation waveform of the DCM Boost power factor correction converter are controlled by a fixed duty ratio;
FIG. 13 is V in When the voltage is not less than 110V, the input voltage, the input current and the inductor current of the DCM Boost power factor correction converter simulate waveforms;
FIG. 14 is V in When =264V, the input voltage, the input current, and the inductor current simulation waveform of the DCM Boost power factor correction converter of the present invention;
the main symbol names of the above figures: v. of in For inputting AC voltage, there are
v rec For rectified input voltage, with->
Omega is the input alternating voltage angular frequency. V in Is the effective value of the input voltage. i.e. i in Is the input current. i.e. i L Is the inductor current. L is Boost converter Boost voltageFeeling is felt. Q is a switching tube. VD is a diode. And C is the output capacitor of the Boost converter. R is a load. V o Is the output voltage. P i Is a control pulse type. D i For controlling the pulse P i The corresponding duty cycle. T is s Is the converter switching period. T is line Is the power frequency cycle. V i Is the input voltage boundary. v. of gs Is a switching tube driving signal.
Detailed Description
The present invention will now be described in further detail by way of specific examples in conjunction with the accompanying drawings.
Fig. 1 is a block diagram of a system structure of a DCM Boost pfc converter according to the present invention, and the control circuit shown in fig. 1 is composed of three parts: an input voltage determiner 100, a control pulse generator 200, and a control pulse selector 300.
The control pulse generator 200 comprises an error amplifier 201, n +1 control pulse coefficients k i (i =0,1,2, \ 8230;, n) and n +1 comparators, and controls the pulse generator 200 to detect the output voltage V o And an error amplifier 201 obtains an output voltage error feedback signal V EA The output end of the error amplifier and n +1 proportionality coefficients k i (i =0,1,2, \ 8230;, n) are connected, resulting in n +1 control signals V con_i (i =0,1,2, \8230;, n) by a sawtooth wave v saw Comparing to obtain n +1 control pulses P i (i =0,1,2, \8230;, n), where the output terminals of the n +1 comparators are respectively connected to the n +1 and gates in the control pulse selector 300. The input voltage determiner 100 is composed of n +1 comparators and n D flip-flops, and the control pulse selector 300 is composed of an or gate 304 and n +1 and gates. At the beginning of each switching cycle, V is input into the voltage determiner 100 PC And sawtooth wave v saw The CLK terminals of all D flip-flops in the input voltage detector 100 are set to 1 when V is compared by the comparator 101 0 ≤v rec ＜V 1 When the comparator 102 outputs high level, the D end of the D flip-flop 106 is set to 1, and V is Q0 Is high level and controls the pulse P by controlling the AND gate 301 of the pulse selector 300 0 Selecting the pulse as an effective control pulse of a Boost converter; when V is i ≤v rec ＜V i+1 When the comparator 103 outputs a low level and the D terminal of the flip-flop 107 is set to 0, V is set to NQi When the voltage level is high, the comparator 104 outputs a high voltage level, the D terminal of the flip-flop 108 is set to 1, and V is set Qi Is also high and controls the pulse P by controlling the and gate 303 in the pulse selector 300 i Selecting the effective control pulse as an effective control pulse of a Boost converter; when in use
When the comparator 105 outputs a low level and the D terminal of the D flip-flop 109 is set to 0, V is set to Qn Is high and controls the pulse P via the AND gate 304 n The selection is made as an active control pulse for the Boost converter.
The duty ratio of the DCM Boost pfc converter is determined by the input voltage determiner 100, the control pulse generator 200 and the control pulse selector 300. The control method comprises the following steps: 1. detecting the output voltage V o And a reference voltage V ref Error amplification is carried out to obtain an error amplification signal V EA (ii) a 2. By n +1 scaling factors k i (i =0,1,2, \ 8230;, n) results in n +1 control signals V con_i (i =0,1,2, \8230;, n), wherein V con_i ＝k i V EA Is provided with
V m_max The peak value of the maximum input voltage, for example: for the input voltage change range of 90V-264V AC, the signal strength is greater than or equal to>
M i (i =0,1,2, \ 8230;, n) is a voltage boundary coefficient, setting @>
3. N +1 control signals V con_i (i =0,1,2, \8230;, n) are compared with the sawtooth wave, respectively, to generate n +1 control pulses P i (i =0,1,2, \8230;, n); 4. at the beginning of each switching cycle, the rectified input voltage v is detected rec And is connected with n +1 input voltage edgesBoundary V i (i =0,1,2, \ 8230;, n) to set an input voltage boundary V i ＝M i V m_max (ii) a 5. When V is 0 ≤v rec ＜V 1 When selecting P 0 The pulse is used as an effective control pulse to control the conduction of the switch tube; when V is i ≤v rec ＜V i+1 When selecting P i As an active control pulse; when v is rec ≥V n When selecting P n As an active control pulse.
Fig. 2 is a flowchart of a control method of the DCM Boost pfc converter of the present invention, and it can be known from fig. 2 that the input voltage determiner 100, the control pulse generator 200 and the control pulse selector 300 function as:
1) Input voltage determiner 100: at the beginning of each switching cycle, the input voltage decider 100 will rectify the input voltage v rec (t) and a predetermined n +1 input voltage boundary V i (i =0,1,2, \8230;, n) were compared to determine v rec (t) a voltage range in which
V i ＝M i V m_max (3)
In the formula, V m_max The voltage amplitude at which the input AC voltage is highest, for example, the 90-264V AC input voltage range,
M i (i =0,1, \8230;, n) is the input voltage boundary coefficient. M i Any manner of defining the boundary coefficient of the input voltage may be used. For optimal technical effect, the unit sin (ω t) is equally divided into (n + 1) segments within the range of 0- π/2, as shown in FIG. 7, M i The corresponding unit sine function is divided equally for each phase.
2) Control pulse generator 200: control pulse generator 200 detects output voltage V of DCM Boost power factor correction converter o With a reference voltage V ref Error reduction is carried outLarge resulting error amplified signal V EA (ii) a Then the set (n + 1) different control pulse proportionality coefficients k are passed i (i =0,1,2, \ 8230;, n), resulting in (n + 1) different control signals V con_i (i =0,1,2, \8230;, n), where V con_i ＝k i V EA Then the control signal is connected with the sawtooth wave v saw Comparing to obtain (n + 1) different control pulses P i (i =0,1,2, \8230;, n), control pulse P i Corresponding duty cycle D i Is composed of
D i ＝k i D o (5)
Wherein the pulse proportionality coefficient k is controlled i Is arranged as
3) Control the pulse selector 300: according to the output signal of the input voltage judger, the control pulse selector selects the corresponding control pulse to realize the control of the switch tube, and the selection process is shown in fig. 6. FIG. 6 is a diagram of the main waveforms of the present invention, wherein (a) is the input voltage waveform, wherein (b) is the selection process of the control pulse, (c) is the inductor current waveform, and (d) is the switch tube driving waveform. As can be seen from FIGS. 6 (a) and 6 (b), when V is greater than V 0 ≤v rec ＜V 1 When selecting P 0 As an effective control pulse, when V i ≤v rec ＜V i+1 When selecting P i As an effective control pulse, when v rec ≥V n When selecting P n As an effective control pulse, the duty ratio change function D of the DCM Boost power factor correction converter can be obtained within a half power frequency period PT (t)。
Input current i of DCM Boost power factor correction converter in ：
To be provided with
The formula (8) is unified into a standard value to obtain a unified input current i in * ：
Wherein i in_i * Is composed of
Taking n =13, all control circuit parameters of the DCM Boost power factor correction converter of the present invention can be determined according to equations (3), (4) and (6). When n =13 in tables 1 and 2, input voltage boundary V i Proportional coefficient k to control pulse i The value of (a).
TABLE 1 input Voltage boundary V i (photovoltaic)
TABLE 2 control pulse coefficient k i
From the above parameters, it can be made that the output voltage V is shown in FIG. 8 o When =400, in half power frequency period, different input voltage effective values V in The corresponding input voltage and input current waveforms. As can be seen from FIG. 8 (a), when V is in When =110V, V rec (t) can only rise to V 3 Therefore, only 4 control pulses are used; when V is in When =264V, V rec (t) will rise to V 13 Therefore, 14 control pulses will be used. As can be seen from FIG. 8 (b), V in =110V and V in =264V, the corresponding input current waveform is very close to being sinusoidal.
Fig. 9 locates the PF of the DCM Boost power factor correction converter of the present invention. As can be seen from fig. 9, in the 90-264V AC input voltage range, the lowest PF value of the DCM Boost power factor correction converter with constant duty ratio control is 0.865, while the lowest PF value of the DCM Boost power factor correction converter of the present invention is 0.996.
Fig. 10 locates the THD of the DCM Boost pfc converter of the present invention. As shown in fig. 10, the maximum THD of the fixed-duty ratio DCM Boost pfc converter is 58% in the 90-264V AC input voltage range, whereas the maximum THD of the DCM Boost pfc converter of the present invention is only 8%.
FIG. 11 and FIG. 12 are each V in Hour and V of =110V in When =264V, the input ac voltage V of the DCM Boost pfc converter is controlled with a fixed duty ratio in Input current i in An inductor current i L The simulated waveform of (2). As can be seen from fig. 11, as the input voltage increases, the input current distortion also increases.
FIGS. 13 and 14, respectively V in Hour and V of =110V in When =264V, the input ac voltage V of the DCM Boost power factor correction converter of the present invention in Input current i in Inductor current i L The simulated waveform of (2). As can be seen from fig. 14, the input current of the DCM Boost pfc converter of the present invention is still close to sinusoidal when the input voltage increases.
Claims (3)
1. A control method of a DCM Boost power factor correction converter is characterized by comprising the following steps:
detecting output voltage V of DCM Boost power factor correction converter o With a reference voltage V ref Error amplification is carried out to obtain an error amplification signal V EA ；
By a proportionality coefficient k i Obtain a control signal V con_i I.e. V con_i ＝k i V EA (ii) a The proportionality coefficient
Wherein V m_max At the peak of the maximum input voltage, M i For the input voltage boundary coefficient to be the input voltage boundary coefficient,
i＝0,1,2,…,n；
will control the signal V con_i Respectively compared with sawtooth waves to generate control pulses P i ；
Detecting the input voltage v after rectification of the DCM Boost power factor correction converter at the beginning of each switching period rec And is bounded by the input voltage i And (3) comparison: when V is i ≤v rec ＜V i+1 When selecting P i As an active control pulse; when v is rec ≥V n When selecting P n As an active control pulse; the input voltage boundary V i ＝M i V m_max And the effective control pulse is used for controlling the conduction of a switching tube of the DCM Boost power factor correction converter.
2. The control method of claim 1, wherein the voltage boundary coefficient
3. A control circuit of a DCM Boost power factor correction converter is characterized by comprising an input voltage judger (100), a control pulse generator (200) and a control pulse selector (300);
the input voltage determiner (100) includes a first comparator B 10 ，B 11 ，…，B 1n And D flip-flop D 1 ，D 2 ，…，D n (ii) a First comparator B 10 Is used for connecting a switching period detection signal V PC Negative deliveryThe input end is used for connecting a sawtooth wave v saw The output end is connected to a D flip-flop D 1 ，D 2 ，…，D n A CLK terminal of; first comparator B 11 ，…，B 1n Respectively for connecting to an input voltage boundary V i I =1,2, \ 8230, n, negative input ends are respectively used for connecting input voltage v after rectification of DCM Boost power factor correction converter rec The output ends are respectively correspondingly connected to the D flip-flops D 1 ，D 2 ，…，D n The D terminal of (1); the input voltage boundary V i ＝M i V m_max In which V is m_max At the peak of the maximum input voltage, M i Is the input voltage boundary coefficient;
the control pulse generator (200) comprises an error amplifier and a voltage division network K 0 ，K 1 ，…，K n And a second comparator B 20 ，B 21 ，…，B 2n (ii) a The negative input end of the error amplifier is used for being connected with the output voltage V of the DCM Boost power factor correction converter o The positive input end is used for connecting a reference voltage V ref The output end is connected to a voltage division network K 0 ，K 1 ，…，K n An input terminal of (1); voltage dividing network K 0 ，K 1 ，…，K n Are respectively correspondingly connected to the second comparator B 20 ，B 21 ，…，B 2n The positive input end of (a); second comparator B 20 ，B 21 ，…，B 2n Is used for connecting a sawtooth wave v saw (ii) a Said voltage divider network K 0 ，K 1 ，…，K n Respectively is k 0 ，k 1 ，…k n (ii) a Coefficient of proportionality
Wherein V m_max At the peak of the maximum input voltage, M i Is an input voltage boundary coefficient, V o For the output voltage of the DCM Boost power factor correction converter, i =0,1,2, \8230;, n;
the control pulse selector (300) comprises an AND gate Y 0 ，Y 1 ，…，Y n And or gate; and gate Y 1 Are respectively connected to the D flip-flops D 1 QN terminal, D flip-flop D 2 And a second comparator B 21 An output terminal of (a); and gate Y 2 Are respectively connected to the D flip-flops D 2 QN terminal, D flip-flop D 3 And a second comparator B 22 An output terminal of (a); and gate Y 3 ，…，Y n-1 The connection relation between the D trigger and the second comparator is analogized; and gate Y 0 Are respectively connected to a D flip-flop D 1 And a second comparator B 20 An output terminal of (a); and gate Y n Are respectively connected to a D flip-flop D n QN terminal and second comparator B 2n An output terminal of (a); AND gate Y 0 ，Y 1 ，…，Y n The output ends of the or gates are respectively connected to the input ends of the or gates, and the output ends of the or gates are used for being connected with a switching tube of the DCM Boost power factor correction converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710803670.0A CN107465341B (en) | 2017-09-08 | 2017-09-08 | Control method and control circuit of DCMBoost power factor correction converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710803670.0A CN107465341B (en) | 2017-09-08 | 2017-09-08 | Control method and control circuit of DCMBoost power factor correction converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107465341A CN107465341A (en) | 2017-12-12 |
| CN107465341B true CN107465341B (en) | 2023-04-11 |
Family
ID=60552226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710803670.0A Expired - Fee Related CN107465341B (en) | 2017-09-08 | 2017-09-08 | Control method and control circuit of DCMBoost power factor correction converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107465341B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010097683A (en) * | 2000-04-25 | 2001-11-08 | 이형도 | Power factor compensation circuit having function of pulse width modulation |
| CN101242134A (en) * | 2008-03-05 | 2008-08-13 | 许建平 | Switch power control method and its device |
| CN102368662A (en) * | 2011-03-10 | 2012-03-07 | 杭州士兰微电子股份有限公司 | Current reference generation circuit, constant current switch power supply control circuit and control method thereof |
| CN102594118A (en) * | 2012-02-29 | 2012-07-18 | 杭州矽力杰半导体技术有限公司 | Boost PFC controller |
| CN103227575A (en) * | 2012-01-31 | 2013-07-31 | 台达电子工业股份有限公司 | Three-phase soft-switched PCF rectifiers |
| CN203933384U (en) * | 2014-06-13 | 2014-11-05 | 杭州电子科技大学 | A kind of high power factor correction control circuit and device |
| CN205195552U (en) * | 2015-11-20 | 2016-04-27 | 南京理工大学 | Power factor correction converter of wide load scope |
| CN106787695A (en) * | 2017-02-22 | 2017-05-31 | 东南大学 | A kind of Switching Power Supply control method of dynamic response optimization |
| CN207218526U (en) * | 2017-09-08 | 2018-04-10 | 西南交通大学 | A kind of control circuit of DCMBoost power factor correcting converters |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI426693B (en) * | 2011-12-01 | 2014-02-11 | Richtek Technology Corp | Switching regulator and control circuit and control method thereof |
-
2017
- 2017-09-08 CN CN201710803670.0A patent/CN107465341B/en not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010097683A (en) * | 2000-04-25 | 2001-11-08 | 이형도 | Power factor compensation circuit having function of pulse width modulation |
| CN101242134A (en) * | 2008-03-05 | 2008-08-13 | 许建平 | Switch power control method and its device |
| CN102368662A (en) * | 2011-03-10 | 2012-03-07 | 杭州士兰微电子股份有限公司 | Current reference generation circuit, constant current switch power supply control circuit and control method thereof |
| CN103227575A (en) * | 2012-01-31 | 2013-07-31 | 台达电子工业股份有限公司 | Three-phase soft-switched PCF rectifiers |
| CN102594118A (en) * | 2012-02-29 | 2012-07-18 | 杭州矽力杰半导体技术有限公司 | Boost PFC controller |
| CN203933384U (en) * | 2014-06-13 | 2014-11-05 | 杭州电子科技大学 | A kind of high power factor correction control circuit and device |
| CN205195552U (en) * | 2015-11-20 | 2016-04-27 | 南京理工大学 | Power factor correction converter of wide load scope |
| CN106787695A (en) * | 2017-02-22 | 2017-05-31 | 东南大学 | A kind of Switching Power Supply control method of dynamic response optimization |
| CN207218526U (en) * | 2017-09-08 | 2018-04-10 | 西南交通大学 | A kind of control circuit of DCMBoost power factor correcting converters |
Non-Patent Citations (2)
| Title |
|---|
| Bifrequency Pulse-Train Control Technique for Switching DC–DC Converters Operating in DCM;Jianping Xu;《IEEE》;20101028;全文 * |
| 脉冲序列控制开关DC-DC变换器研究;沙金;《中国优秀博士学位论文电子期刊》;20160815;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107465341A (en) | 2017-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| De Gusseme et al. | Digitally controlled boost power-factor-correction converters operating in both continuous and discontinuous conduction mode | |
| Zhao et al. | An improved variable on-time control strategy for a CRM flyback PFC converter | |
| Kim et al. | New modulated carrier controlled PFC boost converter | |
| CN109713889B (en) | Power factor correction circuit and control method thereof | |
| CN102664517B (en) | Power factor correction circuit | |
| CN103023299B (en) | Control method of power factor conversion device | |
| Wang et al. | CCM-DCM average current control for both continuous and discontinuous conduction modes boost PFC converters | |
| CN104467433B (en) | Method and device for controlling critical continuous mode unit power factor flyback converter | |
| JP6272691B2 (en) | Amplitude normalization circuit, power supply device and electronic device | |
| CN103296883B (en) | A kind of wide input voltage wide loading range straight convertor control method and device thereof | |
| CN102882378A (en) | Control method and device for unit power factor flyback converter in critical continuous mode | |
| TW201315117A (en) | System and method for controlling current and signal generating circuit thereof | |
| CN201839200U (en) | Power factor correction circuit with variable duty cycle control | |
| CN107546973A (en) | A kind of discontinuous mode pfc converter of low Harmonics of Input | |
| CN110719020B (en) | Control circuit and control method | |
| CN110545037A (en) | CRM boost PFC converter capacitance effect compensation circuit and compensation method | |
| Yao et al. | Three-phase single-switch DCM boost PFC converter with optimum utilization control of switching cycles | |
| Etz et al. | Comparison between digital average current mode control and digital one cycle control for a bridgeless PFC boost converter | |
| CN110518818B (en) | CRM (customer relationship management) buck-flyback PFC (Power factor correction) converter controlled in fixed frequency | |
| CN114744867A (en) | PFC boost circuit with parallel-connection interleaved CRM modes | |
| CN107370361B (en) | Sawtooth wave generating circuit and flyback, SEPIC and Buck-Boost power factor correction converter | |
| CN109309447B (en) | Constant switching frequency controlled CRM buck PFC converter | |
| CN117134586B (en) | Multi-mode working power factor correction control system | |
| US9270218B2 (en) | Power conversion apparatus and control method thereof | |
| CN203039585U (en) | Critical continuous mode unity power factor flyback converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20230411 |