CN107452801A - 高电压晶体管装置 - Google Patents

高电压晶体管装置 Download PDF

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Publication number
CN107452801A
CN107452801A CN201710367658.XA CN201710367658A CN107452801A CN 107452801 A CN107452801 A CN 107452801A CN 201710367658 A CN201710367658 A CN 201710367658A CN 107452801 A CN107452801 A CN 107452801A
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China
Prior art keywords
semiconductor
base material
semiconductor layer
electrode
body base
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S·H·博多
宽特·葛斯荷夫
朱尔根·法尔
彼特·杰瓦卡
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GlobalFoundries US Inc
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GlobalFoundries Inc
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Publication of CN107452801A publication Critical patent/CN107452801A/zh
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Abstract

本发明涉及高电压晶体管装置，其提供一种半导体装置，包含绝缘体上覆硅(SOI)基材，该SOI基材包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；以及晶体管装置，其中该晶体管装置包含由一部分该半导体主体基材所形成的栅极电极、由一部分该埋置型氧化物层所形成的栅极绝缘层、及形成于一部分该半导体层中的通道区。

Description

高电压晶体管装置
技术领域
大体上，本文中所揭示的专利标的关于集成电路，而且更尤指晶体管装置，尤其是高电压操作用的具有(超)低/零阈值电压的场效晶体管。
背景技术
半导体晶圆上形成的集成电路一般包括大量电路元件，该等电路元件形成电气电路。除了举例如场效晶体管及/或双极晶体管等主动装置外，集成电路还可包括诸如电阻器、电感器及/或电容器等被动装置。特别的是，在使用CMOS技术制作复杂集成电路期间，数百万个晶体管，亦即N通道晶体管及P通道晶体管，是在包括结晶半导体层的基材上形成。
举例而言，MOS晶体管无论是N通道晶体管或P通道晶体管，都包含所谓由高掺杂漏极与源极区的界面所形成的PN接面(junction)，该漏极区与该源极区之间布置有反相或弱式掺杂通道区。通道区的导电性即导电通道的驱动电流能力，是通过形成于该通道区附近的栅极电极并以薄绝缘层与其分隔的栅极电极来控制。通道区的导电性在对栅极电极施加适当控制电压而形成导电通道时，还取决于掺质浓度、多数电荷载子的迁移率，对于通道区顺着晶体管的宽度方向的给定延展，还取决于源极与漏极区之间的距离，该距离亦称为通道长度。因此，结合对栅极电极施加控制电压时于绝缘层下面快速建立导电通道的能力，通道区的整体导电性实质决定MOS晶体管的效能。
对于整流及/或切换应用，举例而言，需要维持高供应电压(VDD)的高电压(即高供应电压)晶体管。开发用于整合功率开关与控制电路的单芯片制程在功率IC开发领域中是主要趋势。举例而言，LDMOS(侧向双扩散MOS)制程目前正应用于制造单块IC。举例而言，作为MOSFET的变种，LDMOS FET是射频功率放大器的关键组件，在基站中用于个人通讯系统(例如，GSM、EDGE等)。高崩溃电压是LDMOS FET的最重要优点。然而，LDMOS FET无法在完全耗尽型绝缘体上覆硅(Fully Depleted Silicon-on Insulator；FDSOI)方法里轻易地整合于(MOS)FET的制造程序中。另一方面，根据完全耗尽型绝缘体上覆硅(FDSOI)方法所产生的常见MOS FET由于间隔物薄及或栅极氧化物衰减而未维持高供应电压(例如，VDD>1.8V)。
图1a绘示包含半导体基材101、埋置型氧化物层102及半导体层103的SOI基材上所形成的典型FDSOI场效晶体管(FET)100。FDSOI FET 100可在22纳米节点上制造，并且包含栅极电极104、隆起源极105与隆起漏极106、以及栅极介电质107。间隔物108是在栅极电极104的侧壁上形成。FDSOI FET 100适用于以低于1.8V的供应电压操作。然而，实际上，特定应用中需要大于3V的供应电压，例如，高频切换操作时便需要。如果对栅极电极104与漏极106施加电压(源极105连接至接地)，如3.3V，则薄栅极介电质107及薄间隔物108出现崩溃，并且FDSOI FET 100的操作劣化，或FDSOI FET 100完全无法操作。
所属技术领域中已知有用以在FDSOI FET(举例而如图1a所示的FDSOI FET 100)的制造程序流程中共整合高电压晶体管装置的方法。图1b展示包含P通道FDSOI FET 110(类似于图1a所示的FDSOI FET 100)及P通道高电压FET 120的半导体装置的一实施例。制造始于提供包含半导体主体基材111、埋置型氧化物层112及半导体层113的SOI基材。P通道FDSOI FET 110包含栅极电极114、隆起源极115与隆起漏极116、以及栅极介电质117。提供多层绝缘结构118，其包含在栅极电极114的侧壁上形成的间隔物。此外，栅极电极114、隆起源极115与隆起漏极116的表面上形成硅化物层119以增强电接触特性。
基于上述理由，无法形成作为FDSOI装置的高电压FET 120。反而，必须将高电压FET 120形成为在半导体主体基材111中形成具有通道区的主体装置。高电压FET 120包含栅极电极124。通过适当的掺杂而在半导体主体基材111中形成源极区125与漏极区126。提供多层间隔物结构128，并且通过形成硅化物层129将栅极电极124、及源极区125与漏极区126硅化，可连同硅化物层119在单一制程中形成硅化物层129。
然而，高电压FET 120与FDSOI FET 110的共整合涉及许多单独的掩模与沉积步骤，尤其是相比于纯FDSOI处理具有数种附加掩模的双氧化物与间隔物处理方案。
鉴于上文，本发明关于晶体管装置、及用于形成晶体管装置的技术，可用于高频、高电压操作，具有可在FDSOI制造程序流程中整合但不使制造程序因另外的沉积与掩模步骤而更复杂的高可靠度。
发明内容
以下介绍本发明的简化概要，以便对本发明的一些态样有基本的了解。本概要并非本发明的详尽概述。用意不在于指认本发明的重要或关键要素，或叙述本发明的范畴。目的仅在于以简化形式介绍一些概念，作为下文更详细说明的引言。
大体上，本文中所揭示的专利标的关于半导体装置、及用于制作该半导体装置的方法，其中以完全耗尽型绝缘体上覆硅(FDSOI)技术为基础，可增强N通道晶体管及P通道晶体管的晶体管效能。尤其是，提供容许供应电压高于2.5V或3V的高电压FET，其举例而言，可在FDSOI FET制造程序流程里按照共整合方式来制造。
本文中所揭示的一种说明性半导体装置包含：绝缘体上覆硅(SOI)基材，该SOI基材包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；以及晶体管装置，其中该晶体管装置包含由一部分该半导体主体基材所形成(或在其中形成)的栅极电极、由一部分该埋置型氧化物层所形成(或在其中形成)的栅极绝缘层、及形成于一部分该半导体层中(或由其所形成)的通道区。
再者，提供一种半导体装置，其包含：绝缘体上覆硅(SOI)基材，该SOI基材包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；第一晶体管装置，例如FDSOI FET，其包含形成于该半导体层上方的第一栅极电极、及形成于该第一栅极电极与该半导体层之间的的第一栅极介电质，举例而言，第一栅极介电质包含高k(例如，k>5)介电材料；以及第二(高电压)晶体管装置，其包含形成于该半导体主体基材中(或由其某部分所形成)的第二栅极电极、及形成于该埋置型氧化物层中(或由其某部分所形成)的第二栅极介电质。
一种形成本文中所揭示半导体装置的说明性方法包括：提供绝缘体上覆硅(SOI)基材，该SOI基材包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；以及在该绝缘体上覆硅基材中及上形成第一晶体管装置，其包括下列步骤：在该半导体层上形成第一栅极绝缘层、及在该第一栅极绝缘层上形成第一栅极电极。该方法更包括在该绝缘体上覆硅基材中形成第二晶体管装置，其包括下列步骤：在该半导体主体基材中形成(或由其某部分形成)第二栅极电极、及在该埋置型氧化物层中形成(或由其某部分形成)第二栅极绝缘层。尤其是，该第一晶体管装置可以是低电压FDSOI FET，并且该第二晶体管装置可以是高电压晶体管。该第二晶体管可以是可操作于较高电压(例如，以高于2.5V或3V的供应电压操作)的低阈值电压或超低阈值电压晶体管。
从而制造或提供的晶体管可在高频应用中当作切换装置使用。亦提供一种驱动半导体装置(晶体管装置)的方法，其中该半导体装置包含绝缘体上覆硅(SOI)基材，该SOI基材包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；以及晶体管装置，其中该晶体管装置包含由一部分该半导体主体基材所形成(或在其中形成)的栅极电极、由一部分该埋置型氧化物层所形成(或在其中形成)的栅极绝缘层、及形成于一部分该半导体层中(或由其所形成)的通道区、例如形成于该半导体层上方的源极与漏极区、形成于该半导体层上方的上电极、及形成于该源极与漏极区和该上电极之间的侧壁间隔物。该方法包括施加大于2V(例如，大于2.5V或3V、或在2-3.6V的范围内)的第一电压至栅极电极，施加与该第一电压具有同值的第二电压至漏极，施加小于2V(例如，约1.8V)的第三电压至上电极，以及连接源极区至接地。
附图说明
本发明可搭配附图参照以下说明来了解，其中相似的参考元件符号表示相似的元件，并且其中：
图1a绘示先前技术的FDSOI FET；
图1b绘示先前技术的包含FDSOI FET及高电压FET的半导体装置；
图2根据本发明的一说明性实施例，绘示高电压FET装置；
图3根据本发明的一说明性实施例，绘示包含低阈值电压的半导体装置-高供应电压FET装置；以及
图4根据本发明的一实施例，绘示包含超低阈值电压的半导体装置-高供应电压FET装置。
尽管本文所揭示的专利标的易受各种修改和替代形式所影响，其特定具体实施例仍已通过图式中的实施例予以表示并且在本文中予以详述。然而，应了解的是，本文中特定具体实施例的说明用意不在于将本发明限制于所揭示的特定形式，相反地，如随附权利要求所界定，用意在于涵盖落于本发明的精神及范畴内的所有修改、均等例、及替代方案。
符号说明：
10 晶体管装置或场效晶体管(FET)装置
11 半导体主体基材
12 埋置型氧化物(BOX)层
13 半导体层
14 上电极
15 源极、源极电极、隆起源极区或隆起半导体区
16 漏极、漏极电极、隆起漏极区或隆起半导体区
17 介电层或栅极介电质
18 侧壁间隔物
19 (前)栅极电极
20 半导体装置
20a N通道FET
20b P通道FET
21 半导体主体基材
22 埋置型氧化物(BOX)层
23 半导体层
24、24' 上电极
25、25' 源极电极
26、26' 漏极电极
27、27' 栅极介电质
28a P型井
28b N型井
29 浅沟槽隔离(STI)
30 半导体装置
30a N通道FET
30b P通道FET
31 半导体主体基材
32 埋置型氧化物(BOX)层
33 半导体层
34、34' 上电极
35、35' 源极电极
36、36' 漏极电极
37、37' 栅极介电质
38a N型井
38b P型井
39 浅沟槽隔离(STI)
100 FDSOI FET
101 半导体基材
102 埋置型氧化物层
103 半导体层
104 栅极电极
105 源极或隆起源极
106 漏极或隆起漏极
107 栅极介电质
108 间隔物
110 FDSOI FET或P通道FDSOI FET
111 半导体主体基材
112 埋置型氧化物层
113 半导体层
114 栅极电极
115 隆起源极
116 隆起漏极
117 栅极介电质
118 多层绝缘结构
119 硅化物层
120 高电压FET或P通道高电压FET
124 栅极电极
125 源极区
126 漏极区
128 多层间隔物结构
129 硅化物层
A、B、C、D 接触。
具体实施方式
下面说明本发明的各项说明性具体实施例。为了澄清，本说明书中并未说明实际实作态样的所有特征。当然，将会领会旳是，在开发任何此实际具体实施例时，必须做出许多实作态样特定决策才能达到开发者的特定目的，例如符合系统有关及业务有关的限制条件，这些限制条件会随实作态样不同而变。此外，将了解的是，此一开发努力可能复杂且耗时，虽然如此，仍会是受益于本发明的所属领域技术人员的例行工作。
以下具体实施例经充分详述而使所属领域技术人员能够利用本发明。要理解的是，其它具体实施例基于本发明将显而易见，并且可施作系统、结构、程序或机械变更而不脱离本发明的范畴。在以下说明中，提出特定数值细节是为了得以透彻理解本发明。然而，将显而易见的是，本发明的具体实施例无需此等特定细节也可予以实践。为了避免混淆本发明，并且详细揭示一些众所周知的电路、系统组态、结构组态以及程序步骤。
本发明现将参照附图作说明。各种结构、系统及装置在图式中只是为了阐释而绘示，为的是不要因所属领域技术人员众所周知的细节而混淆本发明。虽然如此，仍将附图包括进来以说明并阐释本发明的说明性实施例。本文中使用的字组及词组应了解并诠释为与所属领域技术人员了解的字组及词组具有一致的意义。与所属领域技术人员了解的通常或惯用意义不同的词汇或词组(即定义)的特殊定义，用意不在于通过本文词汇或词组的一致性用法提供暗示。就一词汇或词组用意在于具有特殊意义的方面来说，即有别于所属领域技术人员了解的意义，此一特殊定义应会按照为此词汇或词组直接且不含糊地提供此特殊定义的定义方式，在本说明书中明确提出。
空间参考“顶端”、“底端”、“上”、“下”、“垂直”、“水平”及类似者于本文中使用时，若涉及FET装置的结构，可为求便利性而使用。这些参考的用意在于仅为了教示目的而以与图式一致的方式加以使用，而且用意不在于当作FET结构的绝对参考。举例而言，FET可按照与图式所示方位不同的任何方式予以空间定向。提及图式时，“垂直”用于指称为正交于半导体层表面的方向，而“水平”用于指称为平行于半导体层表面的方向。“上”用于指称为远离半导体层的垂直方向。安置于另一元件“上面”(“下面”)的一元件相比于该另一元件，位于较远离(较靠近)半导体层表面处。
如所属领域技术人员完整阅读本申请书后将轻易了解的是，本方法适用于例如NMOS、PMOS、CMOS等各种技术，并且原则上轻易适用于各种装置，包括但不限于逻辑电路、记忆体装置、SRAM装置等。本文中所述的技术与技术可用于制作MOS集成电路装置，包括NMOS集成电路装置、PMOS集成电路装置、以及CMOS集成电路装置。尤其是，本文中所述的程序步骤搭配形成集成电路用栅极结构的任何半导体装置制作程序来利用，此等集成电路包括平面型及非平面型这两种集成电路。虽然用语“MOS”适当地指具有金属栅极电极及氧化物栅极绝缘体的装置，该用语全文用于意指包括传导栅极电极(金属或其它传导材料都可以)的任何半导体装置，该传导栅极电极置于栅极绝缘体(氧化物或其它绝缘体都可以)上方，进而置于半导体主体基材上方。
大体上，说明一种具有(超)低阈值电压的高电压晶体管装置，以及如何制造及操作具有此一晶体管装置而容许用于较高供应电压(高电压操作)的半导体装置。请参阅图2、3及4，现将更详细描述说明性具体实施例。
如图2所示，根据本发明的半导体装置包含在SOI基材(尤其是FDSOI基材)上形成的FET装置10。FET装置10可以是MOSFET。SOI基材包含半导体主体基材11、形成于半导体主体基材11上的埋置型氧化物(buried oxide；BOX)层12、以及形成于BOX层12上的半导体层13(主体层)。半导体层13可包含大量的硅，原因在于高集成密度的半导体装置可基于硅进行量产来形成，理由是可用性已增强且过去数十年已开发建置良好的制程技术。然而，可使用任何其它适当的半导体材料，例如，含有诸如锗、碳、硅/锗、硅/碳、其它II-VI族或III-V族半导体化合物及类似者等其它等电子组分(iso-electronic components)的硅基础材料。
BOX层12可包含(二)氧化硅或硼硅酸玻璃或硼磷硅酸盐玻璃(BPSG)。BOX层可由不同层所组成，该等不同层其中一者可包含BPSG、或SiO2-包含硼或磷的化合物。半导体主体基材11可包含硅或由硅所组成，尤其是单晶硅。其它材料可用于形成半导体主体基材11，举例如锗、硅锗、磷酸镓、砷化镓等。半导体层13的厚度范围可以是5纳米至30纳米，尤其是5纳米至15纳米，并且BOX层12的厚度范围可以是10纳米至50纳米，尤其是10纳米至30纳米，而且更特别的是15纳米至25纳米。
可在绝缘体上覆硅基材中形成浅沟槽隔离(shallow trench isolation；STI)区(图2未示)，以便将晶体管装置10与SOI基材上形成的IC的其它电气组件电隔离。STI区在形成方面，可贯穿半导体层13及BOX层12并且在半导体主体基材11中蚀刻开口，以及以例如一些氧化物材料的一些绝缘材料来填充该开口。
FET装置10包含上电极14、源极15与漏极16。上电极14通过栅极介电质17与半导体层13分开。在上电极14的侧壁上形成侧壁间隔物18。上电极14及源极15与漏极16的上表面可进行硅化。硅化作用可包含在隆起半导体区15与16的表面、及上栅极14的上表面上沉积NiPt、Ni或Co层，以及进行一或多个热退火程序。产生的硅化区提供低电阻接触。
上电极14可包含多晶硅层及/或含金属层。含金属层举例而言，可包含氮化钛(TiN)、氮化钽(TaN)、钽(Ta)、钨(W)其中至少一者。含金属层可以较薄，所具厚度低于50纳米，尤其是低于20纳米。上电极14可在含金属层上面包含半导体层，举例而言，包含硅，例如未掺杂多结晶硅。栅极电极材料的半导体层可包含未掺杂多结晶硅。功函数调整层可设于上电极14的金属栅极层与栅极介电质17之间。
栅极介电质17可包含高k材料或由其所组成，所具介电常数举例为k>5。高k材料可包含诸如氧化铪、二氧化铪及氮氧化铪硅其中至少一者的过渡金属氧化物。根据一些例示性具体实施例，(高k)介电层17可直接在半导体层13上形成。根据其它具体实施例，(高k)介电层17可在绝缘层(图未示)上形成，该绝缘层包含形成于半导体层13上的氧化硅。功函数调整层可包含氮化钛(TiN)或所属技术领域已知的任何其它适当的功函数调整金属或金属氧化物。
侧壁间隔物18可包括二氧化硅，并且可通过随后磊晶生长或沉积栅极结构的各别层件，并且适度将其蚀刻，按照多层形式来提供。
源极与漏极电极15与16可通过(选择性)磊晶，由半导体层所形成，例如包含硅的半导体层。藉此，相邻于侧壁间隔物18形成隆起源极与漏极区15与16。隆起源极与漏极区15与16举例而言，可具有范围20纳米至50纳米的厚度。
注意到的是，形成具有高k金属栅极(high-k metal gate；HKMG)结构的平面型或3D晶体管基本上有两种众所周知的处理方法。在取代栅极技术中，所谓的“虚设(dummy)”或牺牲栅极结构在初始时形成，并且在进行用以形成装置的许多程序操作中留在原位，例如形成掺杂源极/漏极区，进行退火程序以修复因离子布植程序对基材所造成的破坏，并且活化植入的掺质材料。在程序流程中的一些制点，移除牺牲栅极结构以界定就装置形成HKMG栅极结构处的栅极凹穴。另一方面，使用“栅极先制(gate first)”技术涉及跨布基材形成材料层堆叠，其中材料堆叠包括高k栅极绝缘层、一或多个金属层、多晶硅层、以及保护性覆盖层，例如氮化硅。进行一或多个蚀刻程序以图案化材料堆叠，藉以就晶体管装置界定基本栅极结构。取代栅极程序流程及栅极先制程序流程两者都可根据本发明来运用。
根据本发明，FET装置10包含在半导体主体基材11中形成并通过接触A接触的(前)栅极电极19。(前)栅极电极19可通过一部分半导体主体基材11来形成，亦即，半导体主体基材11可作用为(前)栅极电极19。上电极14通过接触B来接触，源极电极15通过接触C来接触，并且漏极电极16通过接触D来接触(请参阅图2)。可对接触A与D施加高于2V(尤其是高于3V)的供应电压，并且藉此施加至前栅极电极19与漏极电极16，并且可使接触C，从而还有源极15，接触至接地。
根据替代实施例，上电极14可维持处于浮动状态(浮动上电极14)或可透过接触B施加电压至上电极14，藉此容许对FET装置10的操作进行双栅极控制。双栅极控制容许获得所欲强度的导通电流。施加至上电极14的电压若有限而使得上电极14作用为背电极，则必须观察的是上电极14与源极15之间的电压降、及上电极14与漏极16之间的电压降必须够低，才能防止间隔物18崩溃。举例而言，对漏极电极16与前栅极电极19施加3.6V时，若高于1.8V的电压降出现崩溃，则施加至上电极14的电压必须不超过3.6V至1.8V。
在图2所示的组态中，较厚的BOX层12不仅用于前栅极电极19的栅极氧化物(栅极介电质)，还用于使半导体主体基材11中形成的前栅极电极19与源极电极15及漏极电极16电绝缘。因此，可避免类似于图2所示栅极介电质17的栅极介电质出现崩溃、及类似于图2所示侧壁间隔物18的间隔物出现崩溃的问题。尤其是，可将如图2所示FET装置10的高电压FET的形成轻易地整合在用于制造FDSOI(MOS)FET的程序流程中，举例而言，用于制造适用于较低电压(例如<1.8V)操作的单栅极或延展栅极FET。举例而言，图2所示的晶体管装置可与如图1a所示的晶体管装置予以共制造，并且图2所示的晶体管装置的背栅极可由相同材料所构成，及/或在相同制造程序中，如用于形成图1a所示的晶体管装置100的栅极电极104。
注意到的是，通过在不同区域中适度掺杂半导体主体基材11，可微调类似于图2所示的高电压装置。举例而言，漏极饱和电流可通过适当良好形成及/或选择涉及的功函数来调整。
图3根据本发明，绘示包含低阈值电压FET装置容许高电压操作的半导体装置20。半导体装置20包含N通道FET 20a及p通道FET 20b。N通道FET 20a及P通道FET 20b是在FDSOI基材上形成，FDSOI基材包含半导体主体基材21、形成于半导体主体基材21上的埋置型氧化物(BOX)层22、及形成于BOX层22上的半导体层23(主动层)。通道区是在半导体层22中形成。N通道FET 20a及P通道FET 20b可以是延展栅极装置，其举例而言，包含延展至图3所示区域外侧的半导体主体基材21或BOX层22的栅极电极。可如图2所示内容所述就SOI基材的不同层件选择相同材料。尤其是，半导体层23可以是结晶硅层。
N通道FET 20a与P通道FET 20b两者分别包含上电极24、24'、源极电极25、25'与漏极电极26、26'。上电极24、24'是自半导体层23起通过栅极介电质27、27'分开。再次地，图2所示内容中所述的材料亦可用于图3所示的对应层。尤其是，上电极24、24'可包含金属栅极层及/或多晶硅栅极层，并且栅极介电质27、27'可代表比二氧化硅其中一者具有更大介电常数的高k介电质，例如：k>5。
P型井28a是在N通道FET 20a下面的半导体主体基材21中通过适度掺杂所形成，并且因此，N型井28b是在P通道FET 20b下面的半导体主体基材21中通过适度掺杂所形成。此外，STI 29是在半导体主体基材21中形成(并且贯穿半导体层23及BOX层22)。P型井28a遭到STI 29隔离的部分可具有P+掺杂上部区。因此，N型井28b遭到STI 29隔离的部分可具有N+掺杂上部区。
类似于参照图2所述的实施例，图3所示半导体装置20的半导体主体基材21有部分可当作前栅极用于N通道FET 20a及P通道FET 20b。上电极24与24'可浮动，或可当作背栅极用于双操作控制。P型井的隔离部分的源极25、25'与上部P+区、及N型井的隔离部分的上部N+区可连接至接地。操作时，可对部分半导体主体基材21所形成的漏极26、26'及前栅极电极施加3.6V或更大的较高供应电压。
图4根据本发明绘示包含超低阈值电压FET装置容许高电压操作的半导体装置30。半导体装置30包含N通道FET 30a及P通道FET 30b。N通道FET 30a及P通道FET 30b是在FDSOI基材上形成，FDSOI基材包含半导体主体基材31、形成于半导体主体基材31上的埋置型氧化物(BOX)层32、及形成于BOX层32上的半导体层33(主动层)。N通道FET 30a及P通道FET 30b可以是延展栅极装置，其具有延展至图4所示区域外侧的半导体主体基材31或BOX层32的栅极电极。可如图2所示内容所述就SOI基材的不同层件选择相同材料。尤其是，半导体层33可以是结晶硅层。
N通道FET 30a与P通道FET 30b两者分别包含上电极34、34'、源极电极35、35'与漏极电极36、36'。上电极34、34'是自半导体层33起通过栅极介电质37、37'分开。再次地，图2所示内容中所述的材料亦可用于图4所示的对应层。
N型井38a是在N通道FET 30a下面的半导体主体基材31中通过适度掺杂所形成，并且因此，P型井38b是在P通道FET 30b下面的半导体主体基材31中通过适度掺杂所形成。此外，STI 39是在半导体主体基材31中形成(并且贯穿半导体层33及BOX层32)。N型井38a遭到STI 39隔离的部分可具有N+掺杂上部区。因此，P型井38a遭到STI39隔离的部分可具有P+掺杂上部区。
类似于参照图2所述的实施例，图4所示半导体装置30的半导体主体基材31有部分可当作前栅极用于N通道FET 30a及P通道FET 30b。上电极34与34'可浮动，或可当作背栅极用于双操作控制。P型井的隔离部分的源极35、35'与上部P+区、及N型井的隔离部分的上部N+区可连接至接地。操作时，可对部分半导体主体基材31所形成的漏极36、36'及栅极电极施加3.6V或更大的较高供应电压。
在所有上述实施例中，本发明的半导体装置可与类似的半导体装置共整合，其中半导体基材不包含栅极电极(未当作栅极电极操作)，反而包含背栅极(当作背电极操作)。在不适用于高电压操作的这些半导体装置中，图2、3及4所示的上电极14、24、24'、34、34'形成(操作为)栅极电极。特别的是，图2、3及4所示的半导体装置可与类似于图1所示的半导体装置共整合。
结论是，提供一种用以在制造常见低电压FDSOI FET的程序流程中整合高电压FTE的措施。对于常见的低电压FDSOI FET，SOI基材的半导体主体基材可用于反偏压。这些装置的栅极电极是在SOI基材上面形成，并且通过栅极介电质与SOI基材的半导体层分开。相反地，高电压FTE包含当作前栅极电极的部分SOI基材，并且SOI基材上面形成的电极可用于反偏压。对于高电压FET，SOI基材的BOX层作用为栅极介电质，并且还将半导体主体基材中包含的栅极电极电隔离。因此，可轻易地将高电压FET的制造与适用于低电压操作的常见FDSOI FET的制造程序流程共整合，完全不需要另外的掩模与沉积步骤。
以上所揭示的特定具体实施例仅属描述性，正如本发明可用所属领域技术人员所明显知道的不同但均等方式予以修改并且实践而具有本文教示的效益。举例而言，以上所提出的程序步骤可按照不同顺序来进行。再者，如随附权利要求书中所述除外，未意图限制于本文所示构造或设计的细节。因此，证实可改变或修改以上揭示的特定具体实施例，而且所有此类变体全都视为在本发明的范畴及精神内。要注意的是，本说明书及所附权利要求书中如“第一”、“第二”、“第三”或“第四”的类用以说明各个程序或结构的术语，仅当作此些步骤/结构节略参考，并且不必然暗喻此些步骤/结构的进行/形成序列。当然，取决于精准声称的措辞，可或可不需要此些程序的排列顺序。因此，本文寻求的保护如所附权利要求书中所提。

Claims (15)

1.一种半导体装置，其包含：
绝缘体上覆硅(SOI)基材，其包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；以及
晶体管装置，其中，该晶体管装置包含由一部分该半导体主体基材所形成的栅极电极、由一部分该埋置型氧化物层所形成的栅极绝缘层、及形成于一部分该半导体层中的通道区。
2.如权利要求1所述的半导体装置，更包含形成于该半导体层上方的隆起源极与漏极区。
3.如权利要求2所述的半导体装置，更包含形成于该半导体层上方的上电极、及形成于该上电极的侧壁上和该隆起源极与漏极区与该上电极之间的侧壁间隔物。
4.如权利要求3所述的半导体装置，更包含另一晶体管装置，其中，该另一晶体管装置包含形成于该半导体层上方的栅极电极。
5.如权利要求1所述的半导体装置，更包含形成于该上电极与该半导体层之间的介电层。
6.如权利要求1所述的半导体装置，其中，该埋置型氧化物层具有约20纳米至30纳米的厚度，并且该半导体层具有约5纳米至20纳米的厚度。
7.一种半导体装置，其包含：
绝缘体上覆硅(SOI)基材，其包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；
第一晶体管装置，其包含形成于该半导体层上方的第一栅极电极、及形成于该第一栅极电极与该半导体层之间的第一栅极介电质；以及
第二晶体管装置，其包含形成于该半导体主体基材中的第二栅极电极、及形成于该埋置型氧化物层中的第二栅极介电质。
8.如权利要求7所述的半导体装置，更包含形成于该半导体主体基材中的P型井或N型井。
9.如权利要求7所述的半导体装置，其中，该第一晶体管装置更包含形成于该半导体主体基材中的背栅极。
10.如权利要求7所述的半导体装置，其中，该第二晶体管装置更包含形成于该半导体层上方的背栅极。
11.如权利要求7所述的半导体装置，其中，该第一晶体管装置包含形成于该半导体层中的第一通道区，并且该第二晶体管装置包含形成于该半导体层中的第二通道区。
12.一种形成半导体装置的方法，其包含：
提供绝缘体上覆硅(SOI)基材，其包含半导体主体基材、形成于该半导体主体基材上的埋置型氧化物层、以及形成于该埋置型氧化物层上的半导体层；
在该绝缘体上覆硅基材中及上形成第一晶体管装置，其包含：
在该半导体层上形成第一栅极绝缘层；以及
在该第一栅极绝缘层上形成第一栅极电极；以及
在该绝缘体上覆硅基材中形成第二晶体管装置，其包含：
在该半导体主体基材中形成第二栅极电极；以及
在该埋置型氧化物层中形成第二栅极绝缘层。
13.如权利要求12所述的方法，其中，形成该第一晶体管装置更包含在该半导体层上方形成该第一晶体管装置的第一隆起源极与漏极区，以及其中，形成该第二晶体管装置更包含在该半导体层上方形成该第二晶体管装置的第二隆起源极与漏极区。
14.如权利要求12所述的方法，其中，形成该第一晶体管装置更包含在该半导体层中形成该第一晶体管装置的第一通道区，以及其中，形成该第二晶体管装置更包含在该半导体层中形成该第二晶体管装置的第二通道区。
15.如权利要求12所述的方法，其中，形成该第二晶体管装置更包含由如同形成该第一晶体管装置的该第一栅极电极所用的材料在该半导体层上方形成背栅极。
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