CN107452676B - A kind of embolism forming method - Google Patents
A kind of embolism forming method Download PDFInfo
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- CN107452676B CN107452676B CN201710640184.1A CN201710640184A CN107452676B CN 107452676 B CN107452676 B CN 107452676B CN 201710640184 A CN201710640184 A CN 201710640184A CN 107452676 B CN107452676 B CN 107452676B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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Abstract
The present invention relates to a kind of embolism forming methods.Wherein, embolism forming method, including：Substrate is provided, dielectric layer is formed in substrate surface, hole is formed on dielectric layer；Bore at the openend of expanded hole hole；The first conductive layer is formed on dielectric layer surface, including the embolism portion being locally filled in hole；The first conductive layer of gap, certain media layer and part is removed, exposes the conductive plug of flush.Semiconductor devices sets dielectric layer in substrate surface, and dielectric layer has hole；Electric embolism is filled in hole, the flush of conductive plug and exposed to dielectric layer, and conductive plug is solid surfaces.The conductive plug that the method for the present invention is formed has that tight, resistance is low, high reliability.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of embolism forming method and the semiconductor with the embolism
Device.
Background technology
At present, in semiconductor storage device assembly, generally use forms the mode of embolism structure between the two metal layers
Realize the electrical connection between two metal layers.Since tungsten has good stepcoverage and gap filling performance, often adopt
Embolism is formed with the mode of chemical vapor deposition tungsten.
The formation quality of embolism influences the performance of device very big, if embolism forms second-rate, can cause interconnection electricity
Resistance increase influences the performance of device.However, with the continuous diminution of process node, for forming the depth of the hole opening of embolism
Width is improved than also corresponding, therefore is easy to cause and is difficult to, even into hole bottom, easily exist by the tungsten of chemical vapor deposition
The sidewall surfaces of hole opening form accumulation, cause to deposit to the tungsten in hole when not being filled up completely full hole just in opening
It is closed too early, and then makes to form gap inside the embolism to be formed, it is bad so as to cause the embolism performance formed.Further,
When removing extra tungsten metal subsequently through chemical mechanical grinding or etching technics, it can cause the cavity or gap in embolism
Exposed to outer, there are void defects in the embolism resulted in, influence the reliability that device subsequently connects.In the prior art,
The production in cavity or gap is reduced frequently with temperature, the adjusting parameters such as pressure and air-flow are reduced in chemical vapor deposition processes
It is raw, but the tungsten plug too high in resistance of generation, the conducting being unfavorable between metal layer are deposited under such circumstances.
Disclosed above- mentioned information is only used for strengthening the understanding of the background to the present invention in the introduction, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
The content of the invention
In view of this, the embodiment of the present application desirable to provide a kind of embolism forming method and with the embolism semiconductor device
Part, at least to solve problems of the prior art.
The technical solution of the embodiment of the present application is achieved in that one embodiment according to the application, provides a kind of bolt
Forming method is filled in, including：
Semiconductor substrate is provided, dielectric layer is formed in the substrate surface, is formed on the dielectric layer described in being connected to
The hole of substrate surface, the dielectric layer include a retaining layer portion and a sacrificial layer portion；
Expand the bore at the openend of described hole, to reduce depth-to-width ratio of the described hole at the openend, institute
It states and reaming inclined-plane is formed at the openend of hole, the depth on the reaming inclined-plane is less than the thickness in the sacrificial layer portion；
Form the first conductive layer includes embolism portion, filling in the upper surface , And of the dielectric layer and first conductive layer
In described hole, there is gap in the embolism portion, the gap extends along described hole length direction, under the gap
End is no more than the thickness definition scope in the sacrificial layer portion, and the upper end in the gap is no more than the shape of first conductive layer
Into surface；
The sacrificial layer portion is removed, to remove the gap and part first conductive layer simultaneously, until exposing table
The concordant conductive plug in face is in the thickness definition scope in the retaining layer portion.
In some embodiments, the technique for expanding the bore at the openend is using sputtering technology or grey chemical industry in situ
Skill makes the reaming inclined-plane form the first chamfering compared with the upper surface of the dielectric layer, and then expands the mouth of the openend
Footpath.
In some embodiments, further include：Before first conductive layer is formed, deposition barrier layer is in the dielectric layer
Upper surface and described hole bottom and side wall, so that first conductive layer and the embolism portion are on the barrier layer
Deposition is formed.
In some embodiments, the material on the barrier layer is selected from one of tungsten nitride, titanium and titanium nitride.
In some embodiments, further include：Before the barrier layer is formed, by deposition and annealing process in the hole
The substrate surface that hole bottom-exposed goes out forms the second conductive layer, so that the barrier layer is formed；Second conductive layer
Material is selected from one of titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide.
In some embodiments, further include：Wet clean process is carried out after second conductive layer is formed, removal is attached
It in second conductive layer, described hole madial wall and the surface impurity of the openend.
In some embodiments, first conductive layer is formed in the dielectric layer surface by chemical vapor deposition method
Be filled in described hole.
In some embodiments, the material of the dielectric layer is selected from oxide；The material of first conductive layer is selected from
In one of tungsten, copper, aluminium or polysilicon.
In some embodiments, first conduction on the dielectric layer surface is removed using chemical mechanical milling tech
Layer and the sacrificial layer portion.
A kind of semiconductor devices with embolism, including：
Semi-conductive substrate；
One dielectric layer, is formed at the surface of the substrate, and the dielectric layer has the hole for being connected to the substrate surface
And first flat surface, the opening of described hole are exposed to first flat surface；And conductive plug, it is filled in described hole
In, the conductive plug is the homogeneous solid being made of the first conductive layer, and the conductive plug has the second flat surface, described
Second flat surface is without being recessed and filling up the opening of described hole, and second flat surface is with first flat surface same
One plane.
In some embodiments, it is provided with barrier layer between described hole surface and the conductive plug.
In some embodiments, it is provided between the barrier layer of described hole bottom and described hole lower surface
Second conductive layer.
In some embodiments, the material of first conductive layer is tungsten.
In some embodiments, the barrier layer has ring edge, is revealed in the opening of described hole and described
Between first flat surface and second flat surface, second flat surface is formed via the ring edge and first flat surface
In a continuous surface.
The present invention due to using the technology described above, has the following advantages：1st, the present invention is due to changing hole opening
Caliber size and shape at end reduce the depth-to-width ratio of hole, hence the material of the first conductive layer of subsequent deposition is easy
In entering inside hole, make the conductive plug inner homogeneous to be formed fine and close, and due at open end parallel to substrate table
The dimension enlargement in face direction so that the material of the first conductive layer is not susceptible to accumulate in the sidewall surfaces close to openend, is open
End will not premature generation closed-ended question, so as to inhibit formed the first conductive layer in generate larger gap, make
Obtain the first formed conductive layer dense uniform, electric performance stablity.2nd, since the openend of hole is extended, in openend
The time lengthening of packing phenomenon is formed, it is more to be filled into the material of the first conductive layer in hole, so that being deposited in opening
Position of the material of first conductive layer at end when being closed moves up, i.e., moves on to openend upper end on the position that gap is formed,
Part can remove less dielectric layer and first in subsequent chemical mechanical planarization process and lead beyond dielectric layer surface
Electric layer is so as to forming the conductive plug of flush, save cost and improve production efficiency.3rd, due to the conductive plugs of the present invention
Gap is not contained in plug, therefore the low resistance of the first conductive layer can be kept, reduce contact resistance and increases read/write speed, together
When reduce chemical vapor deposition temperature, pressure and flow.4th, the conductive plug that the method for the present invention is formed has tight, resistance
Low, high reliability.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, outside embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature will be what is be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent the same or similar through the identical reference numeral of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings depict only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the flow chart of the embolism forming method of the present invention；
Fig. 2 is the structure diagram for forming dielectric layer on substrate of the present invention；
Fig. 3 is the structure diagram of the chamfering of the hole openend of the present invention；
Fig. 4 is the structure diagram of the first conductive layer deposition of the present invention；
Fig. 5 is the structure diagram of the conductive plug of the present invention；
Fig. 6 is the deposition process schematic diagram of the second conductive layer of the present invention；
Fig. 7 is the structure diagram of the second conductive layer deposition of the present invention；
Fig. 8 is the structure diagram of the barrier deposition of the present invention；
Fig. 9 is the structure diagram of the semiconductor devices of the present invention.
Reference numeral：
1- substrates；2- dielectric layers；21- retaining layers portion；22- sacrificial layers portion；The first flat surfaces of 23-；3- holes；31- is open
End；The first conductive layers of 4-；41- embolisms portion；42- gaps；The lower end in 43- gaps；The upper end in 44- gaps；5- conductive plugs；
The second flat surfaces of 51-；6- barrier layers；The second conductive layers of 7-.
Specific embodiment
Hereinafter, some exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", " go up ", " under ", " preceding ", " afterwards ", " left side ", " right side ", " heavily fortified point, and directly ", " level ", " top ", " bottom ", " is interior ", " outside ", "
Wait ", " counterclockwise " orientation of instructions clockwise or position relationship be based on orientation shown in the drawings or position relationship, merely to
Convenient for the description present invention and simplify description rather than instruction or imply signified device or element must have specific orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second " are only
For descriptive purposes, and it is not intended that instruction or hint relative importance or the implicit number for indicating indicated technical characteristic
Amount." first " is defined as a result, and the feature of " second " can be expressed or implicitly includes one or more spy
Sign.In the description of the present invention, " multiple " are meant that two or more, unless otherwise specifically defined.
In the description of the present invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected or be integrally connected:It can
To be mechanical connection or electrical connection or can mutually communicate；It can be directly connected, it can also be by between intermediary
It connects connected, can be the interaction relationship of connection inside two elements or two elements.For the ordinary skill of this field
For personnel, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature its " upper " or it " under "
It can be contacted directly including the first and second features, it is not to contact directly but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " top " and " above " include first spy
Sign is directly over second feature and oblique upper or is merely representative of fisrt feature level height higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and " following " directly over second feature and oblique upper or be merely representative of including fisrt feature
Fisrt feature level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component and setting of specific examples are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, between itself not indicating discussed various embodiments and/or setting
Relation.In addition, the present invention provides various specific techniques and material example, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
As shown in Figure 1, present embodiments providing a kind of embolism forming method, following steps are specifically included：
Semiconductor substrate 1 is provided, dielectric layer 2 is formed on 1 surface of Semiconductor substrate, connection substrate 1 is formed on dielectric layer 2
The hole 3 (as shown in Figure 2) of upper surface, dielectric layer 2 include retaining layer portion 21 and sacrificial layer portion 22；Wherein, retaining layer portion 21 is
2 lower part of dielectric layer, sacrificial layer portion 22 are 2 top of dielectric layer, and retaining layer portion 21 and sacrificial layer portion 22 collectively form dielectric layer 2, and
The two is 2 body of dielectric layer and non-physical visible layer, for the ease of difference description so that 2 top of dielectric layer be needed to be removed portion
Divide the sacrificial layer portion 22 that is named as, and dielectric layer 2 is not removed part names as retaining layer portion 21.
Expand the bore at the openend 31 of hole 3, increase opening size, and the caliber size inside hole 3 is constant, with
Reduce depth-to-width ratio of the hole 3 at openend 31, form reaming inclined-plane (as shown in Figure 3) at the openend 31 of hole 3, reaming is oblique
The depth in face is less than the thickness in sacrificial layer portion 22；
As shown in figure 4, form the first conductive layer 4 includes embolism portion in the upper surface , And of dielectric layer 2 and the first conductive layer 4
41, embolism portion 41 is filled in hole 3, has gap 42 in embolism portion 41, and gap 42 extends along 3 length direction of hole, gap
42 lower end 43 is no more than the thickness definition scope in sacrificial layer portion 22, and the upper end 44 in gap 42 is no more than the first conductive layer 4
Formation surface；
As shown in figure 5, sacrificial layer portion 22 is removed, to remove gap 42 and the first conductive layer of part 4 simultaneously, until exposing
The conductive plug 5 of flush is in the thickness definition scope in retaining layer portion 21.
In some embodiments, sputtering technology or grey chemical industry in situ can be used in the technique of the bore at enlarged openings end 31
Skill makes reaming inclined-plane form the first chamfering (as shown in Figure 3), and then enlarged openings by bombardment compared with the upper surface of dielectric layer 2
The bore at end 31, the material convenient for the first conductive layer 4 of subsequent deposition are easy to enter inside hole 3, make the conductive plugs to be formed
The densification of 5 inner homogeneous is filled in, and due to the dimension enlargement parallel to substrate surface direction at open end 31, even if first is conductive
The material of layer 4 is accumulated close to the sidewall surfaces of openend 31, openend 31 will not premature generation closed-ended question, from
And it can inhibit to generate larger gap in formed the first conductive layer 4.So that the first conductive layer dense uniform formed,
Electric performance stablity.
In a preferred embodiment, the expansion of openend 31 is realized using argon sputtering technology.It should be noted that it opens
The change method at mouth end 31 is not limited to mode mentioned above, any way of the prior art can be used, as long as can realize
The change of the shape and size of openend 31.
In a preferred embodiment, the angular range of the first chamfering is preferably 45 ° between 30 °~70 °, this angle
The gradient of first chamfering of degree is moderate, the material deposition velocity of the first conductive layer 4 when can improve deposition, and will not be because of stream
Dynamic excessive velocities cause the first conductive layer 4 of opening to be accumulated, and are closed opening too early.
In another preferred embodiment, the first chamfering can be fillet, deposit the first conductive layer 4 more smooth.
In some embodiments, 2 surface of dielectric layer around openend 31 forms the second chamfering (not shown), the
Two chamfer angles are not more than the angle of the first chamfering, make 4 more smooth filling hole of the first conductive layer.
It should be noted that when 31 too small openings of openend of the hole 3 on substrate 1, first in openend 31 falls
Angle it is circumferential by sputtering technology or cineration technics in situ, bombard 2 surface of dielectric layer of the first chamfering dimension, formed and the
Second chamfering of one chamfering connection, preferred second chamfer angle is equal with the first chamfer angle, so as to form smooth guiding
Structure further expands the bore of the openend 31 of hole 3, the material deposition speed of the first conductive layer 4 when improving deposition
Degree prevents material stacking openend 31 to be closed too early.
In some embodiments, before the first conductive layer 4 is formed, deposition barrier layer 6 is in the upper surface of dielectric layer 2 and hole
The bottom and side wall in hole 3, so that the deposition of the first conductive layer 4 and embolism portion 41 on barrier layer 6 forms (as shown in Figure 7).It needs
It is noted that one or more combinations of the material on barrier layer 6 in tungsten nitride, titanium or titanium nitride.Barrier layer 6 is used for
Stop that the material of the first conductive layer 4 is spread into substrate 1 and dielectric layer 2, while can also play and more preferably be connect with the first conductive layer 4
The purpose of conjunction prevents the generation removed.
In a preferred embodiment, the material of the first conductive layer 4 is selected from tungsten, at this time 4 He of the first conductive layer
Zygosity between barrier layer 6 is good.It should be noted that barrier layer 6 is by chemical vapor deposition technique, gas phase physical deposition
Technique or atomic layer deposition are formed on the surface of hole 3 and the surface of dielectric layer 2.
In some embodiments, before barrier layer 6 is formed, the formation material of deposit second conductive layer 7 is in dielectric layer 2
The bottom and side wall of upper surface and hole 3 (as shown in Figure 6), and pass through what deposition and annealing process went out in 3 bottom-exposed of hole
1 surface of substrate forms the second conductive layer 7 (as shown in Figure 7), so that barrier layer forms 6 (as shown in Figure 8)；Second conductive layer 7
Material is selected from one of titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide.
Wherein, the forming process of the second conductive layer 7 is：After the caliber size of the openend of hole 3 31 changes, in hole
At 3 openend 31 Co, CoSi and Co are deposited to the inner wall of hole 32The combination material of Si carries out annealing process, group after deposition
It closes material and a layer component of the bottom for being deposited on hole 3 is formed by reacting as CoSi2The second conductive layer 7.
In some embodiments, wet clean process is carried out after the second conductive layer 7 is formed, removal is attached to second and leads
The surface impurity of electric layer 7,3 madial wall of hole and openend 31, the surface for making above-mentioned three is smoother, and pattern is more excellent, avoids
Influence the performance of the conductive plug eventually formed.Wherein, the cleaning liquid level acidic cleaning solution that wet clean process is used.
In some embodiments, the first conductive layer 4 is formed in 2 surface of dielectric layer and filling by chemical vapor deposition method
In hole 3.The material of first conductive layer 4 is selected from one of tungsten, copper, aluminium or polysilicon.
In some embodiments, the first conductive layer 4 on chemical mechanical milling tech removal dielectric layer 2 surface and sacrificial is utilized
Domestic animal layer portion 22.
In some embodiments, the material of dielectric layer 2 is selected from oxide, is chosen in particular from silica, silicon nitride or nitrogen
One or more combinations in silica.
In some embodiments, dielectric layer 2 is formed in 1 surface of substrate by depositing operation；Hole 3 passes through etching technics shape
Into in dielectric layer 2.Specifically, the formation process of dielectric layer 2 is chemical vapor deposition method or physical gas-phase deposition；Hole
The formation process in hole 3 is anisotropic dry etch process.
In some embodiments, substrate 1 includes semiconductor base, is formed in semiconductor substrate surface or semiconductor base
Semiconductor devices, for the conductive structure that is electrically connected semiconductor devices and for being electrically isolated semiconductor devices and conductive knot
The insulating layer of structure.Semiconductor base includes silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium on insulator
Substrate, glass substrate.Semiconductor devices includes transistor, and the first conductive layer 4 is electrically connected with transistor, realizes read/write function.
Illustrate the embolism forming method in the present invention below by a preferred embodiment.
Embodiment
A kind of embolism forming method, comprises the following steps：
1) Semiconductor substrate 1 is provided, dielectric layer 2 is formed by chemical vapor deposition method on 1 surface of substrate, in dielectric layer
The hole 3 of 1 upper surface of substrate is exposed on 2 by the formation of anisotropic dry etch process；
2) using the bore at the openend 31 of sputtering technology or cineration technics expansion hole 3 in situ, opposite reduction hole
The depth-to-width ratio in hole 3；
3) Co, CoSi and Co are deposited to the inside of hole 3 at the openend of hole 3 312The combination material of Si；
4) annealing process is carried out after depositing, combination material forms a layer component of the bottom for being deposited on hole 3 by reacting
For CoSi2The second conductive layer 7；
5) wet clean process is carried out after the second conductive layer 7 is formed, removal is attached to the second conductive layer 7, in hole 3
Side wall and the surface impurity of openend 31；
6) barrier layer 6 is deposited in the side wall of hole 3 and the upper surface of the second conductive layer 7；
7) form the first conductive layer 4 in the upper surface of dielectric layer 2, the first conductive layer 4 include being locally filled in hole 3 and
Embolism portion 41 with gap 42, gap 42 are located at the top in embolism portion 41, and gap 42 is for elongate and along the length side of hole 3
To extension, the lower end 43 in gap 42 is located at openend 31, and the upper end 44 in gap 42 is located at the table beyond dielectric layer 2
At the position of face；
8) using chemical mechanical milling tech removal gap 42, certain media layer 2 and the first conductive layer of part 4, until energy
Enough expose the conductive plug 5 electrically isolated of flush.
As shown in figure 9, a kind of semiconductor devices with embolism is present embodiments provided, including：
Semi-conductive substrate 1；
One dielectric layer 2, is formed at the surface of substrate 1, and dielectric layer 2 has the hole 3 and first for being connected to 1 surface of substrate
Flat surface 23, the opening of hole 3 are exposed to the first flat surface 23；And conductive plug 5, it is filled in hole 3, conductive plug 5 is
The homogeneous solid being made of the first conductive layer 4, conductive plug 5 have the second flat surface 51, and the second flat surface 51 is no recess
And the opening of hole is filled up, the second flat surface 51 and the first flat surface 23 are in same plane.
In some embodiments, it is provided with barrier layer 6 between 3 surface of hole and conductive plug 5.
In some embodiments, it is conductive that second is provided between 3 lower surface of the barrier layer 6 of 3 bottom of hole and hole
Layer 7.
In some embodiments, barrier layer 6 has ring edge, be revealed in the opening of hole 3 and the first flat surface 23 with
Between second flat surface 51, the second flat surface 51 is formed in via ring edge and the first flat surface 23 in a continuous surface.I.e. first
Flat surface 23, the second flat surface 51 and ring edge three are in the same plane.
In some embodiments, sputtering technology or grey chemical industry in situ can be used in the technique of the bore at enlarged openings end 31
Skill makes reaming inclined-plane form the first chamfering (as shown in Figure 3), and then enlarged openings by bombardment compared with the upper surface of dielectric layer 2
The bore at end 31, the material convenient for the first conductive layer 4 of subsequent deposition are easy to enter inside hole 3, make the conductive plugs to be formed
The densification of 5 inner homogeneous is filled in, and due to the dimension enlargement parallel to substrate surface direction at open end 31, even if first is conductive
The material of layer 4 is accumulated close to the sidewall surfaces of openend 31, openend 31 will not premature generation closed-ended question, from
And it can inhibit to generate larger gap in formed the first conductive layer 4.So that the first conductive layer dense uniform formed,
Electric performance stablity.
In a preferred embodiment, the angular range of the first chamfering is preferably 45 ° between 30 °~70 °, this angle
The gradient of first chamfering of degree is moderate, the material deposition velocity of the first conductive layer 4 when can improve deposition, and will not be because of stream
Dynamic excessive velocities cause the first conductive layer 4 of opening to be accumulated, and are closed opening too early.
In another preferred embodiment, the first chamfering can be fillet, deposit the first conductive layer 4 more smooth.
In some embodiments, 2 surface of dielectric layer around openend 31 forms the second chamfering (not shown), the
Two chamfer angles are not more than the angle of the first chamfering, make 4 more smooth filling hole of the first conductive layer.
It should be noted that when 31 too small openings of openend of the hole 3 on substrate 1, first in openend 31 falls
Angle it is circumferential by sputtering technology or cineration technics in situ, bombard 2 surface of dielectric layer of the first chamfering dimension, formed and the
Second chamfering of one chamfering connection, preferred second chamfer angle is equal with the first chamfer angle, so as to form smooth guiding
Structure further expands the bore of the openend 31 of hole 3, the material deposition speed of the first conductive layer 4 when improving deposition
Degree prevents material stacking openend 31 to be closed too early.
In some embodiments, the material on barrier layer 6 is selected from tungsten nitride, one or more groups in titanium or titanium nitride
It closes.Barrier layer 6 can also play and for stopping that the material of the first conductive layer 4 is spread into substrate 1 and dielectric layer 2
The purpose that one conductive layer 4 more preferably engages prevents the generation removed.
In a preferred embodiment, the material on barrier layer 6 is selected from titanium, and the material of the first conductive layer 4 is selected from tungsten,
Zygosity at this time between the first conductive layer 4 and barrier layer 6 is good.
It should be noted that barrier layer 6 is by chemical vapor deposition technique, gas phase physical deposition process or atomic layer deposition
Product be formed in hole 3 surface and on the surface of dielectric layer 2.
In some embodiments, the second conductive layer 7, barrier layer 6 are formed in the bottom of hole 3 by deposition and annealing process
It is formed in 7 surface of the second conductive layer；The material of second conductive layer 7 is selected from titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and silicon
Change one of nickel.
In some embodiments, the first conductive layer 4 is formed in 2 surface of dielectric layer and filling by chemical vapor deposition method
In hole 3.
In some embodiments, the material of the first conductive layer 4 is selected from tungsten.
In some embodiments, the material of dielectric layer 2 is selected from oxide, is chosen in particular from silica, silicon nitride or nitrogen
One or more combinations in silica.
In some embodiments, dielectric layer 2 is formed in 1 surface of substrate by depositing operation；Hole 3 passes through etching technics shape
Into in dielectric layer 2.Specifically, the formation process of dielectric layer 2 is chemical vapor deposition method or physical gas-phase deposition；Hole
The formation process in hole 3 is anisotropic dry etch process.
In some embodiments, substrate 1 includes semiconductor base, is formed in semiconductor substrate surface or semiconductor base
Semiconductor devices, for the conductive structure that is electrically connected semiconductor devices and for being electrically isolated semiconductor devices and conductive knot
The insulating layer of structure.Semiconductor base includes silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium on insulator
Substrate, glass substrate.Semiconductor devices includes transistor, and the first conductive layer 4 is electrically connected with transistor, realizes read/write function.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to scope.
Claims (9)
1. a kind of embolism forming method, which is characterized in that including：
Semiconductor substrate is provided, dielectric layer is formed in the substrate surface, is formed on the dielectric layer and is connected to the substrate
The hole on surface, the dielectric layer include a retaining layer portion and a sacrificial layer portion；
Expand the bore at the openend of described hole, to reduce depth-to-width ratio of the described hole at the openend, the hole
Reaming inclined-plane is formed at the openend in hole, the depth on the reaming inclined-plane is less than the thickness in the sacrificial layer portion；
The first conductive layer is formed in the upper surface of the dielectric layer, and first conductive layer includes embolism portion, is filled in institute
It states in hole, there is gap in the embolism portion, the gap extends along described hole length direction, the lower end in the gap
No more than the thickness definition scope in the sacrificial layer portion, the upper end in the gap is no more than the formation table of first conductive layer
Face；
The sacrificial layer portion is removed, to remove the gap and part first conductive layer simultaneously, is put down until exposing surface
Neat conductive plug is in the thickness definition scope in the retaining layer portion.
2. embolism forming method as described in claim 1, which is characterized in that the technique for expanding the bore at the openend is
Using sputtering technology or cineration technics in situ, the reaming inclined-plane is made to form first compared with the upper surface of the dielectric layer and is fallen
Angle, and then expand the bore of the openend.
3. embolism forming method as described in claim 1, which is characterized in that further include：Formed first conductive layer it
Before, deposition barrier layer in the upper surface of the dielectric layer and the bottom and side wall of described hole, for first conductive layer and
Deposition of the embolism portion on the barrier layer is formed.
4. embolism forming method as claimed in claim 3, which is characterized in that the material on the barrier layer selected from tungsten nitride,
One of titanium and titanium nitride.
5. embolism forming method as claimed in claim 3, which is characterized in that further include：Before the barrier layer is formed, lead to
It crosses deposition and annealing process and forms the second conductive layer in the substrate surface that described hole bottom-exposed goes out, for the stop
Layer is formed；The material of second conductive layer selected from titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide wherein it
One.
6. embolism forming method as claimed in claim 5, which is characterized in that further include：Formed second conductive layer it
After carry out wet clean process, removal is attached to second conductive layer, described hole madial wall and the surface of the openend
Impurity.
7. embolism forming method as described in claim 1, which is characterized in that first conductive layer passes through chemical vapor deposition
Technique is formed in the dielectric layer surface and is filled in described hole.
8. embolism forming method as described in claim 1, which is characterized in that the material of the dielectric layer is selected from oxide；
The material of first conductive layer is selected from one of tungsten, copper, aluminium or polysilicon.
9. such as claim 1 to 8 any one of them embolism forming method, which is characterized in that utilize chemical mechanical milling tech
Remove first conductive layer on the dielectric layer surface and the sacrificial layer portion.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810291816.2A CN108511416B (en) | 2017-07-31 | 2017-07-31 | Semiconductor devices with embolism |
| CN201710640184.1A CN107452676B (en) | 2017-07-31 | 2017-07-31 | A kind of embolism forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710640184.1A CN107452676B (en) | 2017-07-31 | 2017-07-31 | A kind of embolism forming method |
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| CN201810291816.2A Division CN108511416B (en) | 2017-07-31 | 2017-07-31 | Semiconductor devices with embolism |
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| CN107452676B true CN107452676B (en) | 2018-05-18 |
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| CN201810291816.2A Active CN108511416B (en) | 2017-07-31 | 2017-07-31 | Semiconductor devices with embolism |
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| CN110299319A (en) * | 2018-03-21 | 2019-10-01 | 联华电子股份有限公司 | The intraconnections manufacturing method of semiconductor element |
| CN113539944B (en) * | 2020-04-16 | 2023-09-12 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and semiconductor device |
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| KR100664870B1 (en) * | 2005-07-11 | 2007-01-03 | 동부일렉트로닉스 주식회사 | Low-regisistivity copper metal line and method for forming the same |
| CN101635273A (en) * | 2009-06-12 | 2010-01-27 | 上海宏力半导体制造有限公司 | Preparation method of tungsten plug |
| CN102054758A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming tungsten plug |
| CN103839874B (en) * | 2012-11-21 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnect structure and preparation method thereof |
| CN104425710B (en) * | 2013-08-20 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
| CN104752334B (en) * | 2013-12-31 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of contact plunger |
| CN105990216A (en) * | 2015-01-29 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
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| CN108511416B (en) | 2019-08-30 |
| CN108511416A (en) | 2018-09-07 |
| CN107452676A (en) | 2017-12-08 |
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Effective date of registration: 20180928 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |