CN108511416B - Semiconductor devices with embolism - Google Patents
Semiconductor devices with embolism Download PDFInfo
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- CN108511416B CN108511416B CN201810291816.2A CN201810291816A CN108511416B CN 108511416 B CN108511416 B CN 108511416B CN 201810291816 A CN201810291816 A CN 201810291816A CN 108511416 B CN108511416 B CN 108511416B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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Abstract
The present invention relates to a kind of semiconductor devices with embolism, including semiconductor substrate, form dielectric layer in substrate surface, dielectric layer has the hole and the first flat surface for being connected to substrate surface, and the opening of hole is exposed to the first flat surface；Conductive plug is filled in hole, and conductive plug is the homogeneous solid being made of the first conductive layer, and conductive plug has the second flat surface, and the second flat surface is without the opening for being recessed and filling up hole, and the second flat surface and the first flat surface are in same plane；Barrier layer is arranged between hole surface and conductive plug；Second conductive layer is set to substrate between the surface of hole bottom and the barrier layer of hole bottom；Barrier layer has ring edge, is revealed in the opening of hole and between the first flat surface and the second flat surface, and the second flat surface is formed in a continuous surface via ring edge and the first flat surface.The conductive plug of semiconductor devices of the present invention has that tight, resistance is low, high reliability.
Description
The application is application number 201710640184.1, July 31 2017 applying date, a kind of denomination of invention " embolism shape
At method and with the semiconductor devices of the embolism " patent application divisional application.
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices with embolism.
Background technique
Currently, generalling use the mode for forming embolism structure between the two metal layers in semiconductor storage device assembly
Realize the electrical connection between two metal layers.Since tungsten has good stepcoverage and gap filling performance, often adopt
Embolism is formed with the mode of chemical vapor deposition tungsten.
The formation quality of embolism influences the performance of device very big, if embolism forms second-rate, can make interconnection electricity
Resistance increases, and influences the performance of device.However, being used to form the depth of the hole opening of embolism with the continuous diminution of process node
Width is correspondinglyd increase than also, therefore is easy to cause and is difficult to be easy even into hole bottom by the tungsten of chemical vapor deposition
The sidewall surfaces of hole opening form accumulation, lead to deposit to the tungsten in hole when not being filled up completely full hole just in opening
Closure too early, and then make to form gap inside the embolism to be formed, so as to cause being formed by, embolism performance is bad.Further,
When removing extra tungsten metal subsequently through chemical mechanical grinding or etching technics, the cavity or gap in embolism can be made
Outside being exposed to, there are void defects in the embolism resulted in, influence the reliability of the subsequent connection of device.In the prior art,
The production in cavity or gap is reduced frequently with temperature, the adjusting parameters such as pressure and air-flow are reduced in chemical vapor deposition processes
It is raw, but the tungsten plug too high in resistance of generation, the conducting being unfavorable between metal layer are deposited under such circumstances.
Disclosed above- mentioned information are only used for reinforcing the understanding to background of the invention in the background technology, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
Summary of the invention
In view of this, the embodiment of the present application is desirable to provide a kind of semiconductor devices with embolism, it is existing at least to solve
The problem of technology.
The technical solution of the embodiment of the present application is achieved in that one embodiment according to the application, provides a kind of tool
There is the semiconductor devices of embolism, comprising:
Substrate；
Dielectric layer, is formed in the surface of the substrate, the dielectric layer have be connected to the hole of the substrate surface with
And first flat surface, the opening of described hole are exposed to first flat surface；
Conductive plug is filled in described hole, and the conductive plug is the homogeneous solid being made of the first conductive layer,
The conductive plug has the second flat surface, and second flat surface is described without the opening for being recessed and filling up described hole
Second flat surface and first flat surface are in same plane；
Barrier layer is arranged between described hole surface and the conductive plug, and the barrier layer is for stopping described the
The material of one conductive layer is spread to the substrate and the dielectric layer；And
Second conductive layer is set to surface of the substrate in described hole bottom and the resistance in described hole bottom
Between barrier；
Wherein, the barrier layer has ring edge, is revealed in the opening of described hole and in first flat surface
Between second flat surface, second flat surface is formed in a continuous table via the ring edge and first flat surface
In face.
In some embodiments, the dielectric layer is formed in by chemical vapor deposition process or physical gas-phase deposition
The substrate surface.
In some embodiments, described hole is formed in the dielectric layer by anisotropic dry etch process.
In some embodiments, the material of first conductive layer includes one of tungsten, copper, aluminium and polysilicon or a variety of
Combination.
In some embodiments, the barrier layer passes through chemical vapor deposition process, physical gas-phase deposition or atom
Layer depositing operation is formed in described hole surface.
In some embodiments, the material on the barrier layer includes tungsten nitride, one of titanium and titanium nitride or a variety of groups
It closes.
In some embodiments, the material of second conductive layer include titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and
One of nickle silicide or multiple combinations.
In some embodiments, the material of the dielectric layer include one of silica, silicon nitride and silicon oxynitride or
Multiple combinations.
The present invention due to using the technology described above, has the advantage that the 1, present invention due to changing hole opening
Caliber size and shape at end, reduce the depth-to-width ratio of hole, so that the material of the first conductive layer of subsequent deposition is easy
In entering inside hole, make even compact inside the conductive plug to be formed, and due to being parallel to substrate table at open end
The dimension enlargement in face direction is open so that the material of the first conductive layer is not susceptible to accumulate in the sidewall surfaces close to open end
End will not premature generation closed-ended question, generate biggish gap in the first conductive layer so as to inhibit to be formed by, make
The first conductive layer dense uniform, electric performance stablity must be formed by.2, since the open end of hole is extended, in open end
The time for forming packing phenomenon extends, and the material for being filled into the first conductive layer in hole is more, so that being deposited in opening
Position of the material of first conductive layer at end when being closed moves up, i.e., moves on to open end upper end on the position that gap is formed,
Part exceeds dielectric layer surface, therefore can remove less dielectric layer and first in subsequent chemical mechanical planarization process and lead
Electric layer is to form the conductive plug of flush, save cost and improve production efficiency.3, due to conductive plugs of the invention
Gap is not contained in plug, therefore is able to maintain the low resistance of the first conductive layer, reduce contact resistance and increases read/write speed, together
When reduce chemical vapor deposition temperature, pressure and flow.4, the conductive plug that the method for the present invention is formed has tight, resistance
Low, high reliability.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings depict only according to the present invention
Disclosed some embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the flow chart of embolism forming method of the invention；
Fig. 2 is the structural schematic diagram that dielectric layer is formed on the substrate of the invention；
Fig. 3 is the structural schematic diagram of the chamfering of hole open end of the invention；
Fig. 4 is the structural schematic diagram of the first conductive layer deposition of the invention；
Fig. 5 is the structural schematic diagram of conductive plug of the invention；
Fig. 6 is the deposition process schematic diagram of the second conductive layer of the invention；
Fig. 7 is the structural schematic diagram of the second conductive layer deposition of the invention；
Fig. 8 is the structural schematic diagram of barrier deposition of the invention；
Fig. 9 is the structural schematic diagram of semiconductor devices of the invention.
Appended drawing reference:
1- substrate；2- dielectric layer；21- retaining layer portion；22- sacrificial layer portion；The first flat surface of 23-；3- hole；31- opening
End；The first conductive layer of 4-；41- embolism portion；The gap 42-；The lower end in the gap 43-；The upper end in the gap 44-；5- conductive plug；
The second flat surface of 51-；The barrier layer 6-；The second conductive layer of 7-.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be modified by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", " go up ", " under ", " preceding ", " afterwards ", " left side ", " right side ", " heavily fortified point, and directly ", " level ", " top ", " bottom ", " is interior ", " outside ", "
Clockwise ", " counterclockwise " wait the orientation or positional relationship of instructions to be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second " are only
For descriptive purposes, it is not understood to indicate or imply relative importance or implicitly indicates the number of indicated technical characteristic
Amount." first " is defined as a result, the feature of " second " can explicitly or implicitly include one or more spy
Sign.In the description of the present invention, " multiple " are meant that two or more, unless otherwise specifically defined.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected: can
To be mechanical connection, it is also possible to be electrically connected or can mutually communicate；It can be directly connected, it can also be by between intermediary
It connects connected, can be the connection inside two elements or the interaction relationship of two elements.For the ordinary skill of this field
For personnel, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature its " upper " or it " under "
It may include that the first and second features directly contact, also may include that the first and second features are not direct contacts but pass through it
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " top " and " above " include first spy
Sign is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and it is " following " including fisrt feature right above second feature and oblique upper, or be merely representative of
First feature horizontal height is less than second feature.
Following disclosure provides many different embodiments or example is used to realize different structure of the invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.In addition, the present invention provides various specific techniques and material example, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
As shown in Figure 1, a kind of embolism forming method is present embodiments provided, specifically includes the following steps:
Semiconductor substrate 1 is provided, dielectric layer 2 is formed on 1 surface of semiconductor substrate, forms connection substrate 1 on dielectric layer 2
The hole 3 (as shown in Figure 2) of upper surface, dielectric layer 2 include retaining layer portion 21 and sacrificial layer portion 22；Wherein, retaining layer portion 21 is
2 lower part of dielectric layer, sacrificial layer portion 22 are 2 top of dielectric layer, and retaining layer portion 21 and sacrificial layer portion 22 collectively form dielectric layer 2, and
The two is 2 ontology of dielectric layer and non-physical visible layer, for the ease of difference description to need 2 top of dielectric layer to be removed portion
Divide the sacrificial layer portion 22 that is named as, and it is retaining layer portion 21 that dielectric layer 2, which is not removed part names,.
Expand the bore at the open end 31 of hole 3, increases opening size, and the caliber size inside hole 3 is constant, with
Reduce depth-to-width ratio of the hole 3 at open end 31, forms reaming inclined-plane (as shown in Figure 3) at the open end 31 of hole 3, reaming is oblique
The depth in face is less than the thickness in sacrificial layer portion 22；
As shown in figure 4, forming the first conductive layer 4 in the upper surface of dielectric layer 2, and the first conductive layer 4 includes embolism portion
41, embolism portion 41 is filled in hole 3, has gap 42 in embolism portion 41, and gap 42 extends along 3 length direction of hole, gap
42 lower end 43 is no more than the thickness definition range in sacrificial layer portion 22, and the upper end 44 in gap 42 is no more than the first conductive layer 4
Formation surface；
As shown in figure 5, sacrificial layer portion 22 is removed, to remove gap 42 and the first conductive layer of part 4 simultaneously, until exposing
Thickness definition range of the conductive plug 5 of flush in retaining layer portion 21.
In some embodiments, sputtering technology or grey chemical industry in situ can be used in the technique of the bore at enlarged openings end 31
Skill makes reaming inclined-plane form the first chamfering (as shown in Figure 3) by bombardment relative to the upper surface of dielectric layer 2, and then enlarged openings
The bore at end 31, the material convenient for the first conductive layer 4 of subsequent deposition are easy to enter inside hole 3, make the conductive plugs to be formed
5 inside even compacts, and the dimension enlargement due to being parallel to substrate surface direction at open end 31 are filled in, even if first is conductive
The material of layer 4 is accumulated close to the sidewall surfaces of open end 31, open end 31 will not premature generation closed-ended question, from
And it is able to suppress to be formed by the first conductive layer 4 and generates biggish gap.So that be formed by the first conductive layer dense uniform,
Electric performance stablity.
In a preferred embodiment, the expansion of open end 31 is realized using argon sputtering technology.It should be noted that opening
The change method at mouth end 31 is not limited to mode mentioned above, any way in the prior art can be used, as long as can be realized
The change of the shape and size of open end 31.
In a preferred embodiment, the angular range of the first chamfering is between 30 °~70 °, and preferably 45 °, this angle
The gradient of first chamfering of degree is moderate, the material deposition velocity of the first conductive layer 4 when can be improved deposition, and will not be because of stream
Dynamic excessive velocities cause the first conductive layer 4 of opening to be accumulated, too early closure opening.
In another preferred embodiment, the first chamfering can be fillet, keep the first conductive layer 4 deposition more smooth.
In some embodiments, 2 surface of dielectric layer around open end 31 forms the second chamfering (not shown), the
Two chamfer angles are not more than the angle of the first chamfering, make the more smooth filling hole of the first conductive layer 4.
It should be noted that first in open end 31 falls when 31 too small openings of open end of the hole 3 on substrate 1
The circumferential direction at angle bombards 2 surface of dielectric layer of the first chamfering dimension by sputtering technology or cineration technics in situ, is formed and the
Second chamfering of one chamfering connection, preferred second chamfer angle is equal with the first chamfer angle, to constitute smooth guiding
Structure further expands the bore of the open end 31 of hole 3, and the material of the first conductive layer 4 deposits speed when improving deposition
Degree prevents material stacking open end 31 to be closed too early.
In some embodiments, before forming the first conductive layer 4, barrier layer 6 is deposited in the upper surface and hole of dielectric layer 2
The bottom and side wall in hole 3, so that the deposition of the first conductive layer 4 and embolism portion 41 on barrier layer 6 forms (as shown in Figure 7).It needs
It is noted that the material on barrier layer 6 is selected from tungsten nitride, one of titanium or titanium nitride or multiple combinations.Barrier layer 6 is used for
Stop the material of the first conductive layer 4 to spread into substrate 1 and dielectric layer 2, while can also play and more preferably be connect with the first conductive layer 4
The purpose of conjunction prevents the generation of removing.
In a preferred embodiment, the material of the first conductive layer 4 is selected from tungsten, at this time 4 He of the first conductive layer
Zygosity between barrier layer 6 is good.It should be noted that barrier layer 6 is by chemical vapor deposition technique, gas phase physical deposition
Technique or atomic layer deposition are formed on the surface of hole 3 and the surface of dielectric layer 2.
In some embodiments, before forming barrier layer 6, the forming material of deposit second conductive layer 7 is in dielectric layer 2
The bottom and side wall (as shown in Figure 6) of upper surface and hole 3, and gone out by deposition and annealing process in 3 bottom-exposed of hole
1 surface of substrate forms the second conductive layer 7 (as shown in Figure 7), so that barrier layer forms 6 (as shown in Figure 8)；Second conductive layer 7
Material is selected from one of titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide.
Wherein, the forming process of the second conductive layer 7 are as follows: after the caliber size of the open end of hole 3 31 changes, in hole
Co, CoSi and Co are deposited to the inner wall of hole 3 at 3 open end 312The combination material of Si carries out annealing process, group after deposition
It is CoSi that material, which is closed, by reacting a layer component of the bottom that formation is deposited on hole 32The second conductive layer 7.
In some embodiments, wet clean process is carried out after forming the second conductive layer 7, removal is attached to second and leads
The surface impurity of electric layer 7, hole 3 inner sidewall and open end 31, keeps the surface of above-mentioned three smoother, and pattern is more excellent, avoids
Influence the performance of the conductive plug eventually formed.Wherein, the cleaning liquid level acidic cleaning solution that wet clean process is used.
In some embodiments, the first conductive layer 4 is formed in 2 surface of dielectric layer and filling by chemical vapor deposition process
In hole 3.The material of first conductive layer 4 is selected from one of tungsten, copper, aluminium or polysilicon.
In some embodiments, the first conductive layer 4 and sacrificial on chemical mechanical milling tech removal 2 surface of dielectric layer is utilized
Domestic animal layer portion 22.
In some embodiments, the material of dielectric layer 2 is selected from oxide, is chosen in particular from silica, silicon nitride or nitrogen
One of silica or multiple combinations.
In some embodiments, dielectric layer 2 is formed in 1 surface of substrate by depositing operation；Hole 3 passes through etching technics shape
At in dielectric layer 2.Specifically, the formation process of dielectric layer 2 is chemical vapor deposition process or physical gas-phase deposition；Hole
The formation process in hole 3 is anisotropic dry etch process.
In some embodiments, substrate 1 includes semiconductor base, is formed in semiconductor substrate surface or semiconductor base
Semiconductor devices, the conductive structure for being electrically connected semiconductor devices and for being electrically isolated semiconductor devices and conductive knot
The insulating layer of structure.Semiconductor base includes silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium on insulator
Substrate, glass substrate.Semiconductor devices includes transistor, and the first conductive layer 4 is electrically connected with transistor, realizes read/write function.
Illustrate the embolism forming method in the present invention below by a preferred embodiment.
Embodiment
A kind of embolism forming method, comprising the following steps:
1) semiconductor substrate 1 is provided, dielectric layer 2 is formed by chemical vapor deposition process on 1 surface of substrate, in dielectric layer
The hole 3 for exposing 1 upper surface of substrate is formed on 2 by anisotropic dry etch process；
2) bore at the open end 31 of hole 3, opposite reduction hole are expanded using sputtering technology or cineration technics in situ
The depth-to-width ratio in hole 3；
3) Co, CoSi and Co are deposited to the inside of hole 3 at the open end of hole 3 312The combination material of Si；
4) annealing process is carried out after depositing, combination material forms a layer component of the bottom for being deposited on hole 3 by reacting
For CoSi2The second conductive layer 7；
5) wet clean process is carried out after forming the second conductive layer 7, removal is attached to the second conductive layer 7, in hole 3
The surface impurity of side wall and open end 31；
6) barrier layer 6 is deposited in the upper surface of the side wall of hole 3 and the second conductive layer 7；
7) form the first conductive layer 4 in the upper surface of dielectric layer 2, the first conductive layer 4 include be locally filled in hole 3 and
Embolism portion 41 with gap 42, gap 42 are located at the top in embolism portion 41, and gap 42 is for elongate and along the length side of hole 3
To extension, the lower end 43 in gap 42 is located at open end 31, and the upper end 44 in gap 42 is located at the table beyond dielectric layer 2
At the position of face；
8) using chemical mechanical milling tech removal gap 42, certain media layer 2 and the first conductive layer of part 4, until energy
Enough expose the conductive plug 5 of flush electrically isolated.
As shown in figure 9, present embodiments providing a kind of semiconductor devices with embolism, comprising:
Semi-conductive substrate 1；
One dielectric layer 2, is formed in the surface of substrate 1, and dielectric layer 2 has the hole 3 and first for being connected to 1 surface of substrate
Flat surface 23, the opening of hole 3 are exposed to the first flat surface 23；And conductive plug 5, it is filled in hole 3, conductive plug 5 is
The homogeneous solid being made of the first conductive layer 4, conductive plug 5 have the second flat surface 51, and the second flat surface 51 is no recess
And the opening of hole is filled up, the second flat surface 51 and the first flat surface 23 are in same plane.
In some embodiments, barrier layer 6 is provided between 3 surface of hole and conductive plug 5.
In some embodiments, the second conduction is provided between 3 bottom surface of barrier layer 6 and hole of 3 bottom of hole
Layer 7.
In some embodiments, barrier layer 6 has ring edge, be revealed in the opening of hole 3 and the first flat surface 23 with
Between second flat surface 51, the second flat surface 51 is formed in a continuous surface via ring edge and the first flat surface 23.I.e. first
Flat surface 23, the second flat surface 51 and ring edge three are in the same plane.
In some embodiments, sputtering technology or grey chemical industry in situ can be used in the technique of the bore at enlarged openings end 31
Skill makes reaming inclined-plane form the first chamfering (as shown in Figure 3) by bombardment relative to the upper surface of dielectric layer 2, and then enlarged openings
The bore at end 31, the material convenient for the first conductive layer 4 of subsequent deposition are easy to enter inside hole 3, make the conductive plugs to be formed
5 inside even compacts, and the dimension enlargement due to being parallel to substrate surface direction at open end 31 are filled in, even if first is conductive
The material of layer 4 is accumulated close to the sidewall surfaces of open end 31, open end 31 will not premature generation closed-ended question, from
And it is able to suppress to be formed by the first conductive layer 4 and generates biggish gap.So that be formed by the first conductive layer dense uniform,
Electric performance stablity.
In a preferred embodiment, the angular range of the first chamfering is between 30 °~70 °, and preferably 45 °, this angle
The gradient of first chamfering of degree is moderate, the material deposition velocity of the first conductive layer 4 when can be improved deposition, and will not be because of stream
Dynamic excessive velocities cause the first conductive layer 4 of opening to be accumulated, too early closure opening.
In another preferred embodiment, the first chamfering can be fillet, keep the first conductive layer 4 deposition more smooth.
In some embodiments, 2 surface of dielectric layer around open end 31 forms the second chamfering (not shown), the
Two chamfer angles are not more than the angle of the first chamfering, make the more smooth filling hole of the first conductive layer 4.
It should be noted that first in open end 31 falls when 31 too small openings of open end of the hole 3 on substrate 1
The circumferential direction at angle bombards 2 surface of dielectric layer of the first chamfering dimension by sputtering technology or cineration technics in situ, is formed and the
Second chamfering of one chamfering connection, preferred second chamfer angle is equal with the first chamfer angle, to constitute smooth guiding
Structure further expands the bore of the open end 31 of hole 3, and the material of the first conductive layer 4 deposits speed when improving deposition
Degree prevents material stacking open end 31 to be closed too early.
In some embodiments, the material on barrier layer 6 is selected from tungsten nitride, one of titanium or titanium nitride or a variety of groups
It closes.Barrier layer 6 can also play and for stopping the material of the first conductive layer 4 to spread into substrate 1 and dielectric layer 2
The purpose that one conductive layer 4 more preferably engages prevents the generation of removing.
In a preferred embodiment, the material on barrier layer 6 is selected from titanium, and the material of the first conductive layer 4 is selected from tungsten,
Zygosity at this time between the first conductive layer 4 and barrier layer 6 is good.
It should be noted that barrier layer 6 is by chemical vapor deposition technique, gas phase physical deposition process or atomic layer deposition
Product be formed in hole 3 surface and on the surface of dielectric layer 2.
In some embodiments, the second conductive layer 7, barrier layer 6 are formed in the bottom of hole 3 with annealing process by depositing
It is formed in 7 surface of the second conductive layer；The material of second conductive layer 7 is selected from titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and silicon
Change one of nickel.
In some embodiments, the first conductive layer 4 is formed in 2 surface of dielectric layer and filling by chemical vapor deposition process
In hole 3.
In some embodiments, the material of the first conductive layer 4 is selected from tungsten.
In some embodiments, the material of dielectric layer 2 is selected from oxide, is chosen in particular from silica, silicon nitride or nitrogen
One of silica or multiple combinations.
In some embodiments, dielectric layer 2 is formed in 1 surface of substrate by depositing operation；Hole 3 passes through etching technics shape
At in dielectric layer 2.Specifically, the formation process of dielectric layer 2 is chemical vapor deposition process or physical gas-phase deposition；Hole
The formation process in hole 3 is anisotropic dry etch process.
In some embodiments, substrate 1 includes semiconductor base, is formed in semiconductor substrate surface or semiconductor base
Semiconductor devices, the conductive structure for being electrically connected semiconductor devices and for being electrically isolated semiconductor devices and conductive knot
The insulating layer of structure.Semiconductor base includes silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium on insulator
Substrate, glass substrate.Semiconductor devices includes transistor, and the first conductive layer 4 is electrically connected with transistor, realizes read/write function.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (8)
1. a kind of semiconductor devices with embolism characterized by comprising
Substrate；
Dielectric layer, is formed in the surface of the substrate, and the dielectric layer has the hole for being connected to the substrate surface, given an account of
Retaining layer portion is formed at the lower part of matter layer, and sacrificial layer portion is formed at the top of the dielectric layer, and the opening of described hole forms reaming
Inclined-plane；
First conductive layer is formed in the surface in the sacrificial layer portion, and first conductive layer, which has, to be filled in described hole
Embolism portion, the embolism portion have gap, and the lower end in the gap is no more than the thickness definition range in sacrificial layer portion, the sky
The upper end of gap is no more than the formation surface of first conductive layer.
2. as described in claim 1 with the semiconductor devices of embolism, which is characterized in that the dielectric layer passes through chemical gaseous phase
Depositing operation or physical gas-phase deposition are formed in the substrate surface.
3. as described in claim 1 with the semiconductor devices of embolism, which is characterized in that described hole passes through anisotropic
Dry etch process is formed in the dielectric layer.
4. as described in claim 1 with the semiconductor devices of embolism, which is characterized in that the material of first conductive layer selects
From one of in tungsten, copper, aluminium and polysilicon.
5. as described in claim 1 with the semiconductor devices of embolism, which is characterized in that further include:
Barrier layer is arranged between described hole surface and the embolism portion, and the barrier layer is for stopping first conduction
The material of layer is spread to the substrate and the dielectric layer；By chemical vapor deposition process, physical vapor is heavy on the barrier layer
Product technique or atom layer deposition process are formed in described hole surface；And
Second conductive layer is set to surface of the substrate in described hole bottom and the barrier layer in described hole bottom
Between.
6. as claimed in claim 5 with the semiconductor devices of embolism, which is characterized in that the material on the barrier layer is selected from
One of tungsten nitride, titanium and titanium nitride or multiple combinations.
7. as claimed in claim 5 with the semiconductor devices of embolism, which is characterized in that the material of second conductive layer selects
From one of in titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide.
8. as described in claim 1 with the semiconductor devices of embolism, which is characterized in that the material of the dielectric layer is selected from
One of silica, silicon nitride and silicon oxynitride or multiple combinations.
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| CN201810291816.2A CN108511416B (en) | 2017-07-31 | 2017-07-31 | Semiconductor devices with embolism |
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| CN201710640184.1A CN107452676B (en) | 2017-07-31 | 2017-07-31 | A kind of embolism forming method |
| CN201810291816.2A CN108511416B (en) | 2017-07-31 | 2017-07-31 | Semiconductor devices with embolism |
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| CN113539944B (en) * | 2020-04-16 | 2023-09-12 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and semiconductor device |
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| CN101635273A (en) * | 2009-06-12 | 2010-01-27 | 上海宏力半导体制造有限公司 | Preparation method of tungsten plug |
| CN102054758A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming tungsten plug |
| CN104425710A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
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| KR100664870B1 (en) * | 2005-07-11 | 2007-01-03 | 동부일렉트로닉스 주식회사 | Low-regisistivity copper metal line and method for forming the same |
| CN103839874B (en) * | 2012-11-21 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnect structure and preparation method thereof |
| CN104752334B (en) * | 2013-12-31 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of contact plunger |
| CN105990216A (en) * | 2015-01-29 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101635273A (en) * | 2009-06-12 | 2010-01-27 | 上海宏力半导体制造有限公司 | Preparation method of tungsten plug |
| CN102054758A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming tungsten plug |
| CN104425710A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
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| CN107452676A (en) | 2017-12-08 |
| CN108511416A (en) | 2018-09-07 |
| CN107452676B (en) | 2018-05-18 |
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