CN107452629B - Power semiconductor device and method of manufacturing the same - Google Patents
Power semiconductor device and method of manufacturing the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The application discloses a power semiconductor device and a method of manufacturing the same. The method comprises the following steps: forming an epitaxial layer on a first surface of a semiconductor substrate, wherein the semiconductor substrate and the epitaxial layer are of a first doping type and respectively have a first doping concentration and a second doping concentration; forming a gate stack on the epitaxial layer, wherein the gate stack comprises a gate dielectric layer and a gate conductor, and the gate dielectric layer is clamped between the gate conductor and the epitaxial layer; forming a body region in the epitaxial layer, wherein the body region is of a second doping type; forming a first doped region in the body region, wherein the first doped region is of a first doping type; forming a first contact to the first doped region; doping the semiconductor substrate from the second surface of the semiconductor substrate to increase the doping concentration; and forming a second contact on the second surface of the semiconductor substrate, wherein the first doping concentration is 5 to 100 times the second doping concentration. The concentration difference between the semiconductor substrate and the epitaxial layer is reduced in the technical process of the method, so that the thickness of the transition region is reduced, and the product yield can be improved.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device and a method of manufacturing the same.
Background
Power semiconductor devices are widely used in electronic devices, for example, as amplifying transistors in power amplifier circuits or as switching transistors in power supply circuits. The power semiconductor device includes a bipolar transistor, a metal oxide semiconductor transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), and the like.
MOSFET devices have evolved into more than one generation of products since the 60 s of the last century. Conventional MOSFET devices include an epitaxial layer grown on a semiconductor substrate, source and drain regions formed in the epitaxial layer, and a gate stack formed over the epitaxial layer. The thickness and concentration of this epitaxial layer determine the withstand voltage and on-resistance Rds (on) of the MOSFET device. The thicker the epitaxial layer thickness, the higher the withstand voltage of the MOSFET device and the larger the on-resistance.
In MOSFET devices, conventional MOSFET devices select semiconductor substrates having very low resistivity in order to reduce the effect of the semiconductor substrate on the on-resistance. For example, the resistivity of the epitaxial layer may be 65-75 ohm cm, for example, and the resistivity of the semiconductor substrate may be less than 0.02 ohm cm. The epitaxial layers are of the same doping type as the semiconductor substrate and the resistivity is largely dependent on the respective doping concentrations. The doping level of the semiconductor substrate is much greater than the doping level of the epitaxial layer. However, between the semiconductor substrate of high doping concentration and the epitaxial layer of low doping concentration, a transition region is formed due to the difference in doping concentration between the two. Thus, the high temperature processes experienced during the growth of the epitaxial layer on the semiconductor substrate and during the subsequent fabrication of the MOSFET device result in the continued diffusion of the dopant impurities of the semiconductor substrate into the epitaxial layer, forming a transition region between the semiconductor substrate and the epitaxial layer. The transition region has little effect on the withstand voltage, but has a great influence on the on-resistance Rds (on) of the MOSFET device, so that the on-resistance Rds (on) of the MOSFET device increases. In a conventional MOSFET, the thickness variation caused by the transition region is compensated for by increasing the thickness of the epitaxial layer.
For a MOSFET device with the withstand voltage reaching 1500V, the thickness of the epitaxial layer is at least more than 170 micrometers, and correspondingly, the transition area between the epitaxial layer and the substrate accounts for more than 20% of the thickness of the whole epitaxial layer, so that the effective utilization rate of the epitaxial layer is greatly reduced. Because the thickness of the epitaxial layer is too thick, the processing efficiency of the epitaxial layer is low, the difficulty is high, more defects are formed at the edge of a wafer in the epitaxial growth process with high thickness, the wafer is seriously warped, and the wafer has higher fragmentation rate in the production process of the subsequent process.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a power semiconductor device and a method of manufacturing the same, in which the thickness of a transition region is reduced by reducing a concentration difference between a semiconductor substrate and an epitaxial layer, so that the thickness of the epitaxial layer can be reduced and the yield of a product can be improved.
According to a first aspect of the present invention, there is provided a method for manufacturing a power semiconductor device, comprising: forming an epitaxial layer on a first surface of a semiconductor substrate, the semiconductor substrate and the epitaxial layer being of a first doping type and having a first doping concentration and a second doping concentration, respectively; forming a gate stack on the epitaxial layer, wherein the gate stack comprises a gate dielectric layer and a gate conductor, and the gate dielectric layer is clamped between the gate conductor and the epitaxial layer; forming a body region in the epitaxial layer, wherein the body region is of a second doping type, and the second doping type is opposite to the first doping type; forming a first doping region in the body region, wherein the first doping region is of the first doping type; forming a first contact to the first doped region; doping the semiconductor substrate from a second surface of the semiconductor substrate such that the first doping concentration is maintained near a first surface of the semiconductor substrate, the second surface and the first surface being opposite each other, increasing from the first doping concentration to a third doping concentration near the second surface of the semiconductor substrate; and forming a second contact on a second surface of the semiconductor substrate, wherein a transition region in which the doping concentration changes from the first doping concentration to the second doping concentration is formed between the semiconductor substrate and the epitaxial layer, the first doping concentration being 5 to 100 times the second doping concentration.
Preferably, the resistivity of the semiconductor substrate before doping is between 1 ohm cm and 10 ohm cm.
Preferably, the resistivity of the epitaxial layer is between 50 ohm cm and 90 ohm cm.
Preferably, the first doping type is N-type, and the second doping type is P-type.
Preferably, the first doping concentration is 5e14 per cubic centimeter to 5e15 per cubic centimeter.
Preferably, the second doping concentration is 5e13 per cubic centimeter to 1e14 per cubic centimeter.
Preferably, the first doping type is P-type, and the second doping type is N-type.
Preferably, the first doping concentration is 1.3e15 per cubic centimeter to 1.5e16 per cubic centimeter.
Preferably, the second doping concentration is 1.5e14 per cubic centimeter to 2.6e14 per cubic centimeter.
Preferably, the thickness of the epitaxial layer is between 50 microns and 140 microns.
Preferably, before the step of doping the semiconductor, further comprising thinning from the second surface of the semiconductor substrate.
Preferably, the semiconductor substrate is thinned to a predetermined thickness.
Preferably, the doping concentration of the epitaxial layer is uniformly distributed along the thickness direction thereof.
Preferably, the first doping concentration minimum is 5 to 100 times the second doping concentration minimum.
Preferably, the first doping concentration maximum is 5 to 100 times the second doping concentration maximum.
Preferably, the transition zone has a thickness of less than 20 microns.
Preferably, the withstand voltage value of the power semiconductor device is 1200V to 1800V.
According to a second aspect of the present invention, there is provided a power semiconductor device comprising: an epitaxial layer on a first surface of a semiconductor substrate, the semiconductor substrate and the epitaxial layer being of a first doping type, the semiconductor substrate having a first doping concentration near the first surface and a third doping concentration near a second surface, the second surface and the first surface being opposite each other, the epitaxial layer having a second doping concentration; a transition region between the semiconductor substrate and the epitaxial layer, the transition region having a doping concentration that varies from the first doping concentration to the second doping concentration; the gate stack layer is positioned on the epitaxial layer and comprises a gate dielectric layer and a gate conductor, and the gate dielectric layer is clamped between the gate conductor and the epitaxial layer; the body region is positioned in the epitaxial layer, and is of a second doping type, and the second doping type is opposite to the first doping type; the first doping region is positioned in the body region and is of the first doping type; a first contact in contact with the first doped region; and a second contact on the second surface of the semiconductor substrate, wherein the first doping concentration is 5 to 100 times the second doping concentration, and the third doping concentration is greater than the first doping concentration.
Preferably, the resistivity of the semiconductor substrate before doping is between 1 ohm cm and 10 ohm cm.
Preferably, the resistivity of the epitaxial layer is between 50 ohm cm and 90 ohm cm.
Preferably, the first doping type is N-type, and the second doping type is P-type.
Preferably, the first doping concentration is 5e14 per cubic centimeter to 5e15 per cubic centimeter.
Preferably, the second doping concentration is 5e13 per cubic centimeter to 1e14 per cubic centimeter.
Preferably, the first doping type is P-type, and the second doping type is N-type.
Preferably, the first doping concentration is 1.3e15 per cubic centimeter to 1.5e16 per cubic centimeter.
Preferably, the second doping concentration is 1.5e14 per cubic centimeter to 2.6e14 per cubic centimeter.
Preferably, the thickness of the epitaxial layer is between 50 microns and 140 microns.
Preferably, the doping concentration of the epitaxial layer is uniformly distributed along the thickness direction thereof.
Preferably, the semiconductor substrate is thinned to a predetermined thickness prior to doping.
Preferably, the first doping concentration minimum is 5 to 100 times the second doping concentration minimum.
Preferably, the first doping concentration maximum is 5 to 100 times the second doping concentration maximum.
Preferably, the transition zone has a thickness of less than 20 microns.
Preferably, the withstand voltage value of the power semiconductor device is 1200V to 1800V.
According to the manufacturing method of the power semiconductor device, the first doping concentration of the semiconductor substrate is 5 to 100 times that of the second doping concentration of the epitaxial layer.
In the prior art, for example, the doping concentration of the semiconductor substrate is 1e18 per cubic centimeter to 5e19 per cubic centimeter, and the doping concentration of the epitaxial layer is 5e13 per cubic centimeter to 1e14 per cubic centimeter, the former is 5 orders of magnitude higher than the latter. For example, the thickness of the transition zone may be up to 30 microns.
Compared with the prior art, the invention reduces the doping concentration difference between the semiconductor substrate and the epitaxial layer. In the present invention, for example, the semiconductor substrate has a doping concentration of 5e14 per cubic centimeter to 5e15 per cubic centimeter, and the epitaxial layer has a doping concentration of 5e13 per cubic centimeter to 1e14 per cubic centimeter, the former being 5 to 100 times that of the latter. Accordingly, the difference in doping concentration between the semiconductor substrate and the epitaxial layer is significantly reduced, so that the thickness of the transition region between the two can be reduced. For example, the thickness of the transition region is less than 20 microns, e.g., reduced to 10 microns. As the thickness of the transition region between the epitaxial layer and the semiconductor substrate is reduced, the thickness of the epitaxial layer may also be correspondingly reduced, for example, from 170 microns to 120 microns for a MOSFET power device with a withstand voltage of 1500V. The thickness of the epitaxial layer is about 2/3 of that of the epitaxial layer in the conventional method. The method can avoid the defect and warpage of the wafer edge caused by the overgrowth of the epitaxial layer in the traditional method, reduce the process difficulty and reduce the fragment rate in the preparation process of the subsequent process.
In a preferred embodiment, during the manufacturing process, an epitaxial layer is formed on the semiconductor substrate and the body region and the first doped region are formed, and at the end of the manufacturing process, the semiconductor substrate is doped to increase its doping concentration. The method provided by the embodiment of the invention can reduce the thickness of the transition area, thereby meeting the requirement of the product yield. The method can also meet the requirement of reducing on-resistance because the doping concentration of the semiconductor substrate is increased in the final product.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 to 6 are schematic cross-sectional views showing respective stages in a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The invention may be embodied in various forms, some examples of which are described below.
Fig. 1 to 6 are schematic cross-sectional views showing respective stages in a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
As shown in fig. 1, an epitaxial layer 102 is formed on a semiconductor substrate 101. In this embodiment, the first doping concentration Csub of the semiconductor substrate 101 is 5 to 100 times the second doping concentration Cep of the epitaxial layer 102. A transition region 131 is formed between the semiconductor substrate 101 and the epitaxial layer 102. The doping concentration of the transition region 131 changes from the first doping concentration Csub to the second doping concentration Cep.
The semiconductor substrate 101 may be any suitable type of semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, or the like. In this embodiment, the semiconductor substrate 101 may be a conventional Czochralski silicon substrate having a crystal orientation <100 >. The epitaxial layer 102 is, for example, a silicon layer doped in situ and having a uniform doping concentration in the thickness direction. The thickness of epitaxial layer 102 is between 50 microns and 120 microns.
As a non-limiting example, semiconductor substrate 101 is a silicon substrate having a resistivity of between 1 ohm-cm and 10 ohm-cm and epitaxial layer 102 is a silicon epitaxial layer having a resistivity of between 50 ohm-cm and 90 ohm-cm.
The epitaxial layer 102 is doped with the same type as the semiconductor substrate 101. In one embodiment, the power semiconductor device is an N-type device, the semiconductor substrate 101 has a doping type of N-type, preferably a doping concentration of 5e14 per cubic centimeter to 5e15 per cubic centimeter, and the epitaxial layer 102 has a doping type of N-type, preferably a doping concentration of 5e13 per cubic centimeter to 1e14 per cubic centimeter. In an alternative embodiment, the power semiconductor device is a P-type device, the semiconductor substrate 101 is doped with a P-type dopant, preferably with a dopant concentration of 1.3e15 per cubic centimeter to 1.5e16 per cubic centimeter, and the epitaxial layer 102 is doped with a P-type dopant, preferably with a dopant concentration of 1.5e14 per cubic centimeter to 2.6e14 per cubic centimeter.
In addition, it will be appreciated by those skilled in the art that the resistivity of the epitaxial layer 102 is determined by the design performance of the MOSFET device and its application.
Then, a gate stack is formed on the front side of the epitaxial layer 102, as shown in fig. 3. The gate stack comprises a gate dielectric layer 103 on the epitaxial layer 102 and a gate conductor layer 104 on the gate dielectric layer 103.
In this step, the front surface (or upper surface) of the epitaxial layer 102 is cleaned, and then an oxide layer (not shown) is grown on the front surface of the epitaxial layer 102, for example, by thermal oxidation. For example, the oxide layer may be grown under an oxygen or wet oxygen atmosphere. The oxide layer has a thickness of 4000 angstroms to 10000 angstroms.
After the oxide layer is formed, the formation of isolation structures, such as shallow trench isolation or field oxide regions, for the MOSFET devices in epitaxial layer 102 may continue, as well as the formation of a voltage divider ring structure. For example, the split ring structure may be fabricated using photolithography, development, ion implantation, annealing, and the like. The isolation structure is used to define the active region (not shown) of the MOSFET. The surface of epitaxial layer 102 is exposed in the active region.
Further, a gate dielectric layer 103 is formed on the surface of the epitaxial layer 102 by thermal oxidation. For example, the material of gate dielectric layer 103 may be silicon dioxide, which may be between 500 and 1500 angstroms thick.
Further, a polysilicon layer is deposited on gate dielectric layer 103, and the polysilicon layer may have a thickness of between 5000 and 8000 angstroms. The polysilicon layer is N-type in doping type and has a resistivity of between 2 ohms per square and 30 ohms per square. The polysilicon layer is patterned using photolithography, development, etching, etc., to form the gate conductor 104 of the MOSFET device.
Then, a body region 105 is formed in the epitaxial layer 102 and a first doped region 106 is formed in the body region 105, as shown in fig. 3. The first doped region 106 is, for example, the source region of a MOSFET device.
In this step, a photoresist mask is formed, for example, using photolithography. Then, a first ion implantation, annealing, etc. process is performed through the photoresist mask, forming a body region 105 in the epitaxial layer 102. The doping type of the body region 105 is opposite to that of the semiconductor substrate 101. After the first ion implantation, the photoresist mask is removed, for example, by ashing or dissolution.
Further, the photoresist mask region is formed, for example, using photolithography. Then, a second ion implantation, annealing, etc. process is performed through the photoresist mask, forming a first doped region 106 in the body region 105. The doping type of the first doped region 106 is the same as that of the semiconductor substrate 101. After the second ion implantation, the photoresist mask is removed, for example, by ashing or dissolution.
In the above step, the regions of the body region 105 and the first doped region 106 are defined using a photoresist mask such that at least a portion of the body region 105 is located below the gate conductor 104 and adjacent to the epitaxial layer 102 and the first doped region 105, respectively, and thus may serve as a channel region of the MOSFET device.
An interlayer dielectric layer 107 is then formed over the gate conductor 104, as shown in fig. 4. The interlayer dielectric layer 107 may be, for example, silicon dioxide (SIO 2) or borophosphosilicate glass (BPSG), and has a total thickness of between 8000 a and 15000 a.
Further, a wiring contact hole 121 is formed on the interlayer dielectric layer 107 by photolithography and etching or the like. The contact hole 121 exposes at least a portion of the surfaces of the body region 105 and the first doped region 106.
Then, a metal layer is deposited on the device surface to fill the contact holes 121, thereby forming the first contacts 108, as shown in fig. 5. The first contact 108 is composed of, for example, aluminum or aluminum silicon copper, but is not limited thereto.
The first contact 108 is a contact layer formed by patterning a metal layer for providing a gate contact and a source contact. Only the source contact through the contact hole in the interlayer dielectric layer 107 to the first doped region 106 (i.e., the source region) is shown in the figure. It will be appreciated that this step also forms a gate contact through the contact hole in the interlayer dielectric layer 107 to the gate conductor 104.
Then, a second contact 109 is formed on the second surface of the semiconductor substrate 101, as shown in fig. 6. In this step, the semiconductor substrate 101 is thinned from the second surface of the semiconductor substrate 101, for example, by grinding and etching until the thickness of the remaining portion of the semiconductor substrate 101 is a predetermined thickness, and the remaining portion of the semiconductor substrate 102 and the epitaxial layer 102 together serve as a current path and a voltage supporting region of the MOSFET device.
Further, the surface of the substrate holding region is doped from the second surface of the semiconductor substrate 101 with the same doping type as the substrate doping type, thereby increasing the doping concentration near the second surface of the semiconductor substrate 101 from the first doping concentration to the third doping concentration.
Further, a metal layer is deposited on the second surface of the semiconductor substrate 101, thereby forming a second contact 109, as shown in fig. 5. The second contact 109 is composed of, for example, aluminum or aluminum silicon copper, but is not limited thereto. In this embodiment, the second contact 109 is a drain contact.
Compared with the prior art, the doping concentration difference between the semiconductor substrate and the epitaxial layer is obviously reduced, so that the thickness of a transition region between the semiconductor substrate and the epitaxial layer can be reduced. As the thickness of the transition region between the epitaxial layer and the semiconductor substrate is reduced, the thickness of the epitaxial layer can be reduced accordingly. The withstand voltage parameter of the power semiconductor device is 1200V to 1800V.
In the present invention, for example, the doping concentration of the semiconductor substrate is 5e14 per cubic centimeter to 5e15 per cubic centimeter for an N-type power semiconductor device, the doping concentration of the epitaxial layer is 5e13 per cubic centimeter to 1e14 per cubic centimeter, the doping concentration of the semiconductor substrate is 1.3e15 per cubic centimeter to 1.5e16 per cubic centimeter for a P-type power semiconductor device, and the doping concentration of the epitaxial layer is 1.5e14 per cubic centimeter to 2.6e14 per cubic centimeter. The doping concentration of the semiconductor substrate is 5 to 100 times that of the epitaxial layer. Accordingly, the difference in doping concentration between the semiconductor substrate and the epitaxial layer is significantly reduced, so that the thickness of the transition region between the two can be reduced. For example, the thickness of the transition region is less than 20 microns, e.g., reduced to 10 microns. As the thickness of the transition region between the epitaxial layer and the semiconductor substrate is reduced, the thickness of the epitaxial layer may also be correspondingly reduced, for example, from 170 microns to 120 microns for a MOSFET power device with a withstand voltage of 1500V. The thickness of the epitaxial layer is about 2/3 of that of the epitaxial layer in the conventional method. The method can avoid the defect and warpage of the wafer edge caused by the overgrowth of the epitaxial layer in the traditional method, reduce the process difficulty and reduce the fragment rate in the preparation process of the subsequent process.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (33)
1. A method for manufacturing a power semiconductor device, comprising:
forming an epitaxial layer on a first surface of a semiconductor substrate, the semiconductor substrate and the epitaxial layer being of a first doping type and having a first doping concentration and a second doping concentration, respectively;
forming a gate stack on the epitaxial layer, wherein the gate stack comprises a gate dielectric layer and a gate conductor, and the gate dielectric layer is clamped between the gate conductor and the epitaxial layer;
forming a body region in the epitaxial layer, wherein the body region is of a second doping type, and the second doping type is opposite to the first doping type;
forming a first doping region in the body region, wherein the first doping region is of the first doping type;
forming a first contact to the first doped region;
doping the semiconductor substrate from a second surface of the semiconductor substrate such that the first doping concentration is maintained near a first surface of the semiconductor substrate, the second surface and the first surface being opposite each other, increasing from the first doping concentration to a third doping concentration near the second surface of the semiconductor substrate; and
a second contact is formed on a second surface of the semiconductor substrate,
wherein a transition region with doping concentration changing from the first doping concentration to the second doping concentration is formed between the semiconductor substrate and the epitaxial layer,
the first doping concentration is 5 to 100 times the second doping concentration.
2. The method of claim 1, wherein the semiconductor substrate has a resistivity of between 1 ohm cm and 10 ohm cm before doping.
3. The method of claim 1, wherein the epitaxial layer has a resistivity of between 50 and 90 ohm cm.
4. The method of claim 1, wherein the first doping type is N-type and the second doping type is P-type.
5. The method of claim 4, wherein the first doping concentration is 5e14 per cubic centimeter to 5e15 per cubic centimeter.
6. The method of claim 4 or 5, wherein the second doping concentration is 5e13 per cubic centimeter to 1e14 per cubic centimeter.
7. The method of claim 1, wherein the first doping type is P-type and the second doping type is N-type.
8. The method of claim 7, wherein the first doping concentration is 1.3e15 per cubic centimeter to 1.5e16 per cubic centimeter.
9. The method of claim 7 or 8, wherein the second doping concentration is 1.5e14 per cubic centimeter to 2.6e14 per cubic centimeter.
10. The method of claim 1, wherein the epitaxial layer has a thickness of between 50 microns and 140 microns.
11. The method of claim 1, further comprising thinning from the second surface of the semiconductor substrate prior to the step of doping the semiconductor.
12. The method of claim 11, wherein the semiconductor substrate is thinned to a predetermined thickness.
13. The method of claim 1, wherein the doping concentration of the epitaxial layer is uniformly distributed along its thickness.
14. The method of claim 1, wherein the first doping concentration minimum is 5 to 100 times the second doping concentration minimum.
15. The method of claim 1, wherein the first doping concentration maximum is 5 to 100 times the second doping concentration maximum.
16. The method of claim 1, wherein the transition region has a thickness of less than 20 microns.
17. The method of claim 1, wherein the power semiconductor device has a withstand voltage value of 1200V to 1800V.
18. A power semiconductor device, comprising:
an epitaxial layer on a first surface of a semiconductor substrate, the semiconductor substrate and the epitaxial layer being of a first doping type, the semiconductor substrate having a first doping concentration near the first surface and a third doping concentration near a second surface, the second surface and the first surface being opposite each other, the epitaxial layer having a second doping concentration;
a transition region between the semiconductor substrate and the epitaxial layer, the transition region having a doping concentration that varies from the first doping concentration to the second doping concentration;
the gate stack layer is positioned on the epitaxial layer and comprises a gate dielectric layer and a gate conductor, and the gate dielectric layer is clamped between the gate conductor and the epitaxial layer;
the body region is positioned in the epitaxial layer, and is of a second doping type, and the second doping type is opposite to the first doping type;
the first doping region is positioned in the body region and is of the first doping type;
a first contact in contact with the first doped region; and
a second contact on a second surface of the semiconductor substrate,
wherein the first doping concentration is 5 to 100 times the second doping concentration, and the third doping concentration is greater than the first doping concentration.
19. The power semiconductor device of claim 18 wherein said semiconductor substrate has a resistivity of between 1 and 10 ohm cm prior to doping.
20. The power semiconductor device of claim 18 wherein the epitaxial layer has a resistivity of between 50 and 90 ohm-cm.
21. The power semiconductor device of claim 18 wherein said first doping type is N-type and said second doping type is P-type.
22. The power semiconductor device of claim 21 wherein said first doping concentration is 5e14 per cubic centimeter to 5e15 per cubic centimeter.
23. The power semiconductor device of claim 21 or 22, wherein the second doping concentration is 5e13 per cubic centimeter to 1e14 per cubic centimeter.
24. The power semiconductor device of claim 18 wherein said first doping type is P-type and said second doping type is N-type.
25. The power semiconductor device of claim 24 wherein said first doping concentration is 1.3e15 per cubic centimeter to 1.5e16 per cubic centimeter.
26. The power semiconductor device of claim 24 or 25, wherein the second doping concentration is 1.5e14 per cubic centimeter to 2.6e14 per cubic centimeter.
27. The power semiconductor device of claim 18 wherein said epitaxial layer has a thickness of between 50 microns and 140 microns.
28. The power semiconductor device of claim 18 wherein the doping concentration of the epitaxial layer is uniformly distributed along its thickness.
29. The power semiconductor device of claim 18 wherein said semiconductor substrate is thinned to a predetermined thickness prior to doping.
30. The power semiconductor device of claim 18 wherein the first doping concentration minimum is 5 to 100 times the second doping concentration minimum.
31. The power semiconductor device of claim 18 wherein the first doping concentration maximum is 5 to 100 times the second doping concentration maximum.
32. The power semiconductor device of claim 18 wherein said transition region has a thickness of less than 20 microns.
33. The power semiconductor device according to claim 18, wherein a withstand voltage value of the power semiconductor device is 1200V to 1800V.
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| US5872374A (en) * | 1996-03-29 | 1999-02-16 | Motorola, Inc. | Vertical semiconductor device |
| JP2015002329A (en) * | 2013-06-18 | 2015-01-05 | シャープ株式会社 | Epitaxial wafer, method for manufacturing the same, and nitride semiconductor device |
| JP2016044115A (en) * | 2014-08-27 | 2016-04-04 | 三菱電機株式会社 | Silicon carbide epitaxial wafer, silicon carbide semiconductor device, and production method of silicon carbide epitaxial wafer |
| CN207265060U (en) * | 2017-08-11 | 2018-04-20 | 杭州士兰集成电路有限公司 | Power semiconductor |
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| JP2009302510A (en) * | 2008-03-03 | 2009-12-24 | Fuji Electric Device Technology Co Ltd | Trench gate type semiconductor device, and method of manufacturing the same |
| US20120080748A1 (en) * | 2010-09-30 | 2012-04-05 | Force Mos Technology Co., Ltd. | Trench mosfet with super pinch-off regions |
| DE112015003483T5 (en) * | 2014-07-30 | 2017-04-20 | Mitsubishi Electric Corporation | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE |
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| US5872374A (en) * | 1996-03-29 | 1999-02-16 | Motorola, Inc. | Vertical semiconductor device |
| JP2015002329A (en) * | 2013-06-18 | 2015-01-05 | シャープ株式会社 | Epitaxial wafer, method for manufacturing the same, and nitride semiconductor device |
| JP2016044115A (en) * | 2014-08-27 | 2016-04-04 | 三菱電機株式会社 | Silicon carbide epitaxial wafer, silicon carbide semiconductor device, and production method of silicon carbide epitaxial wafer |
| CN207265060U (en) * | 2017-08-11 | 2018-04-20 | 杭州士兰集成电路有限公司 | Power semiconductor |
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